From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by sourceware.org (Postfix) with ESMTPS id 34AE83857724 for ; Tue, 24 Oct 2023 08:53:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 34AE83857724 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=redhat.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=redhat.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 34AE83857724 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698137589; cv=none; b=iAtjsF1ZYGff3pYXK84EeEKjnlXNpoRkqAkxGNLd+rmexcLaNYL5Wo0HYWnqdrAP4HPq0wuG0GGWKRGGAQYcrjIT9iG0VxxMGrBFHAf3FYtlUNt9K7w454b+wMm6HReK1oWXC69RZ9C9FD+2+6lnX0CRAxkLkczU2onJ0Wf5JkQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698137589; c=relaxed/simple; bh=kjjGWPVunB0xSzTavoHOnqpWKXg1wCrGA/1FTmHsVq0=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=ZRr3a1+jqv8V7DlkGUNEoeg8hspVpjE3r5OoXZ4ADaoKgw5rt1M69Wdf6lzZsbzn4E+J2iZo8mL9ScJu0vovqbyV4M5e9uloluJGyg83iy1Fz/7Pwyb58jiiHc/dTVBPoYvS0XF5Sdh1dcbqf37k3vsSND+IkRfv3PJ/AaqFGQY= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1698137586; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=IxVa1Z6D0tevc6OlTr6V1bumao9RS/0esQmWq3y8X5A=; b=BFHwGW0hyyIfO3ZNv3WCa9lmyotj630Ur2yBuCcQxN6xF7kxDlG/VgCs+cLUCyCb/UWOow /4vLzkPTS3hYaAfYfrDGZ3g9B0GWU51eyoSxSZOxw8Ag/Zq8cIg2s1P5YqV0GAUyd0mcBs l3SmHQAkrTeDbFh6KNUHuhF/4eBAzpg= Received: from mail-ed1-f70.google.com (mail-ed1-f70.google.com [209.85.208.70]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-436-J-6Y7bVNPDiKRwF1Ut-Biw-1; Tue, 24 Oct 2023 04:53:05 -0400 X-MC-Unique: J-6Y7bVNPDiKRwF1Ut-Biw-1 Received: by mail-ed1-f70.google.com with SMTP id 4fb4d7f45d1cf-531373ea109so2698374a12.3 for ; Tue, 24 Oct 2023 01:53:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698137584; x=1698742384; h=mime-version:message-id:date:references:in-reply-to:subject:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=IxVa1Z6D0tevc6OlTr6V1bumao9RS/0esQmWq3y8X5A=; b=TX3L3f/wiVrmfiWHW6paWFXElPxIr5kDhwBHHRI4rkkCP1T9rLfBZ3NYJCFh+y7cTU 2kG3GS0a6lbT8kLzdb1zZ2RZu1xx4QbmkTtrmGSgrKbNprq6+VuDM7e/tV74F5DX/n5B OZYlVnt1g5BChsBZdFENnw1rnnlLJVLi1ST9eplNJTZJi3UVzDTl3YJt0R4rkhO4lcy2 H2ird0pgiHgZQeBxx1tVBXd8bweBFBXc3Xdl/eK1zVs/eL1sHSgTx76lmaSlRO/MW9E8 b143XAFcgFZ5Lu130ouENv5tHES0veCEcgiE4weIXfIWNXPmnjIAHahLfqwocDBRcLa0 Lzlw== X-Gm-Message-State: AOJu0YzUM9qlEN+LBSEWfqefU5+07WxAomNlP+P2p2NKD/jG9oY6QvQd V6GLem2f1qJLS/1dgV8Gcx4Ca8IJx2StKXT//tl5qWDyERHDWbbGjpN6OrOoQnxRFQ29QTs5Wtq JGA947gnXFNpiMRUcLII/+GFTwBXCog== X-Received: by 2002:a50:d795:0:b0:53e:467c:33f1 with SMTP id w21-20020a50d795000000b0053e467c33f1mr9104962edi.8.1698137583849; Tue, 24 Oct 2023 01:53:03 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF58//pz7I00onRMiMzfncmgN7BNAU0voRaDDjZOG/JPHOY4jJFPHGEYhyH5JvqxJnZTLH36g== X-Received: by 2002:a50:d795:0:b0:53e:467c:33f1 with SMTP id w21-20020a50d795000000b0053e467c33f1mr9104934edi.8.1698137583476; Tue, 24 Oct 2023 01:53:03 -0700 (PDT) Received: from localhost ([31.111.84.209]) by smtp.gmail.com with ESMTPSA id cy8-20020a0564021c8800b0054018a76825sm4760906edb.8.2023.10.24.01.53.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Oct 2023 01:53:03 -0700 (PDT) From: Andrew Burgess To: Carl Love , Carl Love , gdb-patches@sourceware.org, UlrichWeigand , keiths@redhat.com Subject: Re: [PATCH 2/2] PowerPC, Fix-test-gdb.base-store.exp In-Reply-To: <4e8742f920adecfedc347e386bf7f65f3ec62291.camel@linux.ibm.com> References: <6f9c8fa20962129048384d74f6f15d1b37d255ed.camel@us.ibm.com> <0a1d201b8868269496bcb15fd22811607e93a0c5.camel@us.ibm.com> <878r82hbwl.fsf@redhat.com> <4e8742f920adecfedc347e386bf7f65f3ec62291.camel@linux.ibm.com> Date: Tue, 24 Oct 2023 09:53:01 +0100 Message-ID: <87v8aw2yhe.fsf@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Carl Love writes: > GDB maintainers: > > Ver 2: In the new function, rs6000_value_from_register, moved the > declaration of frame to where it gets initialized. Patch was retested > on Power10. > > This is the second patch which fixes the 128-bit floating point > register mappings. This fixes the remaining three issues with the > store.exp test. > > Carl > > ----------------------------------------- > rs6000, Fix test gdb.base/store.exp > > The test currently fails for IEEE 128-bit floating point types. PowerPC > supports the IBM double 128-bit floating point format and IEEE 128-bit > format. The IBM double 128-bit floating point format uses two 64-bit > floating point registers to store the 128-bit value. The IEEE 128-bit > floating point format stores the value in a single 128-bit vector-scalar > register (vsr). > > The various floating point values, 32-bit float, 64-bit double, IBM double > 128-bit float and IEEE 128-bit floating point numbers are all mapped to the > DWARF fpr numbers. The issue is the IEEE 128-bit floating point values are > actually stored in a vsr not the fprs. This patch changes the register > mapping for the vsrs from the fpr to the vsr registers so the value is > properly accessed by GDB. The functions rs6000_linux_register_to_value, > rs6000_linux_value_to_register, rs6000_linux_value_from_register check if > the value is an IEEE 128-bit floating point value and adjust the register > number as needed. The test in function rs6000_convert_register_p is fixed > so it is only true for floating point values. > > This patch fixes three regression tests in gdb.base/store.exp. If this doesn't depend on patch #1 then feel free to go ahead an merge. Approved-By: Andrew Burgess Thanks, Andrew > > The patch has been tested on Power 8 LE/BE, Power 9 LE/BE and Power 10 LE > with no regressions. > --- > gdb/ppc-linux-tdep.c | 4 +++ > gdb/rs6000-tdep.c | 65 +++++++++++++++++++++++++++++++++++++++++++- > 2 files changed, 68 insertions(+), 1 deletion(-) > > diff --git a/gdb/ppc-linux-tdep.c b/gdb/ppc-linux-tdep.c > index dc03430e2af..fac56d961cb 100644 > --- a/gdb/ppc-linux-tdep.c > +++ b/gdb/ppc-linux-tdep.c > @@ -63,6 +63,7 @@ > #include > #include "elf-bfd.h" > #include "producer.h" > +#include "target-float.h" > > #include "features/rs6000/powerpc-32l.c" > #include "features/rs6000/powerpc-altivec32l.c" > @@ -2102,6 +2103,9 @@ rs6000_linux_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num) > /* FIXME: jimb/2004-05-05: What should we do when the debug info > specifies registers the architecture doesn't have? Our > callers don't check the value we return. */ > + /* Map dwarf register numbers for floating point, double, IBM double and > + IEEE 128-bit floating point to the fpr range. Will have to fix the > + mapping for the IEEE 128-bit register numbers later. */ > return tdep->ppc_fp0_regnum + (num - 32); > else if (77 <= num && num < 77 + 32) > return tdep->ppc_vr0_regnum + (num - 77); > diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c > index 23397d037ae..186646673f0 100644 > --- a/gdb/rs6000-tdep.c > +++ b/gdb/rs6000-tdep.c > @@ -2676,7 +2676,25 @@ rs6000_convert_register_p (struct gdbarch *gdbarch, int regnum, > && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs > && type->code () == TYPE_CODE_FLT > && (type->length () > - != builtin_type (gdbarch)->builtin_double->length ())); > + == builtin_type (gdbarch)->builtin_float->length ())); > +} > + > +static int > +ieee_128_float_regnum_adjust (struct gdbarch *gdbarch, struct type *type, > + int regnum) > +{ > + ppc_gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); > + > + /* If we have the an IEEE 128-bit floating point value, need to map the > + register number to the corresponding VSR. */ > + if (tdep->ppc_vsr0_regnum != -1 > + && regnum >= tdep->ppc_fp0_regnum > + && regnum < (tdep->ppc_fp0_regnum + ppc_num_fprs) > + && (gdbarch_long_double_format (gdbarch) == floatformats_ieee_quad) > + && (type->length() == 16)) > + regnum = regnum - tdep->ppc_fp0_regnum + tdep->ppc_vsr0_regnum; > + > + return regnum; > } > > static int > @@ -2691,6 +2709,10 @@ rs6000_register_to_value (frame_info_ptr frame, > > gdb_assert (type->code () == TYPE_CODE_FLT); > > + /* We have an IEEE 128-bit float -- need to change regnum mapping from > + fpr to vsr. */ > + regnum = ieee_128_float_regnum_adjust (gdbarch, type, regnum); > + > if (!get_frame_register_bytes (frame, regnum, 0, > gdb::make_array_view (from, > register_size (gdbarch, > @@ -2715,11 +2737,51 @@ rs6000_value_to_register (frame_info_ptr frame, > > gdb_assert (type->code () == TYPE_CODE_FLT); > > + /* We have an IEEE 128-bit float -- need to change regnum mapping from > + fpr to vsr. */ > + regnum = ieee_128_float_regnum_adjust (gdbarch, type, regnum); > + > target_float_convert (from, type, > to, builtin_type (gdbarch)->builtin_double); > put_frame_register (frame, regnum, to); > } > > +static struct value * > +rs6000_value_from_register (struct gdbarch *gdbarch, struct type *type, > + int regnum, struct frame_id frame_id) > +{ > + int len = type->length (); > + struct value *value = value::allocate (type); > + > + /* We have an IEEE 128-bit float -- need to change regnum mapping from > + fpr to vsr. */ > + regnum = ieee_128_float_regnum_adjust (gdbarch, type, regnum); > + > + value->set_lval (lval_register); > + frame_info_ptr frame = frame_find_by_id (frame_id); > + > + if (frame == NULL) > + frame_id = null_frame_id; > + else > + frame_id = get_frame_id (get_next_frame_sentinel_okay (frame)); > + > + VALUE_NEXT_FRAME_ID (value) = frame_id; > + VALUE_REGNUM (value) = regnum; > + > + /* Any structure stored in more than one register will always be > + an integral number of registers. Otherwise, you need to do > + some fiddling with the last register copied here for little > + endian machines. */ > + if (type_byte_order (type) == BFD_ENDIAN_BIG > + && len < register_size (gdbarch, regnum)) > + /* Big-endian, and we want less than full size. */ > + value->set_offset (register_size (gdbarch, regnum) - len); > + else > + value->set_offset (0); > + > + return value; > +} > + > /* The type of a function that moves the value of REG between CACHE > or BUF --- in either direction. */ > typedef enum register_status (*move_ev_register_func) (struct regcache *, > @@ -8337,6 +8399,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) > set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p); > set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value); > set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register); > + set_gdbarch_value_from_register (gdbarch, rs6000_value_from_register); > > set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum); > set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum); > -- > 2.37.2