From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by sourceware.org (Postfix) with ESMTPS id E33FA397182C for ; Wed, 20 Jan 2021 20:23:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org E33FA397182C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=andrew.burgess@embecosm.com Received: by mail-wr1-x42c.google.com with SMTP id q7so2385225wre.13 for ; Wed, 20 Jan 2021 12:23:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JxBZOxQTgCC/h7MSpGtyfGJBuO59jXtC/Bn3Vr1vb78=; b=BBfsanFF0gFkOQGh1XFvTQgd0LAmGfzSutvEsl9g3dLcdETNypzPxlk6mvlQnxxw1N 4N+ZFFVJaSew9w6xoL8dgiiKaUvO0+mWHY6QWl6CG6XgPwOWA4oC0LVoWkkytlVNL6tY LUsD0dCwDryOJcA1/HVfQTvT81AhZmp8AFgHFIls77V9ZHxAKbmkx+LTrOvVoIo/Z8j0 5TFEHlN6CQ+TX9BbfGZYEL8jI6IzLypz0wv+sPCIIMQhEMrch7PV2isCWfVLaCR1aRex AcMpXn1mB/OkmXgueKRW/gad2Jpp6TLLbq094+jsh0sDx8iArYrtDALTm+tkZsHyuILO ax2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JxBZOxQTgCC/h7MSpGtyfGJBuO59jXtC/Bn3Vr1vb78=; b=uOpgqq9N1qFsfKZhSANatIRcj4xTmiGn7MfRXLLVpcnX/96FI75goX2DHQv3bwfHFB FLaAf96XEvX9pqnUKNJ9Ckz1MNyYHF42AvtOPV2aW0DJJ8qOUAsbpJqTbt8fzLXfhtic C16EHJUNAOO54vnbJqNk4bT3LqabKSyDvGE+OqYc48QaMJytIKLQKucD0yl4AJ1FAOUB w/Z+K7mdLOU2qnK/DWldCCnyYC1tHGVLK9W29gRNX/yVQUKTwVnK8r4iX7/SXg+jH8QN y+fJJa+occWifYA/d31ncmmXieY82TlP4NKksb36TX4KjyibdkkDuPmlzgdpKpmboVpC xXLw== X-Gm-Message-State: AOAM5325JJK3lbA8tE8YKBmygIYjnlV05M/KpCi+9o9Hh3OjIeAT9J8h ckaVtDuMGkXNdrqrplv1dQE2k2mY2dp0eQ== X-Google-Smtp-Source: ABdhPJyumxmxC6JducUViYK2wv6jtkenaAX6zkqJpzVaMf4uVZQfXhxUwM1/B2ZaC+1idzjhwnzLrA== X-Received: by 2002:adf:c106:: with SMTP id r6mr10639677wre.175.1611174209868; Wed, 20 Jan 2021 12:23:29 -0800 (PST) Received: from localhost (host86-180-62-229.range86-180.btcentralplus.com. [86.180.62.229]) by smtp.gmail.com with ESMTPSA id z14sm5793051wrm.5.2021.01.20.12.23.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Jan 2021 12:23:29 -0800 (PST) From: Andrew Burgess To: gdb-patches@sourceware.org, binutils@sourceware.org Cc: Fredrik Hederstierna , Andrew Burgess Subject: [PATCHv2 7/9] gdb/riscv: make riscv target description names global Date: Wed, 20 Jan 2021 20:23:13 +0000 Message-Id: <93b9873e8ef7eadf0ba73d901cbfb693baedd97d.1611172468.git.andrew.burgess@embecosm.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Jan 2021 20:23:32 -0000 A later commit will need the names of the RISC-V target description features in files other than riscv-tdep.c. This commit just makes the names global strings that can be accessed from other riscv-*.c files. There should be no user visible changes after this commit. gdb/ChangeLog: * riscv-tdep.c (riscv_feature_name_csr): Define. (riscv_feature_name_cpu): Define. (riscv_feature_name_fpu): Define. (riscv_feature_name_virtual): Define. (riscv_xreg_feature): Use riscv_feature_name_cpu. (riscv_freg_feature): Use riscv_feature_name_fpu. (riscv_virtual_feature): Use riscv_feature_name_virtual. (riscv_csr_feature): Use riscv_feature_name_csr. * riscv-tdep.h (riscv_feature_name_csr): Declare. --- gdb/ChangeLog | 12 ++++++++++++ gdb/riscv-tdep.c | 14 ++++++++++---- gdb/riscv-tdep.h | 3 +++ 3 files changed, 25 insertions(+), 4 deletions(-) diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index b16e7d78fc5..cb917247bab 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -94,6 +94,12 @@ static unsigned int riscv_debug_unwinder = 0; static unsigned int riscv_debug_gdbarch = 0; +/* The names of the RISC-V target description features. */ +const char *riscv_feature_name_csr = "org.gnu.gdb.riscv.csr"; +static const char *riscv_feature_name_cpu = "org.gnu.gdb.riscv.cpu"; +static const char *riscv_feature_name_fpu = "org.gnu.gdb.riscv.fpu"; +static const char *riscv_feature_name_virtual = "org.gnu.gdb.riscv.virtual"; + /* Cached information about a frame. */ struct riscv_unwind_cache @@ -257,7 +263,7 @@ riscv_register_feature::register_info::check struct riscv_xreg_feature : public riscv_register_feature { riscv_xreg_feature () - : riscv_register_feature ("org.gnu.gdb.riscv.cpu") + : riscv_register_feature (riscv_feature_name_cpu) { m_registers = { { RISCV_ZERO_REGNUM + 0, { "zero", "x0" } }, @@ -354,7 +360,7 @@ static const struct riscv_xreg_feature riscv_xreg_feature; struct riscv_freg_feature : public riscv_register_feature { riscv_freg_feature () - : riscv_register_feature ("org.gnu.gdb.riscv.fpu") + : riscv_register_feature (riscv_feature_name_fpu) { m_registers = { { RISCV_FIRST_FP_REGNUM + 0, { "ft0", "f0" } }, @@ -482,7 +488,7 @@ static const struct riscv_freg_feature riscv_freg_feature; struct riscv_virtual_feature : public riscv_register_feature { riscv_virtual_feature () - : riscv_register_feature ("org.gnu.gdb.riscv.virtual") + : riscv_register_feature (riscv_feature_name_virtual) { m_registers = { { RISCV_PRIV_REGNUM, { "priv" } } @@ -518,7 +524,7 @@ static const struct riscv_virtual_feature riscv_virtual_feature; struct riscv_csr_feature : public riscv_register_feature { riscv_csr_feature () - : riscv_register_feature ("org.gnu.gdb.riscv.csr") + : riscv_register_feature (riscv_feature_name_csr) { m_registers = { #define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER) \ diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h index d1f1cf17ba8..154097df5d0 100644 --- a/gdb/riscv-tdep.h +++ b/gdb/riscv-tdep.h @@ -160,4 +160,7 @@ extern void riscv_supply_regset (const struct regset *regset, struct regcache *regcache, int regnum, const void *regs, size_t len); +/* The names of the RISC-V target description features. */ +extern const char *riscv_feature_name_csr; + #endif /* RISCV_TDEP_H */ -- 2.25.4