From: "Doug Evans via gdb-patches" <gdb-patches@sourceware.org>
To: Stafford Horne <shorne@gmail.com>
Cc: GDB patches <gdb-patches@sourceware.org>,
Simon Marchi <simon.marchi@polymtl.ca>,
Mike Frysinger <vapier@gentoo.org>,
Openrisc <openrisc@lists.librecores.org>
Subject: Re: [PATCH v6 3/6] sim: or1k: add or1k target to sim
Date: Wed, 18 Oct 2017 20:15:00 -0000 [thread overview]
Message-ID: <94eb2c05879608d374055bd7e7c3@google.com> (raw)
Stafford Horne writes:
> This adds the OpenRISC 32-bit sim target. The OpenRISC sim is a CGEN
> based sim so the bulk of the code is generated from the .cpu files by
> CGEN. The engine decode and execute logic in mloop uses scache with
> pseudo-basic-block extraction and supports both full and fast (switch)
> modes.
>
> The sim does not implement an mmu at the moment. The sim does implement
> fpu instructions via the common sim-fpu implementation.
>
> sim/ChangeLog:
>
> 2017-09-13 Stafford Horne <shorne@gmail.com>
> Peter Gavin <pgavin@gmail.com>
>
> * configure.tgt: Add or1k sim.
> * or1k/README: New file.
> * or1k/Makefile.in: New file.
> * or1k/configure.ac: New file.
> * or1k/mloop.in: New file.
> * or1k/or1k-sim.h: New file.
> * or1k/or1k.c: New file.
> * or1k/sim-if.c: New file.
> * or1k/sim-main.h: New file.
> * or1k/traps.c: New file.
LGTM
next reply other threads:[~2017-10-18 20:15 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-18 20:15 Doug Evans via gdb-patches [this message]
-- strict thread matches above, loose matches on Subject: below --
2017-10-13 12:37 [PATCH v6 0/6] sim port for OpenRISC Stafford Horne
2017-10-13 12:37 ` [PATCH v6 3/6] sim: or1k: add or1k target to sim Stafford Horne
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