From: will schmidt <will_schmidt@vnet.ibm.com>
To: gdb-patches@sourceware.org
Cc: rogerio <rogealve@br.ibm.com>,
Ulrich Weigand <Ulrich.Weigand@de.ibm.com>,
Alan Modra <amodra@gmail.com>
Subject: [PATCH] gdb-power10-single-step
Date: Fri, 05 Mar 2021 12:51:30 -0600 [thread overview]
Message-ID: <983294f95974a6a3572d31b077f0ca66de554655.camel@vnet.ibm.com> (raw)
gdb-power10-single-step
Hi,
This is a patch written by Alan Modra. With his permission
I'm submitting this for review and helping get this upstream.
Powerpc / Power10 ISA 3.1 adds prefixed instructions, which
are 8 bytes in length. This is in contrast to powerpc previously
always having 4 byte instruction length. This patch implements
changes to allow GDB to better detect prefixed instructions, and
handle single stepping across the 8 byte instructions.
gdb/ChangeLog
2021-03-05 Alan Modra <amodra@gmail.com>
* ppc-tdep.h (ppc_software_single_step): Rename from
ppc_deal_with_atomic_sequence.
* rs6000-aix-tdep.c (rs6000_software_single_step): Adjust.
* rs6000-tdep.c (OP_MASK): Rename from BRANCH_MASK, adjust throughout.
(ppc_displaced_step_copy_insn): Handle reads of less than two
insns.
(ppc_displaced_step_fixup): Handle power10 insns.
(ppc_software_single_step): Likewise.
(rs6000_gdbarch_init): Adjust for rename. Set max_insn_length
to two words.
diff --git a/gdb/ppc-tdep.h b/gdb/ppc-tdep.h
index 77b6ab154f..8591e2cdbb 100644
--- a/gdb/ppc-tdep.h
+++ b/gdb/ppc-tdep.h
@@ -75,7 +75,7 @@ int ppc_altivec_support_p (struct gdbarch *gdbarch);
/* Return non-zero if the architecture described by GDBARCH has
VSX registers (vsr0 --- vsr63). */
int vsx_support_p (struct gdbarch *gdbarch);
-std::vector<CORE_ADDR> ppc_deal_with_atomic_sequence
+std::vector<CORE_ADDR> ppc_software_single_step
(struct regcache *regcache);
diff --git a/gdb/rs6000-aix-tdep.c b/gdb/rs6000-aix-tdep.c
index 02d492b337..9d4c79fdf0 100644
--- a/gdb/rs6000-aix-tdep.c
+++ b/gdb/rs6000-aix-tdep.c
@@ -785,7 +785,7 @@ rs6000_software_single_step (struct regcache *regcache)
insn = read_memory_integer (loc, 4, byte_order);
- std::vector<CORE_ADDR> next_pcs = ppc_deal_with_atomic_sequence (regcache);
+ std::vector<CORE_ADDR> next_pcs = ppc_software_single_step (regcache);
if (!next_pcs.empty ())
return next_pcs;
diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c
index b09f63137d..bc981036a8 100644
--- a/gdb/rs6000-tdep.c
+++ b/gdb/rs6000-tdep.c
@@ -841,7 +841,7 @@ typedef BP_MANIPULATION_ENDIAN (little_breakpoint, big_breakpoint)
rs6000_breakpoint;
/* Instruction masks for displaced stepping. */
-#define BRANCH_MASK 0xfc000000
+#define OP_MASK 0xfc000000
#define BP_MASK 0xFC0007FE
#define B_INSN 0x48000000
#define BC_INSN 0x40000000
@@ -895,7 +895,10 @@ ppc_displaced_step_copy_insn (struct gdbarch *gdbarch,
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
int insn;
- read_memory (from, buf, len);
+ len = target_read (current_top_target (), TARGET_OBJECT_MEMORY, NULL,
+ buf, from, len);
+ if ((ssize_t) len < PPC_INSN_SIZE)
+ memory_error (TARGET_XFER_E_IO, from);
insn = extract_signed_integer (buf, PPC_INSN_SIZE, byte_order);
@@ -934,9 +937,9 @@ ppc_displaced_step_fixup (struct gdbarch *gdbarch,
PPC_INSN_SIZE, byte_order);
ULONGEST opcode = 0;
/* Offset for non PC-relative instructions. */
- LONGEST offset = PPC_INSN_SIZE;
+ LONGEST offset;
- opcode = insn & BRANCH_MASK;
+ opcode = insn & OP_MASK;
displaced_debug_printf ("(ppc) fixup (%s, %s)",
paddress (gdbarch, from), paddress (gdbarch, to));
@@ -1001,9 +1004,14 @@ ppc_displaced_step_fixup (struct gdbarch *gdbarch,
else if ((insn & BP_MASK) == BP_INSN)
regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), from);
else
- /* Handle any other instructions that do not fit in the categories above. */
- regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
- from + offset);
+ {
+ offset = PPC_INSN_SIZE;
+ /* Power10 prefix instructions are two words in length. */
+ if (opcode == 1 << 26)
+ offset = 2 * PPC_INSN_SIZE;
+ regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
+ from + offset);
+ }
}
/* Implementation of gdbarch_displaced_step_prepare. */
@@ -1061,12 +1069,13 @@ ppc_displaced_step_hw_singlestep (struct gdbarch *gdbarch)
return true;
}
-/* Checks for an atomic sequence of instructions beginning with a
- Load And Reserve instruction and ending with a Store Conditional
- instruction. If such a sequence is found, attempt to step through it.
- A breakpoint is placed at the end of the sequence. */
+/* Step over Power10 prefix instructions and atomic sequence of
+ instructions beginning with a Load And Reserve instruction and
+ ending with a Store Conditional instruction. If such a sequence is
+ found, attempt to step through it. A breakpoint is placed at the
+ end of the sequence. */
std::vector<CORE_ADDR>
-ppc_deal_with_atomic_sequence (struct regcache *regcache)
+ppc_software_single_step (struct regcache *regcache)
{
struct gdbarch *gdbarch = regcache->arch ();
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
@@ -1081,6 +1090,10 @@ ppc_deal_with_atomic_sequence (struct regcache *regcache)
const int atomic_sequence_length = 16; /* Instruction sequence length. */
int bc_insn_count = 0; /* Conditional branch instruction count. */
+ /* Power10 prefix instructions are two words in length. */
+ if ((insn & OP_MASK) == 1 << 26)
+ return { pc + 8 };
+
/* Assume all atomic sequences start with a Load And Reserve instruction. */
if (!IS_LOAD_AND_RESERVE_INSN (insn))
return {};
@@ -1095,7 +1108,7 @@ ppc_deal_with_atomic_sequence (struct regcache *regcache)
/* Assume that there is at most one conditional branch in the atomic
sequence. If a conditional branch is found, put a breakpoint in
its destination address. */
- if ((insn & BRANCH_MASK) == BC_INSN)
+ if ((insn & OP_MASK) == BC_INSN)
{
int immediate = ((insn & 0xfffc) ^ 0x8000) - 0x8000;
int absolute = insn & 2;
@@ -7038,8 +7051,8 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
it shouldn't be. */
set_gdbarch_sofun_address_maybe_missing (gdbarch, 1);
- /* Handles single stepping of atomic sequences. */
- set_gdbarch_software_single_step (gdbarch, ppc_deal_with_atomic_sequence);
+ /* Handles single stepping of power10 prefix insns and atomic sequences. */
+ set_gdbarch_software_single_step (gdbarch, ppc_software_single_step);
/* Not sure on this. FIXMEmgo */
set_gdbarch_frame_args_skip (gdbarch, 8);
@@ -7070,7 +7083,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
set_gdbarch_displaced_step_restore_all_in_ptid
(gdbarch, ppc_displaced_step_restore_all_in_ptid);
- set_gdbarch_max_insn_length (gdbarch, PPC_INSN_SIZE);
+ set_gdbarch_max_insn_length (gdbarch, 2 * PPC_INSN_SIZE);
/* Hook in ABI-specific overrides, if they have been registered. */
info.target_desc = tdesc;
next reply other threads:[~2021-03-05 18:51 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-05 18:51 will schmidt [this message]
2021-03-10 17:50 ` Ulrich Weigand
2021-03-16 21:48 ` will schmidt
2021-03-25 17:21 ` will schmidt
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