From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 50376 invoked by alias); 27 Sep 2018 08:45:22 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 50236 invoked by uid 89); 27 Sep 2018 08:45:08 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-11.3 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,SPF_PASS autolearn=ham version=3.3.2 spammy=Managing, 1012, Activate, 10-12 X-HELO: mga09.intel.com Received: from mga09.intel.com (HELO mga09.intel.com) (134.134.136.24) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 27 Sep 2018 08:45:05 +0000 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Sep 2018 01:45:02 -0700 Received: from irsmsx110.ger.corp.intel.com ([163.33.3.25]) by fmsmga005.fm.intel.com with ESMTP; 27 Sep 2018 01:44:46 -0700 Received: from irsmsx155.ger.corp.intel.com (163.33.192.3) by irsmsx110.ger.corp.intel.com (163.33.3.25) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 27 Sep 2018 09:44:45 +0100 Received: from irsmsx104.ger.corp.intel.com ([169.254.5.213]) by irsmsx155.ger.corp.intel.com ([169.254.14.27]) with mapi id 14.03.0319.002; Thu, 27 Sep 2018 09:44:45 +0100 From: "Metzger, Markus T" To: Pierre Marsais , "gdb-patches@sourceware.org" Subject: RE: [PATCH] Add support for recording xsave x86 instruction Date: Thu, 27 Sep 2018 08:45:00 -0000 Message-ID: References: <20180921003827.1525-1-pierre.marsais@lse.epita.fr> In-Reply-To: <20180921003827.1525-1-pierre.marsais@lse.epita.fr> Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Return-Path: markus.t.metzger@intel.com Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2018-09/txt/msg00873.txt.bz2 Hello Pierre, > + case 4: /* xsave */ We should also check MOD !=3D 3. > + uint64_t tmpu64; > + if (i386_record_lea_modrm_addr (&ir, &tmpu64)) > + return -1; > + if (record_full_arch_list_add_mem (tmpu64, 512 + 64)) > + return -1; > + > + for (int i =3D 2; i < 64; i++) { > + if (!((1 << i) & tdep->xcr0)) > + continue; > + > + unsigned int size, offset, tmp1, tmp2; > + > + if (!__get_cpuid_count(0xd, i, &size, &offset, &tmp1, &tmp2)) > + return -1; This would check the native configuration, correct? What if we recorded remotely on a different x86 box? Also I think that we would need to check the inferior architecture to handle 32-bit compatibility mode. SIZE may be zero. We should probably check that and continue. I'm not sure whether we can actually run into this case but it doesn't hurt to check. Nit: there's a space before (. > + > + if (record_full_arch_list_add_mem (tmpu64 + offset, size)) > + return -1; Looks like this assumes the standard (non-compacted) XSAVE format. For the compacted format, the offset must be computed by accumulating the sizes of preceding components. > diff --git a/gdb/testsuite/gdb.reverse/i386-xsave-reverse.c > b/gdb/testsuite/gdb.reverse/i386-xsave-reverse.c > +void xsave_test(void) { Nit: space before (. > + char buf[4096] __attribute__ ((aligned (64))) =3D { 0 }; The test could query the XSAVE buffer size. > + asm ("xor %%eax, %%eax\n\t" > + "not %%eax\n\t" > + "mov %%eax, %%edx\n\t" > + "xsave %0":"=3Dm"(buf) ::"eax", "edx"); } /* end xsave_test */ The } should probably go onto the next line. > +if ![istarget "*86*-*linux*"] then { > + verbose "Skipping i386 reverse tests." > + return > +} Why exclude 64-bit? > +runto main You'd typically check whether that succeeds and abort the test if it doesn'= t. > +if [supports_process_record] { > + # Activate process record/replay > + gdb_test_no_output "record" "turn on process record" > +} Shouldn't we abort the test if record is not supported? > +gdb_test "reverse-step" "xor.*" "reverse-step to xsave" > + > +gdb_test "print buf" ".* =3D '\\\\000' " \ > + "verify xsave buffer after reverse xsave" Regards, Markus. Intel Deutschland GmbH Registered Address: Am Campeon 10-12, 85579 Neubiberg, Germany Tel: +49 89 99 8853-0, www.intel.de Managing Directors: Christin Eisenschmid, Christian Lamprechter Chairperson of the Supervisory Board: Nicole Lau Registered Office: Munich Commercial Register: Amtsgericht Muenchen HRB 186928