From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 10572 invoked by alias); 7 Nov 2018 09:07:19 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 10552 invoked by uid 89); 7 Nov 2018 09:07:19 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-6.8 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_2,SPF_PASS autolearn=ham version=3.3.2 spammy=Managing, 7th, Commercial, germany X-HELO: mga18.intel.com Received: from mga18.intel.com (HELO mga18.intel.com) (134.134.136.126) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 07 Nov 2018 09:07:13 +0000 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Nov 2018 01:07:11 -0800 Received: from irsmsx106.ger.corp.intel.com ([163.33.3.31]) by orsmga001.jf.intel.com with ESMTP; 07 Nov 2018 01:07:10 -0800 Received: from irsmsx112.ger.corp.intel.com (10.108.20.5) by IRSMSX106.ger.corp.intel.com (163.33.3.31) with Microsoft SMTP Server (TLS) id 14.3.408.0; Wed, 7 Nov 2018 09:07:09 +0000 Received: from irsmsx104.ger.corp.intel.com ([169.254.5.131]) by irsmsx112.ger.corp.intel.com ([169.254.1.93]) with mapi id 14.03.0415.000; Wed, 7 Nov 2018 09:07:09 +0000 From: "Metzger, Markus T" To: Simon Marchi , Jan Beulich CC: GDB Subject: RE: Ping: [PATCH v2] x86-64: fix ZMM register state tracking Date: Wed, 07 Nov 2018 09:07:00 -0000 Message-ID: References: <5B8FD8B302000078001E5940@prv1-mh.provo.novell.com> <5BD6E19202000078001F5BC4@prv1-mh.provo.novell.com> <8bafd220c79c3936de8ce3d6421a9c01@polymtl.ca> In-Reply-To: <8bafd220c79c3936de8ce3d6421a9c01@polymtl.ca> Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Return-Path: markus.t.metzger@intel.com Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2018-11/txt/msg00090.txt.bz2 > On 2018-10-29 06:31, Jan Beulich wrote: > >>>> On 10.10.18 at 17:12, wrote: > >> The three AVX512 state components are entirely independent - one > >> being in its "init state" has no implication whatsoever on either of > >> the other two. Fully separate X86_XSTATE_ZMM_H and X86_XSTATE_ZMM > >> handling, to prevent upper halves of the upper 16 ZMM registers to > >> display as if they were zero (when they aren't) after e.g. > >> VZEROALL/VZEROUPPER. > >> > >> gdb/ > >> 2018-10-10 Jan Beulich > >> > >> * i387-tdep.c (i387_supply_xsave): Split handling of > >> X86_XSTATE_ZMM_H and X86_XSTATE_ZMM. > >> (i387_collect_xsave): Likewise. > >> > >> gdb/testsuite/ > >> 2018-10-10 Simon Marchi > >> > >> * testsuite/gdb.arch/i386-avx512.c, > >> testsuite/gdb.arch/i386-avx512.exp: Add 7th test. > >> > >> --- > >> v2: Attach comments to zmm_endlo_regnum declarations. Add testcase > >> provided by Simon. >=20 > The testcase obviously LGTM. I will let Markus approve the other changes. The code already looked good to me in v1. Thanks for adding comments. Markus. Intel Deutschland GmbH Registered Address: Am Campeon 10-12, 85579 Neubiberg, Germany Tel: +49 89 99 8853-0, www.intel.de Managing Directors: Christin Eisenschmid, Christian Lamprechter Chairperson of the Supervisory Board: Nicole Lau Registered Office: Munich Commercial Register: Amtsgericht Muenchen HRB 186928