From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 98042 invoked by alias); 7 Nov 2018 13:18:54 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 98024 invoked by uid 89); 7 Nov 2018 13:18:53 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-6.8 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_2,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.2 spammy=Hx-languages-length:2057 X-HELO: mga12.intel.com Received: from mga12.intel.com (HELO mga12.intel.com) (192.55.52.136) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 07 Nov 2018 13:18:52 +0000 Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Nov 2018 05:18:51 -0800 Received: from irsmsx153.ger.corp.intel.com ([163.33.192.75]) by fmsmga007.fm.intel.com with ESMTP; 07 Nov 2018 05:18:49 -0800 Received: from irsmsx104.ger.corp.intel.com ([169.254.5.131]) by IRSMSX153.ger.corp.intel.com ([169.254.9.139]) with mapi id 14.03.0415.000; Wed, 7 Nov 2018 13:18:49 +0000 From: "Metzger, Markus T" To: Jan Beulich , Simon Marchi CC: GDB , "Pedro Alves (palves@redhat.com)" Subject: RE: Ping: [PATCH v2] x86-64: fix ZMM register state tracking Date: Wed, 07 Nov 2018 13:18:00 -0000 Message-ID: References: <5B8FD8B302000078001E5940@prv1-mh.provo.novell.com> <5BD6E19202000078001F5BC4@prv1-mh.provo.novell.com> <8bafd220c79c3936de8ce3d6421a9c01@polymtl.ca> <5BE2AC5802000078001F8F7D@prv1-mh.provo.novell.com> In-Reply-To: <5BE2AC5802000078001F8F7D@prv1-mh.provo.novell.com> Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2018-11/txt/msg00093.txt.bz2 > >>> On 07.11.18 at 10:07, wrote: > >> On 2018-10-29 06:31, Jan Beulich wrote: > >> >>>> On 10.10.18 at 17:12, wrote: > >> >> The three AVX512 state components are entirely independent - one > >> >> being in its "init state" has no implication whatsoever on either > >> >> of the other two. Fully separate X86_XSTATE_ZMM_H and > >> >> X86_XSTATE_ZMM handling, to prevent upper halves of the upper 16 > >> >> ZMM registers to display as if they were zero (when they aren't) af= ter e.g. > >> >> VZEROALL/VZEROUPPER. > >> >> > >> >> gdb/ > >> >> 2018-10-10 Jan Beulich > >> >> > >> >> * i387-tdep.c (i387_supply_xsave): Split handling of > >> >> X86_XSTATE_ZMM_H and X86_XSTATE_ZMM. > >> >> (i387_collect_xsave): Likewise. > >> >> > >> >> gdb/testsuite/ > >> >> 2018-10-10 Simon Marchi > >> >> > >> >> * testsuite/gdb.arch/i386-avx512.c, > >> >> testsuite/gdb.arch/i386-avx512.exp: Add 7th test. > >> >> > >> >> --- > >> >> v2: Attach comments to zmm_endlo_regnum declarations. Add testcase > >> >> provided by Simon. > >> > >> The testcase obviously LGTM. I will let Markus approve the other chan= ges. > > > > The code already looked good to me in v1. Thanks for adding comments. >=20 > So can I translate this into an ack for me to commit the change? > Or else, who would be the one to give the go-ahead? Simon can approve your patch. IIRC Pedro had a question regarding gdbserver. From a first look, it seems= to get the feature bits right but does not distinguish 32-bit and 64-bit mode regardin= g the number of available registers. Did you run the new test you added also in remote configuration? Markus. Intel Deutschland GmbH Registered Address: Am Campeon 10-12, 85579 Neubiberg, Germany Tel: +49 89 99 8853-0, www.intel.de Managing Directors: Christin Eisenschmid, Christian Lamprechter Chairperson of the Supervisory Board: Nicole Lau Registered Office: Munich Commercial Register: Amtsgericht Muenchen HRB 186928