From: "Tedeschi, Walfred" <walfred.tedeschi@intel.com>
To: Marcin Koscielnicki <koriakin@0x04.net>,
"palves@redhat.com" <palves@redhat.com>,
"eliz@gnu.org" <eliz@gnu.org>,
"brobecker@adacore.com" <brobecker@adacore.com>
Cc: "gdb-patches@sourceware.org" <gdb-patches@sourceware.org>
Subject: RE: [PATCH 0/2] Split tdesc_(amd64|i386)_mpx into tdesc(amd64|i386)_mpx_* and tdesc(amd64|i386)_avx_mpx_*
Date: Wed, 02 Mar 2016 10:03:00 -0000 [thread overview]
Message-ID: <AC542571535E904D8E8ADAE745D60B194455DA23@IRSMSX104.ger.corp.intel.com> (raw)
In-Reply-To: <56CF5430.2000502@0x04.net>
-----Original Message-----
From: Marcin Kościelnicki [mailto:koriakin@0x04.net]
Sent: Thursday, February 25, 2016 8:21 PM
To: Tedeschi, Walfred; palves@redhat.com; eliz@gnu.org; brobecker@adacore.com
Cc: gdb-patches@sourceware.org
Subject: Re: [PATCH 0/2] Split tdesc_(amd64|i386)_mpx into tdesc(amd64|i386)_mpx_* and tdesc(amd64|i386)_avx_mpx_*
On 22/02/16 09:49, Walfred Tedeschi wrote:
> CPU features can occur in any combination. The current assumption that
> feature "A" implies in feature "B" does not necessarily hold.
>
> This patch series construct an additional combination of the Intel(R)
> Memory Protection Extensions (MPX) with Intel(R) Advanced Vector
> Extensions (AVX).
>
> Starting from the current implementation that has MPX combined with AVX.
> A new target description having only MPX will be created using a two
> step approach as described below:
>
> First step:
> Mirror (i386|amd64)mpx target descriptors onto (i386|amd64)-avx-mpx
> ones.
>
> Add a redundant target description for the MPX and AVX case using a
> combined feature name to reflect that, i.e. avx-mpx. A new flag 2is
> also added to address MPX case without AVX.
>
>
> Second step:
> Refactor (i386|amd64)-mpx target descriptors.
>
> AVX feature is removed from the set of files that described MPX alone
> feature. Present on GDB code previous to this patch.
>
>
> Tests were done with hardware having MPX and AVX as is.
> For MPX standing alone tests were done forcing the XCR0 bits.
>
>
FYI, I've just refactored a few things in x86 tdescs, to properly pass them into the IPA - you will have a conflict with my commit ae91f6253926e4dadebcae90772f4f5a5bd06056. You will have to add an X86_TDESC_AVX_MPX enum value, emit it in gdbserver when you're using one of the new tdescs, and recognize it in the IPAs. Sorry for the inconvenience.
Marcin,
Thanks a lot for the heads up!
I looks like it is time to refactor the tdesc_selection, or? I suppose I have seen this code now 5 times.
May I do it and send as a separated patch?
Thanks and regards,
-Fred
Intel Deutschland GmbH
Registered Address: Am Campeon 10-12, 85579 Neubiberg, Germany
Tel: +49 89 99 8853-0, www.intel.de
Managing Directors: Christin Eisenschmid, Christian Lamprechter
Chairperson of the Supervisory Board: Nicole Lau
Registered Office: Munich
Commercial Register: Amtsgericht Muenchen HRB 186928
prev parent reply other threads:[~2016-03-02 10:03 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-22 8:49 Walfred Tedeschi
2016-02-22 8:49 ` [PATCH 2/2] Re-factor (i386|amd64)mpx target descriptors Walfred Tedeschi
2016-02-22 8:49 ` [PATCH 1/2] Add redundant target descriptor for tdesc(amd64|i386)_avx_mpx_* Walfred Tedeschi
2016-02-25 19:21 ` [PATCH 0/2] Split tdesc_(amd64|i386)_mpx into tdesc(amd64|i386)_mpx_* and tdesc(amd64|i386)_avx_mpx_* Marcin Kościelnicki
2016-03-02 10:03 ` Tedeschi, Walfred [this message]
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