Hi Tom,

Here is the patch with the changes you specified.

Regards,
Branislav

________________________________
From: Tom Tromey <tom@tromey.com>
Sent: Tuesday, June 20, 2023 4:08 PM
To: Branislav Brzak <Branislav.Brzak@Syrmia.com>
Cc: gdb-patches@sourceware.org <gdb-patches@sourceware.org>; Dragoslav Sicarov <Dragoslav.Sicarov@Syrmia.com>; Djordje Todorovic <Djordje.Todorovic@syrmia.com>
Subject: Re: [PATCH 0/1] riscv: Ensure LE instruction fetching

> Currently riscv gdb code looks at arch byte order
> when fetching instructions. This works when the
> target is LE, but on BE arch it will byte swap the
> instruction, while the riscv spec defines all
> instructions are LE encoded regardless of
> system memory endianess.

Thank you for the patch.

> @@ -1812,7 +1812,7 @@ ULONGEST
>  riscv_insn::fetch_instruction (struct gdbarch *gdbarch,
>                               CORE_ADDR addr, int *len)
>  {
> -  enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch);
> +  enum bfd_endian byte_order = BFD_ENDIAN_LITTLE;

The variable is only used once, so you might as well remove it entirely
and replace it BFD_ENDIAN_LITTLE in the call.

A comment saying that instructions are always little-endian might be nice.

Tom