From 368fd34e4736192f053de73b0f24a288b43bfd29 Mon Sep 17 00:00:00 2001 From: Branislav Brzak Date: Tue, 20 Jun 2023 16:19:55 +0200 Subject: [PATCH] * riscv-tdep.c (riscv_insn::fetch_instruction): Always fetch instructions as LE --- gdb/riscv-tdep.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index 500279e1ae9..ae18eb64452 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -1812,7 +1812,6 @@ ULONGEST riscv_insn::fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR addr, int *len) { - enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch); gdb_byte buf[RISCV_MAX_INSN_LEN]; int instlen, status; @@ -1833,7 +1832,8 @@ riscv_insn::fetch_instruction (struct gdbarch *gdbarch, memory_error (TARGET_XFER_E_IO, addr + 2); } - return extract_unsigned_integer (buf, instlen, byte_order); + /* RISC-V Specification states instructions are always little endian */ + return extract_unsigned_integer (buf, instlen, BFD_ENDIAN_LITTLE); } /* Fetch from target memory an instruction at PC and decode it. This can -- 2.34.1