[PATCH v2 2/2] sim: riscv: Simplify the signed div by -1 code

[PATCH v2 2/2] sim: riscv: Simplify the signed div by -1 code

[Bernd Edlinger]

This uses the idea from the previous patch to
simplify the code for non-overflowing signed
divisions by -1.  This is no bug-fix but it
simplifies the code and avoids some unnecessary
branches.
---
 sim/riscv/sim-main.c      | 13 ++++++-----
 sim/testsuite/riscv/div.s | 46 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 53 insertions(+), 6 deletions(-)
 create mode 100644 sim/testsuite/riscv/div.s

v2: added a test case

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 2b8a800232e..3b72fb53bc1 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -700,18 +700,19 @@ execute_m (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
   const char *rd_name = riscv_gpr_names_abi[rd];
   const char *rs1_name = riscv_gpr_names_abi[rs1];
   const char *rs2_name = riscv_gpr_names_abi[rs2];
-  unsigned_word tmp, dividend_max;
+  unsigned_word tmp;
   sim_cia pc = riscv_cpu->pc + 4;
 
-  dividend_max = -((unsigned_word) 1 << (WITH_TARGET_WORD_BITSIZE - 1));
-
   switch (op->match)
     {
     case MATCH_DIV:
       TRACE_INSN (cpu, "div %s, %s, %s;  // %s = %s / %s",
 		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
-      if (riscv_cpu->regs[rs1] == dividend_max && riscv_cpu->regs[rs2] == -1)
-	tmp = dividend_max;
+      /* Dividing by -1 can potentially overflow, and has therefore
+	 to be done separately.  Note that the sign change operation
+	 is done on an unsigned value and is therefore safe to do.  */
+      if (riscv_cpu->regs[rs2] == -1)
+	tmp = -riscv_cpu->regs[rs1];
       else if (riscv_cpu->regs[rs2])
 	tmp = (signed_word) riscv_cpu->regs[rs1] /
 	  (signed_word) riscv_cpu->regs[rs2];
@@ -793,7 +794,7 @@ execute_m (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
     case MATCH_REM:
       TRACE_INSN (cpu, "rem %s, %s, %s;  // %s = %s %% %s",
 		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
-      if (riscv_cpu->regs[rs1] == dividend_max && riscv_cpu->regs[rs2] == -1)
+      if (riscv_cpu->regs[rs2] == -1)
 	tmp = 0;
       else if (riscv_cpu->regs[rs2])
 	tmp = (signed_word) riscv_cpu->regs[rs1]
diff --git a/sim/testsuite/riscv/div.s b/sim/testsuite/riscv/div.s
new file mode 100644
index 00000000000..e16b8ef17b0
--- /dev/null
+++ b/sim/testsuite/riscv/div.s
@@ -0,0 +1,46 @@
+# Basic div tests.
+# mach: riscv32 riscv64
+
+.include "testutils.inc"
+
+	.macro test_divrem  dividend, divisor, quotient, remainder
+	# Setup inputs.
+	li	a1, \dividend
+	li	a2, \divisor
+
+	# Do the divide.
+	div	a3, a1, a2
+	rem	a4, a1, a2
+
+	# Check answer is correct.
+	li	a5, \quotient
+	li	a6, \remainder
+	bne	a3, a5, test_failed
+	bne	a4, a6, test_failed
+
+	mul	a3, a3, a2
+	add	a3, a3, a4
+	bne	a3, a1, test_failed
+	.endm
+
+
+	start
+
+	test_divrem     12, 4, 3, 0
+	test_divrem     12, 3, 4, 0
+
+	test_divrem	13, -1, -13, 0
+	test_divrem	-13, -1, 13, 0
+
+	test_divrem     14, 3, 4, 2
+	test_divrem     -14, 3, -4, -2
+	test_divrem     14, -3, -4, 2
+	test_divrem     -14, -3, 4, -2
+
+	test_divrem     15, 0, -1, 15
+	test_divrem     -15, 0, -1, -15
+
+	pass
+
+test_failed:
+	fail
-- 
2.39.2