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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: syrmia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AS8PR03MB9698.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: ef525d64-2525-4813-b871-08dc21a68ae7 X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Jan 2024 15:17:15.7901 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 19214a73-c1ab-4e19-8f59-14bdcb09a66e X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: KOcOE4oEYaXdS4TCFjh346Z9E33clHI6SgLzVutXeK0MH9cC1t92Y06ARZFggAW9ivZlvCCIATv7djItrz/WyokxfmQhS9TCAk32MMrp8Ms= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR03MB6927 X-Spam-Status: No, score=-13.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Introduce new instruction encodings from Release 6 of the MIPS=0A= architecture [1]. Support breakpoints and single stepping with=0A= compact branches, forbidden slots, new branch instruction and=0A= new atomic load-store instruction encodings.=0A= =0A= Changes from v2: Added new tests=0A= =0A= [1] "MIPS64 Architecture for Programmers Volume II-A: The MIPS64=0A= Instruction Set Reference Manual", Document Number: MD00087,=0A= Revision 6.06, December 15, 2016, Section 3 "The MIPS64=0A= Instruction Set", pp. 42-530=0A= https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00087-2B-MIPS= 64BIS-AFP-6.06.pdf=0A= =0A= 2024-01-30 Andrew Bennett =0A= Matthew Fortune =0A= Faraz Shahbazker =0A= =0A= gdb/ChangeLog:=0A= * mips-tdep.c (is_mipsr6_isa): New.=0A= (b0s21_imm): New define.=0A= (mips32_relative_offset21, mips32_relative_offset26): New.=0A= (is_add32bit_overflow, is_add64bit_overflow): New.=0A= (mips32_next_pc): Handle r6 compact and fpu coprocessor branches.=0A= Move handling of BLEZ, BGTZ opcode into ...=0A= (mips32_blez_pc): New.=0A= (mips32_instruction_is_compact_branch): New.=0A= (mips32_insn_at_pc_has_forbidden_slot): New.=0A= (mips32_scan_prologue): Ignore pre-r6 addi encoding on r6.=0A= Stop at compact branch also.=0A= (LLSC_R6_OPCODE,LL_R6_FUNCT,LLE_FUNCT,=0A= LLD_R6_FUNCT,SC_R6_FUNCT,SCE_FUNCT,=0A= SCD_R6_FUNCT: New defines.=0A= (is_ll_insn, is_sc_insn): New.=0A= (mips_deal_with_atomic_sequence): Use is_ll_insn/is_sc_insn.=0A= Handle compact branches.=0A= (mips_about_to_return): Handle jrc and macro jr.=0A= (mips32_stack_frame_destroyed_p): Likewise.=0A= (mips32_instruction_has_delay_slot): Don't handle JALX on r6.=0A= Handle compact branches and coprocessor branches.=0A= (mips_adjust_breakpoint_address): Skip forbidden slot for=0A= compact branches.=0A= ---=0A= gdb/mips-tdep.c | 520 ++++++++-=0A= gdb/testsuite/gdb.arch/mips-64-r6.c | 1469 +++++++++++++++++++++++++=0A= gdb/testsuite/gdb.arch/mips-64-r6.exp | 99 ++=0A= 3 files changed, 2046 insertions(+), 42 deletions(-)=0A= create mode 100644 gdb/testsuite/gdb.arch/mips-64-r6.c=0A= create mode 100644 gdb/testsuite/gdb.arch/mips-64-r6.exp=0A= =0A= diff --git a/gdb/mips-tdep.c b/gdb/mips-tdep.c=0A= index bf0b66c4b00..a60377f25e0 100644=0A= --- a/gdb/mips-tdep.c=0A= +++ b/gdb/mips-tdep.c=0A= @@ -76,6 +76,9 @@ static int mips16_insn_at_pc_has_delay_slot (struct gdbar= ch *gdbarch,=0A= static void mips_print_float_info (struct gdbarch *, struct ui_file *,=0A= frame_info_ptr, const char *);=0A= =0A= +static void mips_read_fp_register_single (struct frame_info_ptr, int,=0A= + gdb_byte *);=0A= +=0A= /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */=0A= /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */= =0A= #define ST0_FR (1 << 26)=0A= @@ -1500,6 +1503,16 @@ mips_fetch_instruction (struct gdbarch *gdbarch,=0A= return extract_unsigned_integer (buf, instlen, byte_order);=0A= }=0A= =0A= +/* Return one if the gdbarch is based on MIPS Release 6. */=0A= +static int=0A= +is_mipsr6_isa (struct gdbarch *gdbarch)=0A= +{=0A= + const struct bfd_arch_info *info =3D gdbarch_bfd_arch_info (gdbarch);=0A= +=0A= + return (info->mach =3D=3D bfd_mach_mipsisa32r6=0A= + || info->mach =3D=3D bfd_mach_mipsisa64r6);=0A= +}=0A= +=0A= /* These are the fields of 32 bit mips instructions. */=0A= #define mips32_op(x) (x >> 26)=0A= #define itype_op(x) (x >> 26)=0A= @@ -1542,6 +1555,7 @@ mips_fetch_instruction (struct gdbarch *gdbarch,=0A= #define b0s11_op(x) ((x) & 0x7ff)=0A= #define b0s12_imm(x) ((x) & 0xfff)=0A= #define b0s16_imm(x) ((x) & 0xffff)=0A= +#define b0s21_imm(x) ((x) & 0x1fffff)=0A= #define b0s26_imm(x) ((x) & 0x3ffffff)=0A= #define b6s10_ext(x) (((x) >> 6) & 0x3ff)=0A= #define b11s5_reg(x) (((x) >> 11) & 0x1f)=0A= @@ -1578,6 +1592,18 @@ mips32_relative_offset (ULONGEST inst)=0A= return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2;=0A= }=0A= =0A= +static LONGEST=0A= +mips32_relative_offset21 (ULONGEST insn)=0A= +{=0A= + return ((b0s21_imm (insn) ^ 0x100000) - 0x100000) << 2;=0A= +}=0A= +=0A= +static LONGEST=0A= +mips32_relative_offset26 (ULONGEST insn)=0A= +{=0A= + return ((b0s26_imm (insn) ^ 0x2000000) - 0x2000000) << 2;=0A= +}=0A= +=0A= /* Determine the address of the next instruction executed after the INST= =0A= floating condition branch instruction at PC. COUNT specifies the=0A= number of the floating condition bits tested by the branch. */=0A= @@ -1636,6 +1662,71 @@ is_octeon_bbit_op (int op, struct gdbarch *gdbarch)= =0A= return 0;=0A= }=0A= =0A= +static int=0A= +is_add32bit_overflow (int32_t a, int32_t b)=0A= +{=0A= + int32_t r =3D (uint32_t) a + (uint32_t) b;=0A= + return (a < 0 && b < 0 && r >=3D 0) || (a >=3D 0 && b >=3D 0 && r < 0);= =0A= +}=0A= +=0A= +static int=0A= +is_add64bit_overflow (int64_t a, int64_t b)=0A= +{=0A= + if (a !=3D (int32_t)a)=0A= + return 1;=0A= + if (b !=3D (int32_t)b)=0A= + return 1;=0A= + return is_add32bit_overflow ((int32_t)a, (int32_t)b);=0A= +}=0A= +=0A= +/* Calculate address of next instruction after BLEZ. */=0A= +=0A= +static CORE_ADDR=0A= +mips32_blez_pc (struct gdbarch *gdbarch, struct regcache *regcache,=0A= + ULONGEST inst, CORE_ADDR pc, int invert)=0A= +{=0A= + int rs =3D itype_rs (inst);=0A= + int rt =3D itype_rt (inst);=0A= + LONGEST val_rs =3D regcache_raw_get_signed (regcache, rs);=0A= + LONGEST val_rt =3D regcache_raw_get_signed (regcache, rt);=0A= + ULONGEST uval_rs =3D regcache_raw_get_unsigned (regcache, rs);=0A= + ULONGEST uval_rt =3D regcache_raw_get_unsigned (regcache, rt);=0A= + int taken =3D 0;=0A= + int delay_slot_size =3D 4;=0A= +=0A= + /* BLEZ, BLEZL, BGTZ, BGTZL */=0A= + if (rt =3D=3D 0)=0A= + taken =3D (val_rs <=3D 0);=0A= + else if (is_mipsr6_isa (gdbarch))=0A= + {=0A= + /* BLEZALC, BGTZALC */=0A= + if (rs =3D=3D 0 && rt !=3D 0)=0A= + taken =3D (val_rt <=3D 0);=0A= + /* BGEZALC, BLTZALC */=0A= + else if (rs =3D=3D rt && rt !=3D 0)=0A= + taken =3D (val_rt >=3D 0);=0A= + /* BGEUC, BLTUC */=0A= + else if (rs !=3D rt && rs !=3D 0 && rt !=3D 0)=0A= + taken =3D (uval_rs >=3D uval_rt);=0A= +=0A= + /* Step through the forbidden slot to avoid repeated exceptions we d= o=0A= + not currently have access to the BD bit when hitting a breakpoint=0A= + and therefore cannot tell if the breakpoint hit on the branch or the=0A= + forbidden slot. */=0A= + /* delay_slot_size =3D 0; */=0A= + }=0A= +=0A= + if (invert)=0A= + taken =3D !taken;=0A= +=0A= + /* Calculate branch target. */=0A= + if (taken)=0A= + pc +=3D mips32_relative_offset (inst);=0A= + else=0A= + pc +=3D delay_slot_size;=0A= +=0A= + return pc;=0A= +}=0A= =0A= /* Determine where to set a single step breakpoint while considering=0A= branch prediction. */=0A= @@ -1646,12 +1737,17 @@ mips32_next_pc (struct regcache *regcache, CORE_ADD= R pc)=0A= struct gdbarch *gdbarch =3D regcache->arch ();=0A= unsigned long inst;=0A= int op;=0A= + int mips64bitreg =3D 0;=0A= +=0A= + if (mips_isa_regsize (gdbarch) =3D=3D 8)=0A= + mips64bitreg =3D 1;=0A= +=0A= inst =3D mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);=0A= op =3D itype_op (inst);=0A= if ((inst & 0xe0000000) !=3D 0) /* Not a special, jump or branch=0A= instruction. */=0A= {=0A= - if (op >> 2 =3D=3D 5)=0A= + if (op >> 2 =3D=3D 5 && ((op & 0x02) =3D=3D 0 || itype_rt (inst) =3D= =3D 0))=0A= /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */=0A= {=0A= switch (op & 0x03)=0A= @@ -1661,7 +1757,7 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR = pc)=0A= case 1: /* BNEL */=0A= goto neq_branch;=0A= case 2: /* BLEZL */=0A= - goto less_branch;=0A= + goto lez_branch;=0A= case 3: /* BGTZL */=0A= goto greater_branch;=0A= default:=0A= @@ -1671,15 +1767,19 @@ mips32_next_pc (struct regcache *regcache, CORE_ADD= R pc)=0A= else if (op =3D=3D 17 && itype_rs (inst) =3D=3D 8)=0A= /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */=0A= pc =3D mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 1);=0A= - else if (op =3D=3D 17 && itype_rs (inst) =3D=3D 9=0A= + else if (!is_mipsr6_isa (gdbarch)=0A= + && op =3D=3D 17=0A= + && itype_rs (inst) =3D=3D 9=0A= && (itype_rt (inst) & 2) =3D=3D 0)=0A= /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */=0A= pc =3D mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 2);=0A= - else if (op =3D=3D 17 && itype_rs (inst) =3D=3D 10=0A= - && (itype_rt (inst) & 2) =3D=3D 0)=0A= + else if (!is_mipsr6_isa (gdbarch)=0A= + && op =3D=3D 17=0A= + && itype_rs (inst) =3D=3D 10=0A= + && (itype_rt (inst) & 2) =3D=3D 0)=0A= /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */=0A= pc =3D mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 4);=0A= - else if (op =3D=3D 29)=0A= + else if (!is_mipsr6_isa (gdbarch) && op =3D=3D 29)=0A= /* JALX: 011101 */=0A= /* The new PC will be alternate mode. */=0A= {=0A= @@ -1707,7 +1807,128 @@ mips32_next_pc (struct regcache *regcache, CORE_ADD= R pc)=0A= else=0A= pc +=3D 8; /* After the delay slot. */=0A= }=0A= + else if (is_mipsr6_isa (gdbarch))=0A= + {=0A= + /* BOVC, BEQZALC, BEQC and BNVC, BNEZALC, BNEC */=0A= + if (op =3D=3D 8 || op =3D=3D 24)=0A= + {=0A= + int rs =3D rtype_rs (inst);=0A= + int rt =3D rtype_rt (inst);=0A= + LONGEST val_rs =3D regcache_raw_get_signed (regcache, rs);=0A= + LONGEST val_rt =3D regcache_raw_get_signed (regcache, rt);=0A= + int taken =3D 0;=0A= + /* BOVC (BNVC) */=0A= + if (rs >=3D rt)=0A= + {=0A= + if (mips64bitreg =3D=3D 1)=0A= + taken =3D is_add64bit_overflow (val_rs, val_rt);=0A= + else=0A= + taken =3D is_add32bit_overflow (val_rs, val_rt);=0A= + }=0A= + /* BEQZALC (BNEZALC) */=0A= + else if (rs < rt && rs =3D=3D 0)=0A= + taken =3D (val_rt =3D=3D 0);=0A= + /* BEQC (BNEC) */=0A= + else=0A= + taken =3D (val_rs =3D=3D val_rt);=0A= +=0A= + /* BNVC, BNEZALC, BNEC */=0A= + if (op =3D=3D 24)=0A= + taken =3D !taken;=0A= =0A= + if (taken)=0A= + pc +=3D mips32_relative_offset (inst) + 4;=0A= + else=0A= + /* Step through the forbidden slot to avoid repeated exceptions=0A= + we do not currently have access to the BD bit when hitting a=0A= + breakpoint and therefore cannot tell if the breakpoint=0A= + hit on the branch or the forbidden slot. */=0A= + pc +=3D 8;=0A= + }=0A= + /* BC1EQZ, BC1NEZ */=0A= + else if (op =3D=3D 17 && (itype_rs (inst) =3D=3D 9 || itype_rs (inst) = =3D=3D 13))=0A= + {=0A= + gdb_byte status;=0A= + gdb_byte true_val =3D 0;=0A= + unsigned int fp =3D (gdbarch_num_regs (gdbarch)=0A= + + mips_regnum (gdbarch)->fp0=0A= + + itype_rt (inst));=0A= + struct frame_info_ptr frame =3D get_current_frame ();=0A= + gdb_byte *raw_buffer =3D (gdb_byte *) alloca (sizeof (gdb_byte) * 4= );=0A= + mips_read_fp_register_single (frame, fp, raw_buffer);=0A= +=0A= + if (gdbarch_byte_order (gdbarch) =3D=3D BFD_ENDIAN_BIG)=0A= + status =3D *(raw_buffer + 3);=0A= + else=0A= + status =3D *(raw_buffer);=0A= +=0A= + if (itype_rs (inst) =3D=3D 13)=0A= + true_val =3D 1;=0A= +=0A= + if ((status & 0x1) =3D=3D true_val)=0A= + pc +=3D mips32_relative_offset (inst) + 4;=0A= + else=0A= + pc +=3D 8;=0A= + }=0A= + else if (op =3D=3D 22 || op =3D=3D 23)=0A= + /* BLEZC, BGEZC, BGEC, BGTZC, BLTZC, BLTC */=0A= + {=0A= + int rs =3D rtype_rs (inst);=0A= + int rt =3D rtype_rt (inst);=0A= + LONGEST val_rs =3D regcache_raw_get_signed (regcache, rs);=0A= + LONGEST val_rt =3D regcache_raw_get_signed (regcache, rt);=0A= + int taken =3D 0;=0A= + /* The R5 rt =3D=3D 0 case is handled above so we treat it as=0A= + an unknown instruction here for future ISA usage. */=0A= + if (rs =3D=3D 0 && rt !=3D 0)=0A= + taken =3D (val_rt <=3D 0);=0A= + else if (rs =3D=3D rt && rt !=3D 0)=0A= + taken =3D (val_rt >=3D 0);=0A= + else if (rs !=3D rt && rs !=3D 0 && rt !=3D 0)=0A= + taken =3D (val_rs >=3D val_rt);=0A= +=0A= + if (op =3D=3D 23)=0A= + taken =3D !taken;=0A= +=0A= + if (taken)=0A= + pc +=3D mips32_relative_offset (inst) + 4;=0A= + else=0A= + /* Step through the forbidden slot to avoid repeated exceptions=0A= + we do not currently have access to the BD bit when hitting a=0A= + breakpoint and therefore cannot tell if the breakpoint=0A= + hit on the branch or the forbidden slot. */=0A= + pc +=3D 8;=0A= + }=0A= + else if (op =3D=3D 50 || op =3D=3D 58)=0A= + /* BC, BALC */=0A= + pc +=3D mips32_relative_offset26 (inst) + 4;=0A= + else if ((op =3D=3D 54 || op =3D=3D 62)=0A= + && rtype_rs (inst) =3D=3D 0)=0A= + /* JIC, JIALC */=0A= + {=0A= + pc =3D regcache_raw_get_signed (regcache, itype_rt (inst));=0A= + pc +=3D (itype_immediate (inst) ^ 0x8000) - 0x8000;=0A= + }=0A= + else if (op =3D=3D 54 || op =3D=3D 62)=0A= + /* BEQZC, BNEZC */=0A= + {=0A= + int rs =3D itype_rs (inst);=0A= + LONGEST rs_val =3D regcache_raw_get_signed (regcache, rs);=0A= + int taken =3D (rs_val =3D=3D 0);=0A= + if (op =3D=3D 62)=0A= + taken =3D !taken;=0A= + if (taken)=0A= + pc +=3D mips32_relative_offset21 (inst) + 4;=0A= + else=0A= + /* Step through the forbidden slot to avoid repeated exceptions=0A= + we do not currently have access to the BD bit when hitting a=0A= + breakpoint and therefore cannot tell if the breakpoint=0A= + hit on the branch or the forbidden slot. */=0A= + pc +=3D 8;=0A= + }=0A= + else=0A= + pc +=3D 4; /* Not a branch, next instruction is easy. */=0A= + }=0A= else=0A= pc +=3D 4; /* Not a branch, next instruction is easy. */=0A= }=0A= @@ -1751,7 +1972,6 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR = pc)=0A= case 2: /* BLTZL */=0A= case 16: /* BLTZAL */=0A= case 18: /* BLTZALL */=0A= - less_branch:=0A= if (regcache_raw_get_signed (regcache, itype_rs (inst)) < 0)=0A= pc +=3D mips32_relative_offset (inst) + 4;=0A= else=0A= @@ -1767,22 +1987,38 @@ mips32_next_pc (struct regcache *regcache, CORE_ADD= R pc)=0A= pc +=3D 8; /* after the delay slot */=0A= break;=0A= case 0x1c: /* BPOSGE32 */=0A= + case 0x1d: /* BPOSGE32C */=0A= case 0x1e: /* BPOSGE64 */=0A= pc +=3D 4;=0A= if (itype_rs (inst) =3D=3D 0)=0A= {=0A= unsigned int pos =3D (op & 2) ? 64 : 32;=0A= int dspctl =3D mips_regnum (gdbarch)->dspctl;=0A= + int delay_slot_size =3D 4;=0A= =0A= if (dspctl =3D=3D -1)=0A= /* No way to handle; it'll most likely trap anyway. */=0A= break;=0A= =0A= + /* BPOSGE32C */=0A= + if (op =3D=3D 0x1d)=0A= + {=0A= + if (!is_mipsr6_isa (gdbarch))=0A= + break;=0A= +=0A= + /* Step through the forbidden slot to avoid repeated=0A= + exceptions we do not currently have access to the BD=0A= + bit when hitting a breakpoint and therefore cannot=0A= + tell if the breakpoint hit on the branch or the=0A= + forbidden slot. */=0A= + /* delay_slot_size =3D 0; */=0A= + }=0A= +=0A= if ((regcache_raw_get_unsigned (regcache,=0A= dspctl) & 0x7f) >=3D pos)=0A= pc +=3D mips32_relative_offset (inst);=0A= else=0A= - pc +=3D 4;=0A= + pc +=3D delay_slot_size;=0A= }=0A= break;=0A= /* All of the other instructions in the REGIMM category */=0A= @@ -1816,19 +2052,14 @@ mips32_next_pc (struct regcache *regcache, CORE_ADD= R pc)=0A= else=0A= pc +=3D 8;=0A= break;=0A= - case 6: /* BLEZ, BLEZL */=0A= - if (regcache_raw_get_signed (regcache, itype_rs (inst)) <=3D 0)=0A= - pc +=3D mips32_relative_offset (inst) + 4;=0A= - else=0A= - pc +=3D 8;=0A= + case 6: /* BLEZ, BLEZL, BLEZALC, BGEZALC, BGEUC */=0A= + lez_branch:=0A= + pc =3D mips32_blez_pc (gdbarch, regcache, inst, pc + 4, 0);=0A= break;=0A= case 7:=0A= default:=0A= - greater_branch: /* BGTZ, BGTZL */=0A= - if (regcache_raw_get_signed (regcache, itype_rs (inst)) > 0)=0A= - pc +=3D mips32_relative_offset (inst) + 4;=0A= - else=0A= - pc +=3D 8;=0A= + greater_branch: /* BGTZ, BGTZL, BGTZALC, BLTZALC, BLTUC */=0A= + pc =3D mips32_blez_pc (gdbarch, regcache, inst, pc + 4, 1);=0A= break;=0A= } /* switch */=0A= } /* else */=0A= @@ -2451,6 +2682,72 @@ micromips_instruction_is_compact_branch (unsigned sh= ort insn)=0A= }=0A= }=0A= =0A= +/* Return non-zero if the MIPS instruction INSN is a compact branch=0A= + or jump. A value of 1 indicates an unconditional compact branch=0A= + and a value of 2 indicates a conditional compact branch. */=0A= +=0A= +static int=0A= +mips32_instruction_is_compact_branch (struct gdbarch *gdbarch, ULONGEST in= sn)=0A= +{=0A= + switch (itype_op (insn))=0A= + {=0A= + /* BC */=0A= + case 50:=0A= + /* BALC */=0A= + case 58:=0A= + if (is_mipsr6_isa (gdbarch))=0A= + return 1;=0A= + break;=0A= + /* BOVC, BEQZALC, BEQC */=0A= + case 8:=0A= + /* BNVC, BNEZALC, BNEC */=0A= + case 24:=0A= + if (is_mipsr6_isa (gdbarch))=0A= + return 2;=0A= + break;=0A= + /* BEQZC, JIC */=0A= + case 54:=0A= + /* BNEZC, JIALC */=0A= + case 62:=0A= + if (is_mipsr6_isa (gdbarch))=0A= + /* JIC, JIALC are unconditional */=0A= + return (itype_rs (insn) =3D=3D 0) ? 1 : 2;=0A= + break;=0A= + /* BLEZC, BGEZC, BGEC */=0A= + case 22:=0A= + /* BGTZC, BLTZC, BLTC */=0A= + case 23:=0A= + /* BLEZALC, BGEZALC, BGEUC */=0A= + case 6:=0A= + /* BGTZALC, BLTZALC, BLTUC */=0A= + case 7:=0A= + if (is_mipsr6_isa (gdbarch)=0A= + && itype_rt (insn) !=3D 0)=0A= + return 2;=0A= + break;=0A= + /* BPOSGE32C */=0A= + case 1:=0A= + if (is_mipsr6_isa (gdbarch)=0A= + && itype_rt (insn) =3D=3D 0x1d && itype_rs (insn) =3D=3D 0)=0A= + return 2;=0A= + }=0A= + return 0;=0A= +}=0A= +=0A= +/* Return non-zero if a standard MIPS instruction at ADDR has a branch=0A= + forbidden slot (i.e. it is a conditional compact branch instruction). = */=0A= +=0A= +static int=0A= +mips32_insn_at_pc_has_forbidden_slot (struct gdbarch *gdbarch, CORE_ADDR a= ddr)=0A= +{=0A= + int status;=0A= + ULONGEST insn =3D mips_fetch_instruction (gdbarch, ISA_MIPS, addr, &stat= us);=0A= + if (status)=0A= + return 0;=0A= +=0A= + return mips32_instruction_is_compact_branch (gdbarch, insn) =3D=3D 2;=0A= +}=0A= +=0A= struct mips_frame_cache=0A= {=0A= CORE_ADDR base;=0A= @@ -3494,7 +3791,8 @@ mips32_scan_prologue (struct gdbarch *gdbarch,=0A= reg =3D high_word & 0x1f;=0A= =0A= if (high_word =3D=3D 0x27bd /* addiu $sp,$sp,-i */=0A= - || high_word =3D=3D 0x23bd /* addi $sp,$sp,-i */=0A= + || (high_word =3D=3D 0x23bd /* addi $sp,$sp,-i */=0A= + && !is_mipsr6_isa (gdbarch))=0A= || high_word =3D=3D 0x67bd) /* daddiu $sp,$sp,-i */=0A= {=0A= if (offset < 0) /* Negative stack adjustment? */=0A= @@ -3632,7 +3930,9 @@ mips32_scan_prologue (struct gdbarch *gdbarch,=0A= =0A= /* A jump or branch, or enough non-prologue insns seen? If so,=0A= then we must have reached the end of the prologue by now. */=0A= - if (prev_delay_slot || non_prologue_insns > 1)=0A= + if (prev_delay_slot=0A= + || non_prologue_insns > 1=0A= + || mips32_instruction_is_compact_branch (gdbarch, inst))=0A= break;=0A= =0A= prev_non_prologue_insn =3D this_non_prologue_insn;=0A= @@ -3938,6 +4238,59 @@ mips_addr_bits_remove (struct gdbarch *gdbarch, CORE= _ADDR addr)=0A= #define LLD_OPCODE 0x34=0A= #define SC_OPCODE 0x38=0A= #define SCD_OPCODE 0x3c=0A= +#define LLSC_R6_OPCODE 0x1f=0A= +#define LL_R6_FUNCT 0x36=0A= +#define LLE_FUNCT 0x2e=0A= +#define LLD_R6_FUNCT 0x37=0A= +#define SC_R6_FUNCT 0x26=0A= +#define SCE_FUNCT 0x1e=0A= +#define SCD_R6_FUNCT 0x27=0A= +=0A= +static int=0A= +is_ll_insn (struct gdbarch *gdbarch, ULONGEST insn)=0A= +{=0A= + if (itype_op (insn) =3D=3D LL_OPCODE=0A= + || itype_op (insn) =3D=3D LLD_OPCODE)=0A= + return 1;=0A= +=0A= + if (rtype_op (insn) =3D=3D LLSC_R6_OPCODE=0A= + && rtype_funct (insn) =3D=3D LLE_FUNCT=0A= + && (insn & 0x40) =3D=3D 0)=0A= + return 1;=0A= +=0A= + /* Handle LL and LLP varieties. */=0A= + if (is_mipsr6_isa (gdbarch)=0A= + && rtype_op (insn) =3D=3D LLSC_R6_OPCODE=0A= + && (rtype_funct (insn) =3D=3D LL_R6_FUNCT=0A= + || rtype_funct (insn) =3D=3D LLD_R6_FUNCT=0A= + || rtype_funct (insn) =3D=3D LLE_FUNCT))=0A= + return 1;=0A= +=0A= + return 0;=0A= +}=0A= +=0A= +static int=0A= +is_sc_insn (struct gdbarch *gdbarch, ULONGEST insn)=0A= +{=0A= + if (itype_op (insn) =3D=3D SC_OPCODE=0A= + || itype_op (insn) =3D=3D SCD_OPCODE)=0A= + return 1;=0A= +=0A= + if (rtype_op (insn) =3D=3D LLSC_R6_OPCODE=0A= + && rtype_funct (insn) =3D=3D SCE_FUNCT=0A= + && (insn & 0x40) =3D=3D 0)=0A= + return 1;=0A= +=0A= + /* Handle SC and SCP varieties. */=0A= + if (is_mipsr6_isa (gdbarch)=0A= + && rtype_op (insn) =3D=3D LLSC_R6_OPCODE=0A= + && (rtype_funct (insn) =3D=3D SC_R6_FUNCT=0A= + || rtype_funct (insn) =3D=3D SCD_R6_FUNCT=0A= + || rtype_funct (insn) =3D=3D SCE_FUNCT))=0A= + return 1;=0A= +=0A= + return 0;=0A= +}=0A= =0A= static std::vector=0A= mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)=0A= @@ -3950,10 +4303,11 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdb= arch, CORE_ADDR pc)=0A= int index;=0A= int last_breakpoint =3D 0; /* Defaults to 0 (no breakpoints placed). */= =0A= const int atomic_sequence_length =3D 16; /* Instruction sequence length.= */=0A= + int is_mipsr6 =3D is_mipsr6_isa (gdbarch);=0A= =0A= insn =3D mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL);=0A= /* Assume all atomic sequences start with a ll/lld instruction. */=0A= - if (itype_op (insn) !=3D LL_OPCODE && itype_op (insn) !=3D LLD_OPCODE)= =0A= + if (!is_ll_insn (gdbarch, insn))=0A= return {};=0A= =0A= /* Assume that no atomic sequence is longer than "atomic_sequence_length= " =0A= @@ -3983,28 +4337,72 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdb= arch, CORE_ADDR pc)=0A= return {}; /* fallback to the standard single-step code. */=0A= case 4: /* BEQ */=0A= case 5: /* BNE */=0A= - case 6: /* BLEZ */=0A= - case 7: /* BGTZ */=0A= case 20: /* BEQL */=0A= case 21: /* BNEL */=0A= - case 22: /* BLEZL */=0A= - case 23: /* BGTTL */=0A= + case 22: /* BLEZL (BLEZC, BGEZC, BGEC) */=0A= + case 23: /* BGTZL (BGTZC, BLTZC, BLTC) */=0A= + is_branch =3D 1;=0A= + break;=0A= + case 6: /* BLEZ (BLEZALC, BGEZALC, BGEUC) */=0A= + case 7: /* BGTZ (BGTZALC, BLTZALC, BLTUC) */=0A= + if (is_mipsr6)=0A= + {=0A= + /* BLEZALC, BGTZALC */=0A= + if (itype_rs (insn) =3D=3D 0 && itype_rt (insn) !=3D 0)=0A= + return {}; /* fallback to the standard single-step code. */=0A= + /* BGEZALC, BLTZALC */=0A= + else if (itype_rs (insn) =3D=3D itype_rt (insn)=0A= + && itype_rt (insn) !=3D 0)=0A= + return {}; /* fallback to the standard single-step code. */=0A= + }=0A= is_branch =3D 1;=0A= break;=0A= + case 8: /* BOVC, BEQZALC, BEQC */=0A= + case 24: /* BNVC, BNEZALC, BNEC */=0A= + if (is_mipsr6)=0A= + is_branch =3D 1;=0A= + break;=0A= + case 50: /* BC */=0A= + case 58: /* BALC */=0A= + if (is_mipsr6)=0A= + return {}; /* fallback to the standard single-step code. */=0A= + break;=0A= + case 54: /* BEQZC, JIC */=0A= + case 62: /* BNEZC, JIALC */=0A= + if (is_mipsr6)=0A= + {=0A= + if (itype_rs (insn) =3D=3D 0) /* JIC, JIALC */=0A= + return {}; /* fallback to the standard single-step code. */=0A= + else=0A= + is_branch =3D 2; /* Marker for branches with a 21-bit offset. */=0A= + }=0A= + break;=0A= case 17: /* COP1 */=0A= - is_branch =3D ((itype_rs (insn) =3D=3D 9 || itype_rs (insn) =3D=3D 10)= =0A= - && (itype_rt (insn) & 0x2) =3D=3D 0);=0A= - if (is_branch) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */=0A= + is_branch =3D ((!is_mipsr6=0A= + /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */=0A= + && (itype_rs (insn) =3D=3D 9 || itype_rs (insn) =3D=3D 10)=0A= + && (itype_rt (insn) & 0x2) =3D=3D 0)=0A= + /* BZ.df: 010001 110xx */=0A= + || (itype_rs (insn) & 0x18) =3D=3D 0x18);=0A= + if (is_branch)=0A= break;=0A= [[fallthrough]];=0A= case 18: /* COP2 */=0A= case 19: /* COP3 */=0A= - is_branch =3D (itype_rs (insn) =3D=3D 8); /* BCzF, BCzFL, BCzT, BCzTL *= /=0A= + /* BCzF, BCzFL, BCzT, BCzTL, BC*EQZ, BC*NEZ */=0A= + is_branch =3D ((itype_rs (insn) =3D=3D 8)=0A= + || (is_mipsr6=0A= + && (itype_rs (insn) =3D=3D 9=0A= + || itype_rs (insn) =3D=3D 13)));=0A= break;=0A= }=0A= if (is_branch)=0A= {=0A= - branch_bp =3D loc + mips32_relative_offset (insn) + 4;=0A= + /* Is this a special PC21_S2 branch? */=0A= + if (is_branch =3D=3D 2)=0A= + branch_bp =3D loc + mips32_relative_offset21 (insn) + 4;=0A= + else=0A= + branch_bp =3D loc + mips32_relative_offset (insn) + 4;=0A= if (last_breakpoint >=3D 1)=0A= return {}; /* More than one branch found, fallback to the=0A= standard single-step code. */=0A= @@ -4012,12 +4410,12 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdb= arch, CORE_ADDR pc)=0A= last_breakpoint++;=0A= }=0A= =0A= - if (itype_op (insn) =3D=3D SC_OPCODE || itype_op (insn) =3D=3D SCD_O= PCODE)=0A= + if (is_sc_insn (gdbarch, insn))=0A= break;=0A= }=0A= =0A= /* Assume that the atomic sequence ends with a sc/scd instruction. */= =0A= - if (itype_op (insn) !=3D SC_OPCODE && itype_op (insn) !=3D SCD_OPCODE)= =0A= + if (!is_sc_insn (gdbarch, insn))=0A= return {};=0A= =0A= loc +=3D MIPS_INSN32_SIZE;=0A= @@ -4242,8 +4640,14 @@ mips_about_to_return (struct gdbarch *gdbarch, CORE_= ADDR pc)=0A= gdb_assert (mips_pc_is_mips (pc));=0A= =0A= insn =3D mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);=0A= - hint =3D 0x7c0;=0A= - return (insn & ~hint) =3D=3D 0x3e00008; /* jr(.hb) $ra */=0A= + /* Mask the hint and the jalr/jr bit. */=0A= + hint =3D 0x7c1;=0A= +=0A= + if (is_mipsr6_isa (gdbarch) && insn =3D=3D 0xd81f0000) /* jrc $31 */=0A= + return 1;=0A= +=0A= + /* jr(.hb) $ra and "jalr(.hb) $ra" */=0A= + return ((insn & ~hint) =3D=3D 0x3e00008);=0A= }=0A= =0A= =0A= @@ -6760,7 +7164,9 @@ mips32_stack_frame_destroyed_p (struct gdbarch *gdbar= ch, CORE_ADDR pc)=0A= =0A= if (high_word !=3D 0x27bd /* addiu $sp,$sp,offset */=0A= && high_word !=3D 0x67bd /* daddiu $sp,$sp,offset */=0A= - && inst !=3D 0x03e00008 /* jr $ra */=0A= + && (inst & ~0x1) !=3D 0x03e00008 /* jr $31 or jalr $0, $31 */=0A= + && (!is_mipsr6_isa (gdbarch)=0A= + || inst !=3D 0xd81f0000) /* jrc $31 */=0A= && inst !=3D 0x00000000) /* nop */=0A= return 0;=0A= }=0A= @@ -7139,22 +7545,31 @@ mips32_instruction_has_delay_slot (struct gdbarch *= gdbarch, ULONGEST inst)=0A= int op;=0A= int rs;=0A= int rt;=0A= + int is_mipsr6 =3D is_mipsr6_isa (gdbarch);=0A= =0A= op =3D itype_op (inst);=0A= if ((inst & 0xe0000000) !=3D 0)=0A= {=0A= rs =3D itype_rs (inst);=0A= rt =3D itype_rt (inst);=0A= - return (is_octeon_bbit_op (op, gdbarch) =0A= - || op >> 2 =3D=3D 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */=0A= - || op =3D=3D 29 /* JALX: bits 011101 */=0A= + return (is_octeon_bbit_op (op, gdbarch)=0A= + || (op >> 1 =3D=3D 10) /* BEQL, BNEL: bits 01010x */=0A= + || (op >> 1 =3D=3D 11 && rt =3D=3D 0) /* BLEZL, BGTZL: bits 01011x = */=0A= + || (!is_mipsr6 && op =3D=3D 29) /* JALX: bits 011101 */=0A= || (op =3D=3D 17=0A= && (rs =3D=3D 8=0A= /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */=0A= - || (rs =3D=3D 9 && (rt & 0x2) =3D=3D 0)=0A= + || (!is_mipsr6 && rs =3D=3D 9 && (rt & 0x2) =3D=3D 0)=0A= /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */=0A= - || (rs =3D=3D 10 && (rt & 0x2) =3D=3D 0))));=0A= + || (!is_mipsr6 && rs =3D=3D 10 && (rt & 0x2) =3D=3D 0)))=0A= /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */=0A= + || (is_mipsr6=0A= + && ((op =3D=3D 17=0A= + && (rs =3D=3D 9 /* BC1EQZ: 010001 01001 */=0A= + || rs =3D=3D 13)) /* BC1NEZ: 010001 01101 */=0A= + || (op =3D=3D 18=0A= + && (rs =3D=3D 9 /* BC2EQZ: 010010 01001 */=0A= + || rs =3D=3D 13))))); /* BC2NEZ: 010010 01101 */=0A= }=0A= else=0A= switch (op & 0x07) /* extract bits 28,27,26 */=0A= @@ -7173,7 +7588,11 @@ mips32_instruction_has_delay_slot (struct gdbarch *g= dbarch, ULONGEST inst)=0A= || ((rt & 0x1e) =3D=3D 0x1c && rs =3D=3D 0));=0A= /* BPOSGE32, BPOSGE64: bits 1110x */=0A= break; /* end REGIMM */=0A= - default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */=0A= + case 6: /* BLEZ */=0A= + case 7: /* BGTZ */=0A= + return (itype_rt (inst) =3D=3D 0);=0A= + break;=0A= + default: /* J, JAL, BEQ, BNE */=0A= return 1;=0A= break;=0A= }=0A= @@ -7385,7 +7804,18 @@ mips_adjust_breakpoint_address (struct gdbarch *gdba= rch, CORE_ADDR bpaddr)=0A= =0A= So, we'll use the second solution. To do this we need to know if=0A= the instruction we're trying to set the breakpoint on is in the=0A= - branch delay slot. */=0A= + branch delay slot.=0A= +=0A= + A similar problem occurs for breakpoints on forbidden slots where=0A= + the trap will be reported for the branch with the BD bit set.=0A= + In this case it would be ideal to recover using solution 1 from=0A= + above as there is no problem with the branch being skipped=0A= + (since the forbidden slot only exists on not-taken branches).=0A= + However, the BD bit is not available in all scenarios currently=0A= + so instead we move the breakpoint on to the next instruction.=0A= + This means that it is not possible to stop on an instruction=0A= + that can be in a forbidden slot even if that instruction is=0A= + jumped to directly. */=0A= =0A= boundary =3D mips_segment_boundary (bpaddr);=0A= =0A= @@ -7407,6 +7837,12 @@ mips_adjust_breakpoint_address (struct gdbarch *gdba= rch, CORE_ADDR bpaddr)=0A= prev_addr =3D bpaddr - 4;=0A= if (mips32_insn_at_pc_has_delay_slot (gdbarch, prev_addr))=0A= bpaddr =3D prev_addr;=0A= + /* If the previous instruction has a forbidden slot, we have to=0A= + move the breakpoint to the following instruction to prevent=0A= + breakpoints in forbidden slots being reported as unknown=0A= + traps. */=0A= + else if (mips32_insn_at_pc_has_forbidden_slot (gdbarch, prev_addr))= =0A= + bpaddr +=3D 4;=0A= }=0A= else=0A= {=0A= diff --git a/gdb/testsuite/gdb.arch/mips-64-r6.c b/gdb/testsuite/gdb.arch/m= ips-64-r6.c=0A= new file mode 100644=0A= index 00000000000..833274cef36=0A= --- /dev/null=0A= +++ b/gdb/testsuite/gdb.arch/mips-64-r6.c=0A= @@ -0,0 +1,1469 @@=0A= +/*=0A= + Copyright 2006-2024 Free Software Foundation, Inc.=0A= +=0A= + This file is part of GDB.=0A= +=0A= + This program is free software; you can redistribute it and/or modify=0A= + it under the terms of the GNU General Public License as published by=0A= + the Free Software Foundation; either version 3 of the License, or=0A= + (at your option) any later version.=0A= +=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=0A= + You should have received a copy of the GNU General Public License=0A= + along with this program. If not, see .= =0A= +*/=0A= +=0A= +#include =0A= +=0A= +#define xstr(s) str(s)=0A= +#define str(s) #s=0A= +=0A= +/* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D macros from sim/testutils/mips/uti= ls-r6.inc =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */=0A= +=0A= +// 58 is local label to exit with errcode !=3D 0=0A= +#define fp_assert(a, b) "beq " xstr(a) ", " xstr(b) ", 1f \n\t" \=0A= + "nop \n\t" \=0A= + "b 58f \n\t" \=0A= + "nop \n\t" \=0A= + "1: \n\t"=0A= +=0A= +// Clobbers: $4,$6,$7=0A= +#define r6ck_1r(inst, a, ret) \=0A= + "li $4, " xstr(a) " \n\t" \=0A= + "li $6, " xstr(ret) " \n\t" \=0A= + xstr(inst) " $7, $4 \n\t" \=0A= + fp_assert($6, $7)=0A= +=0A= +// Clobbers: $4,$6,$7=0A= +#define r6ck_1dr(inst, a, ret) \=0A= + "ld $4, " xstr(a) " \n\t" \=0A= + "ld $6, " xstr(ret) " \n\t" \=0A= + xstr(inst) " $7, $4 \n\t" \=0A= + fp_assert($6, $7)=0A= +=0A= +// Clobbers: $4,$5,$6,$7=0A= +#define r6ck_2r(inst, a, b, ret) \=0A= + "li $4, " xstr(a) " \n\t" \=0A= + "li $5, " xstr(b) " \n\t" \=0A= + "li $6, " xstr(ret) " \n\t" \=0A= + xstr(inst) " $7, $4, $5 \n\t" \=0A= + fp_assert($6, $7)=0A= +=0A= +// Clobbers: $4,$5,$6,$7=0A= +#define r6ck_2dr(inst, a, b, ret) \=0A= + "ld $4, " xstr(a) " \n\t" \=0A= + "ld $5, " xstr(b) " \n\t" \=0A= + "ld $6, " xstr(ret) " \n\t" \=0A= + xstr(inst) " $7, $4, $5 \n\t" \=0A= + fp_assert($6, $7)=0A= +=0A= +// Clobbers: $4,$5,$6,$7=0A= +#define r6ck_2dr1i(inst, a, b, imm, ret) \=0A= + "ld $4, " xstr(a) " \n\t" \=0A= + "ld $5, " xstr(b) " \n\t" \=0A= + "ld $6, " xstr(ret) " \n\t" \=0A= + xstr(inst) " $7, $4, $5, " xstr(imm) " \n\t" \=0A= + fp_assert($6, $7)=0A= +=0A= +// Clobbers: $4,$6,$7=0A= +#define r6ck_1r1i(inst, a, imm, ret) \=0A= + "li $4, " xstr(a) " \n\t" \=0A= + "li $6, " xstr(ret) " \n\t" \=0A= + xstr(inst) " $7, $4, " xstr(imm) " \n\t" \=0A= + fp_assert($6, $7)=0A= +=0A= +// Clobbers: $4,$6,$7=0A= +#define r6ck_1dr1i(inst, a, imm, ret) \=0A= + "ld $4, " xstr(a) " \n\t" \=0A= + "ld $6, " xstr(ret) " \n\t" \=0A= + xstr(inst) " $7, $4, " xstr(imm) " \n\t" \=0A= + fp_assert($6, $7)=0A= +=0A= +// Clobbers: $4,$6=0A= +#define r6ck_0dr1i(inst, a, imm, ret) \=0A= + "ld $4, " xstr(a) " \n\t" \=0A= + "ld $6, " xstr(ret) " \n\t" \=0A= + xstr(inst) " $4, $4, " xstr(imm) " \n\t" \=0A= + fp_assert($6, $4)=0A= +=0A= +// Clobbers: $4,$5,$6,$7=0A= +#define r6ck_2r1i(inst, a, b, imm, ret) \=0A= + "li $4, " xstr(a) " \n\t" \=0A= + "li $5, " xstr(b) " \n\t" \=0A= + "li $6, " xstr(ret) " \n\t" \=0A= + xstr(inst) " $7, $4, $5, " xstr(imm) " \n\t" \=0A= + fp_assert($6, $7)=0A= +=0A= +// Clobbers: $4,$5,$6,$7,$8,$f2,$f4,$f6=0A= +#define r6ck_3s(inst, a, b, c, ret) \=0A= + "li $4, " xstr(a) " \n\t" \=0A= + "li $5, " xstr(b) " \n\t" \=0A= + "li $6, " xstr(c) " \n\t" \=0A= + "li $7, " xstr(ret) " \n\t" \=0A= + "mtc1 $4, $f2 \n\t" \=0A= + "mtc1 $5, $f4 \n\t" \=0A= + "mtc1 $6, $f6 \n\t" \=0A= + xstr(inst) " $f2, $f4, $f6 \n\t" \=0A= + "mfc1 $8, $f2 \n\t" \=0A= + fp_assert($7, $8)=0A= +=0A= +// Clobbers: $4,$5,$6,$7,$f2,$f4=0A= +#define r6ck_2s(inst, a, b, ret) \=0A= + "li $4, " xstr(a) " \n\t" \=0A= + "li $5, " xstr(b) " \n\t" \=0A= + "li $6, " xstr(ret) " \n\t" \=0A= + "mtc1 $4, $f2 \n\t" \=0A= + "mtc1 $5, $f4 \n\t" \=0A= + xstr(inst) " $f2, $f4 \n\t" \=0A= + "mfc1 $7, $f2 \n\t" \=0A= + fp_assert($6, $7)=0A= +=0A= +// Clobbers: $4,$5,$6,$7,$8,$9,$10,$f2,$f4=0A= +#define r6ck_2d(inst, a, b, ret) \=0A= + ".data \n\t" \=0A= +"1: .dword " xstr(a) " \n\t" \=0A= +"2: .dword " xstr(b) " \n\t" \=0A= +"3: .dword " xstr(ret) " \n\t" \=0A= +" .text \n\t" \=0A= + "la $4, 1b \n\t" \=0A= + "la $5, 2b \n\t" \=0A= + "la $6, 3b \n\t" \=0A= + "ldc1 $f2, 0($4) \n\t" \=0A= + "ldc1 $f4, 0($5) \n\t" \=0A= + "lw $7, 0($6) \n\t" \=0A= + "lw $8, 4($6) \n\t" \=0A= + xstr(inst) " $f2, $f4 \n\t" \=0A= + "mfhc1 $9, $f2 \n\t" \=0A= + "mfc1 $10, $f2 \n\t" \=0A= + fp_assert($7, $9) \=0A= + fp_assert($8, $10)=0A= +=0A= +// Clobbers: $2,$4,$5,$6,$7,$8,$9,$10,$f2,$f4,$f6=0A= +#define r6ck_3d(inst, a, b, c, ret) \=0A= + ".data \n\t" \=0A= +"1: .dword " xstr(a) " \n\t" \=0A= +"2: .dword " xstr(b) " \n\t" \=0A= +"3: .dword " xstr(c) " \n\t" \=0A= +"4: .dword " xstr(ret) " \n\t" \=0A= + ".text \n\t" \=0A= + "la $4, 1b \n\t" \=0A= + "la $5, 2b \n\t" \=0A= + "la $6, 3b \n\t" \=0A= + "la $2, 4b \n\t" \=0A= + "ldc1 $f2, 0($4) \n\t" \=0A= + "ldc1 $f4, 0($5) \n\t" \=0A= + "ldc1 $f6, 0($6) \n\t" \=0A= + "lw $7, 0($2) \n\t" \=0A= + "lw $8, 4($2) \n\t" \=0A= + xstr(inst) " $f2, $f4, $f6 \n\t" \=0A= + "mfhc1 $9, $f2 \n\t" \=0A= + "mfc1 $10, $f2 \n\t" \=0A= + fp_assert($7, $9) \=0A= + fp_assert($8, $10)=0A= +=0A= +=0A= +/* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D macros from sim/testutils/mips/tes= tutils.inc =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */=0A= +=0A= +/* Put value 'val' into register 'reg'=0A= + * Clobbers: None */=0A= +#define load32(reg, val) \=0A= + "li " xstr(reg) ", " xstr(val) " \n\t"=0A= +=0A= +/* Check whether two registers contain the same value=0A= + * Clobbers: None */=0A= +#define checkreg(reg, expreg) \=0A= + ".set push \n\t" \=0A= + ".set noat \n\t" \=0A= + ".set noreorder \n\t" \=0A= + "beq " xstr(expreg) ", " xstr(reg) ", 901f \n\t" \=0A= + "nop \n\t" \=0A= + "b 58f \n\t" \=0A= + "nop \n\t" \=0A= +"901: \n\t" \=0A= + ".set pop \n\t"=0A= +=0A= +/* Check if register 'reg' contains value 'val'.=0A= + * Clobbers: $1 */=0A= +#define check32(reg, val) \=0A= + ".set push \n\t" \=0A= + ".set noat \n\t" \=0A= + load32($1, val) \=0A= + checkreg(reg, $1) \=0A= + ".set pop \n\t"=0A= +=0A= +/* Checkpair based on endianess=0A= + * Clobbers: $1 */=0A= +#define checkpair_xendian(lo, hi, base, ec, w) \=0A= + ".set noat \n\t" \=0A= + "lw $1, " xstr(ec) " \n\t" \=0A= + "andi $1, $1, 0x1 \n\t" \=0A= + "beqz $1, 2f \n\t" \=0A= + ".set at \n\t" \=0A= +"1: \n\t" \=0A= + checkpair_be_##w(lo, hi, base) \=0A= + "b 3f \n\t" \=0A= + "nop \n\t" \=0A= +"2: \n\t" \=0A= + checkpair_le_##w(lo, hi, base) \=0A= +"3: \n\t"=0A= +=0A= +/*=0A= + checkpair_xendian($2, $3, test_data_2, end_check_2, d)=0A= +=3D=0A= +"lw $1, end_check_2 \n\t"=0A= +"andi $1, $1, 0x1 \n\t"=0A= +"beqz $1, 2f \n\t"=0A= +"1: \n\t"=0A= +checkpair_be_d($2, $3, test_data_2) =3D checkpair($2, $3, test_data_2, w, = 4, 0)=0A= +"b 3f \n\t"=0A= +"nop \n\t"=0A= +"2: \n\t"=0A= +checkpair_le_d($2, $3, test_data_2) =3D checkpair($2, $3, test_data_2, w, = 0, 4)=0A= +"3: \n\t"=0A= +*/=0A= +=0A= +/* Check hi-lo register pair against data stored at base+o1 and base+o2=0A= + * Clobbers: $1 - $5 */=0A= +#define checkpair(lo, hi, base, w, o1, o2) \=0A= + "move $2, " xstr(lo) " \n\t" \=0A= + "move $3, " xstr(hi) " \n\t" \=0A= + ".set noat \n\t" \=0A= + "la $1, " xstr(base) " \n\t" \=0A= + "l" xstr(w) " $4, " xstr(o1) "($1) \n\t" \=0A= + "l" xstr(w) " $5, " xstr(o2) "($1) \n\t" \=0A= + ".set at \n\t" \=0A= + checkreg($2, $4) \=0A= + checkreg($3, $5)=0A= +=0A= +#define checkpair_le_d(lo, hi, base) \=0A= + checkpair(lo, hi, base, w, 0, 4)=0A= +=0A= +#define checkpair_be_d(lo, hi, base) \=0A= + checkpair(lo, hi, base, w, 4, 0)=0A= +=0A= +=0A= +#define checkpair_le_q(lo, hi, base) \=0A= + checkpair(lo, hi, base, d, 0, 8)=0A= +=0A= +#define checkpair_be_q(lo, hi, base) \=0A= + checkpair(lo, hi, base, d, 8, 0)=0A= +=0A= +#define checkpair_qword(lo, hi, base, oe) \=0A= + checkpair_xendian(lo, hi, base, oe, q)=0A= +=0A= +#define checkpair_dword(lo, hi, base, oe) \=0A= + checkpair_xendian(lo, hi, base, oe, d)=0A= +=0A= +void abort (void);=0A= +=0A= +=0A= +int test_r6_branch()=0A= +{=0A= + // using volatile to prevent certain optimizations which could cause i= nstruction deletion=0A= + volatile int err =3D -1; // identifies instruction which caused error.= (err =3D=3D 0) =3D=3D> all instructions executed successfully=0A= +=0A= + volatile int a14 =3D 0xffffffff; // the other variables are bound to r= egisters=0A= + volatile int a13 =3D 0x123;=0A= + volatile int a12 =3D 0x45;=0A= + volatile int a7 =3D 0x45;=0A= + volatile int a8 =3D 0xfffffffe;=0A= + volatile int a9 =3D 2147483647;=0A= + volatile int a11 =3D 0;=0A= + volatile int a10 =3D 0;=0A= + asm (=0A= + ".set push \n\t" // create new scope for asm confi= guration=0A= + ".set noreorder \n\t" // don't allow reordering of inst= ructions=0A= + "li %[err], 1 \n\t"=0A= + "bovc %[a12], %[a13], Lfail \n\t" // BOVC=0A= + "nop \n\t"=0A= + "bovc %[a9], %[a13], L2 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L2: \n\t"=0A= + "li %[err], 2 \n\t"=0A= + "bnvc %[a9], %[a13], Lfail \n\t" // BNVC=0A= + "nop \n\t"=0A= + "bnvc %[a12], %[a13], L3 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L3: \n\t"=0A= + "li %[err], 3 \n\t"=0A= + "beqc %[a12], %[a13], Lfail \n\t" // BEQC=0A= + "nop \n\t"=0A= + "beqc %[a12], %[a7], L4 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L4: \n\t"=0A= + "li %[err], 4 \n\t"=0A= + "bnec %[a12], %[a7], Lfail \n\t" // BNEC=0A= + "nop \n\t"=0A= + "bnec %[a12], %[a13], L5 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L5: \n\t"=0A= + "li %[err], 5 \n\t"=0A= + "bltc %[a13], %[a12], Lfail \n\t" // BLTC=0A= + "nop \n\t"=0A= + "bltc %[a12], %[a13], L6 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L6: \n\t"=0A= + "L7: \n\t"=0A= + "li %[err], 7 \n\t"=0A= + "bgec %[a12], %[a13], Lfail \n\t" // BGEC=0A= + "nop \n\t"=0A= + "bgec %[a13], %[a12], L8 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L8: \n\t"=0A= + "L9: \n\t"=0A= + "li %[err], 9 \n\t"=0A= + "bltuc %[a14], %[a13], Lfail \n\t" // BLTUC=0A= + "nop \n\t"=0A= + "bltuc %[a8], %[a14], L10 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L10: \n\t"=0A= + "L11: \n\t"=0A= + "li %[err], 11 \n\t"=0A= + "bgeuc %[a13], %[a14], Lfail \n\t" // BGEUC=0A= + "nop \n\t"=0A= + "bgeuc %[a14], %[a8], L12 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L12: \n\t"=0A= + "L13: \n\t"=0A= + "li %[err], 13 \n\t"=0A= + "bltzc %[a13], Lfail \n\t" // BLTZC=0A= + "nop \n\t"=0A= + "bltzc %[a11], Lfail \n\t"=0A= + "nop \n\t"=0A= + "bltzc %[a14], L14 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L14: \n\t"=0A= + "li %[err], 14 \n\t"=0A= + "blezc %[a13], Lfail \n\t" // BLEZC=0A= + "nop \n\t"=0A= + "blezc %[a11], L145 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L145: \n\t"=0A= + "blezc %[a14], L15 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L15: \n\t"=0A= + "li %[err], 15 \n\t"=0A= + "bgezc %[a8], Lfail \n\t" // BGEZC=0A= + "nop \n\t"=0A= + "bgezc %[a11], L155 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L155: \n\t"=0A= + "bgezc %[a13], L16 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L16: \n\t"=0A= + "li %[err], 16 \n\t"=0A= + "bgtzc %[a8], Lfail \n\t" // BGTZC=0A= + "nop \n\t"=0A= + "bgtzc %[a11], Lfail \n\t"=0A= + "nop \n\t"=0A= + "bgtzc %[a13], L17 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "li %[a10], 0 \n\t"=0A= + "L17: \n\t"=0A= + "li %[err], 17 \n\t"=0A= + "blezalc %[a12], Lfail \n\t" // BLEZALC=0A= + "nop \n\t"=0A= + "blezalc %[a11], Lret \n\t"=0A= + "li %[a10], 1 \n\t"=0A= + "beqzc %[a10], L175 \n\t" // BEQZC=0A= + "nop \n\t"=0A= + "li %[err], 8531 \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L175: \n\t"=0A= + "li %[err], 23531 \n\t"=0A= + "blezalc %[a14], Lret \n\t"=0A= + "li %[a10], 1 \n\t"=0A= + "beqzc %[a10], L18 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L18: \n\t"=0A= + "li %[err], 18 \n\t"=0A= + "bgezalc %[a14], Lfail \n\t" // BGEZALC=0A= + "nop \n\t"=0A= + "bgezalc %[a11], Lret \n\t"=0A= + "li %[a10], 1 \n\t"=0A= + "beqzc %[a10], L185 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L185: \n\t"=0A= + "bgezalc %[a12], Lret \n\t"=0A= + "li %[a10], 1 \n\t"=0A= + "beqzc %[a10], L19 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L19: \n\t"=0A= + "li %[err], 19 \n\t"=0A= + "bgtzalc %[a14], Lfail \n\t" // BGTZALC=0A= + "nop \n\t"=0A= + "bgtzalc %[a11], Lfail \n\t"=0A= + "nop \n\t"=0A= + "bgtzalc %[a12], Lret \n\t"=0A= + "li %[a10], 1 \n\t"=0A= + "beqzc %[a10], L20 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L20: \n\t"=0A= + "li %[err], 20 \n\t"=0A= + "bltzalc %[a12], Lfail \n\t" // BLTZALC=0A= + "nop \n\t"=0A= + "bltzalc %[a11], Lfail \n\t"=0A= + "nop \n\t"=0A= + "bltzalc %[a14], Lret \n\t"=0A= + "li %[a10], 1 \n\t"=0A= + "beqzc %[a10], L21 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L21: \n\t"=0A= + "li %[err], 21 \n\t"=0A= + "bc L22 \n\t" // BC=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L22: \n\t"=0A= + "li %[err], 22 \n\t"=0A= + "balc Lret \n\t" // BALC=0A= + "li %[a10], 1 \n\t"=0A= + "beqzc %[a10], L23 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L23: \n\t"=0A= + "li %[err], 23 \n\t"=0A= + "jal GetPC \n\t" // JAL=0A= + "nop \n\t"=0A= + "jic $6, 4 \n\t" // JIC=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L24: \n\t"=0A= + "li %[err], 24 \n\t"=0A= + "li %[a10], 1 \n\t"=0A= + "jal GetPC \n\t"=0A= + "nop \n\t"=0A= + "jialc $6, 20 \n\t" // JIALC=0A= + "nop \n\t"=0A= + "beqzc %[a10], L25 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "LJIALCRET: \n\t"=0A= + "li %[a10], 0 \n\t"=0A= + "jr $31 \n\t" // JR=0A= + "nop \n\t"=0A= + "L25: \n\t"=0A= + "li %[err], 25 \n\t"=0A= + "jal GetPC \n\t"=0A= + "nop \n\t"=0A= + "move %[a11], $6 \n\t"=0A= + "nal \n\t"=0A= + "nop \n\t"=0A= + "addiu %[a11], 12 \n\t" // ADDIU=0A= + "beqc %[a11], $31, L26 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L26: \n\t"=0A= + "li %[err], 26 \n\t"=0A= + "balc Lret \n\t"=0A= + "li %[a10], 1 \n\t"=0A= + "beqzc %[a10], Lend \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "Lret: \n\t"=0A= + "li %[a10], 0 \n\t"=0A= + "daddiu $31, 4 \n\t" // DADDIU=0A= + "jrc $31 \n\t" // JRC=0A= + "nop \n\t"=0A= + "GetPC: \n\t"=0A= + "move $6, $31 \n\t"=0A= + "jr $31 \n\t"=0A= + "Lend: \n\t"=0A= + "li %[err], 0 \n\t"=0A= + "Lfail: \n\t"=0A= + ".set pop \n\t" // restore previous config=0A= + : [err] "+r"(err), [a14] "+r"(a14), [a13] "+r"(a13), [a12] "+r"(a12),= =0A= + [a7] "+r"(a7), [a8] "+r"(a8), [a9] "+r"(a9), [a10] "+r"(a10), [a11] "+= r"(a11)=0A= + : // inputs=0A= + : "$31", "$6" // clobbers=0A= +=0A= + );=0A= +=0A= + return err;=0A= +=0A= +}=0A= +=0A= +int test_r6_forbidden()=0A= +{=0A= + volatile int err =3D -1;=0A= + volatile int a4 =3D 0;=0A= + volatile int a2 =3D 0;=0A= + volatile int a1 =3D 0;=0A= +=0A= + asm(=0A= + ".set push \n\t"=0A= + ".set noreorder \n\t"=0A= + "li %[err], 1 \n\t" // Test if FS is ignored when= branch is taken=0A= + "li %[a4], 0 \n\t"=0A= + "beqzalc %[a4], L41 \n\t"=0A= + "li %[err], -85 \n\t"=0A= + "L42: \n\t"=0A= + "b Lfail2 \n\t"=0A= + "nop \n\t"=0A= + "L41: \n\t"=0A= + "blez %[err], Lfail2 \n\t"=0A= + "li %[err], 2 \n\t" // Test if FS is used when br= anch is not taken=0A= + "li %[a4], 1 \n\t"=0A= + "blezc %[a4], L43 \n\t"=0A= + "addiu %[a4], %[a4], 1 \n\t"=0A= + "li %[a2], 2 \n\t"=0A= + "beq %[a4], %[a2], L44 \n\t"=0A= + "nop \n\t"=0A= + "L43: \n\t"=0A= + "nop \n\t"=0A= + "b Lfail2 \n\t"=0A= + "nop \n\t"=0A= + "L44: \n\t"=0A= + "li %[err], 3 \n\t" // Test if FS causes an error= when it contains a branch=0A= + "li %[a4], 3 \n\t"=0A= + "beqzalc %[a4], Lfail2 \n\t"=0A= + "nop \n\t" // Note: bc L45 here causes S= egmentation Fault: Illegal instruction which is OK.=0A= + "b Lend2 \n\t"=0A= + "nop \n\t"=0A= + "L45: \n\t"=0A= + "nop \n\t"=0A= + "b Lfail2 \n\t"=0A= + "nop \n\t"=0A= + "Lend2: \n\t"=0A= + "li %[err], 0 \n\t"=0A= + "Lfail2: \n\t"=0A= + "nop \n\t"=0A= + ".set pop \n\t"=0A= +=0A= + : [err] "+r" (err), [a4] "+r"(a4), [a2] "+r"(a2), [a1] "+r"(a1) // o= utputs=0A= + : // inputs=0A= + : "$31" // clobbers=0A= + );=0A= +=0A= + return err;=0A= +}=0A= +=0A= +int test_r6_64()=0A= +{=0A= + volatile int err =3D 0;=0A= +=0A= + asm(=0A= + ".set push \n\t"=0A= + ".set noreorder \n\t"=0A= + ".data \n\t"=0A= + "d0: .dword 0 \n\t"=0A= + "dval: .dword 0xaa55bb66cc77dd88 \n\t"=0A= + "d1: .dword 0xaaaabbbbccccdddd \n\t"=0A= + "d2: .dword 256 \n\t"=0A= + "dlo: .dword 0xaabbbbccccdddd00 \n\t"=0A= + "dhi: .dword 0xffffffffffffffaa \n\t"=0A= + "dhiu: .dword 0x00000000000000aa \n\t"=0A= + "d3: .dword 0xffaaaabbbbccccde \n\t"=0A= + "d4: .dword 0xffffffffffffffdd \n\t"=0A= + "d5: .dword 0x00000000000000dd \n\t"=0A= + "d6: .dword 0x00aaaabbbbccccdd \n\t"=0A= + "d7: .dword 0xeeeeffff00001111 \n\t"=0A= + "d8: .dword 0xbbccccddddeeeeff \n\t"=0A= + "d9: .dword 0x000000ddaaaabbbb \n\t"=0A= + "d10: .dword 0x5555dddd3333bbbb \n\t"=0A= + "d11: .dword 0x9999999999999999 \n\t"=0A= + "d12: .dword 56 \n\t"=0A= + "d13: .dword 8 \n\t"=0A= + "d14: .dword 57 \n\t"=0A= + "d15: .dword 0x000000ddaaaac98b \n\t"=0A= + "d16: .dword 0xffffffffdead00dd \n\t"=0A= + "d17: .dword 0xffffffffc0de0000 \n\t"=0A= + "d18: .dword 0x0000123400000000 \n\t"=0A= + "d19: .dword 0xffffabcddead00dd \n\t"=0A= + "d20: .dword 0xc0de000000000000 \n\t"=0A= + "d21: .dword 0x8000abcddead00dd \n\t"=0A= + "dmask:.dword 0xffffffffffff0000 \n\t"=0A= + "dval1: .word 0x1234abcd \n\t"=0A= + "dval2: .word 0xffee0000 \n\t"=0A= + "dval3: .dword 0xffffffffffffffff \n\t"=0A= + " .fill 240,1,0 \n\t"=0A= + "dval4: .dword 0x5555555555555555 \n\t"=0A= + " .fill 264,1,0 \n\t"=0A= + "dval5: .dword 0xaaaaaaaaaaaaaaaa \n\t"=0A= +=0A= + // Register $11 stores instruction currently being tested and hence id= entifies error if it occurs=0A= + ".text \n\t"=0A= + "li $11, 1 \n\t" // Test DMUL=0A= + r6ck_2r(dmul, 6, 5, 30)=0A= + r6ck_2r(dmul, -7, 9, -63)=0A= + r6ck_2r(dmul, -1, 1, -1)=0A= + r6ck_2dr(dmul, d1, d2, dlo)=0A= +=0A= + "li $11, 2 \n\t" // Test DMUH=0A= + r6ck_2r(dmuh, 6, 5, 0)=0A= + r6ck_2r(dmuh, -7, 9, 0xffffffffffffffff)=0A= + r6ck_2r(dmuh, -1, 1, -1)=0A= + r6ck_2dr(dmuh, d1, d2, dhi)=0A= +=0A= + "li $11, 3 \n\t" // Test DMULU=0A= + r6ck_2r(dmulu, 12, 10, 120)=0A= + r6ck_2r(dmulu, -1, 1, -1)=0A= + r6ck_2dr(dmulu, d1, d2, dlo)=0A= +=0A= + "li $11, 4 \n\t" // Test DMUHU=0A= + r6ck_2r(dmuhu, 12, 10, 0)=0A= + r6ck_2r(dmuhu, -1, 1, 0)=0A= + r6ck_2dr(dmuhu, d1, d2, dhiu)=0A= +=0A= + "li $11, 5 \n\t" // Test DDIV=0A= + r6ck_2r(ddiv, 10001, 10, 1000)=0A= + r6ck_2r(ddiv, -123456, 560, -220)=0A= + r6ck_2dr(ddiv, d1, d2, d3)=0A= +=0A= + "li $11, 6 \n\t" // Test DMOD=0A= + r6ck_2r(dmod, 10001, 10, 1)=0A= + r6ck_2r(dmod, -123456, 560, 0xffffffffffffff00)=0A= + r6ck_2dr(dmod, d1, d2, d4)=0A= +=0A= + "li $11, 7 \n\t" // Test DDIVU=0A= + r6ck_2r(ddivu, 9, 100, 0)=0A= + r6ck_2dr(ddivu, d1, d2, d6)=0A= +=0A= + "li $11, 8 \n\t" // Test DMODU=0A= + r6ck_2r(dmodu, 9, 100, 9)=0A= + r6ck_2dr(dmodu, d1, d2, d5)=0A= +=0A= + "li $11, 9 \n\t" // Test DALIGN=0A= + r6ck_2dr1i(dalign, d7, d1, 3, d8)=0A= + r6ck_2dr1i(dalign, d1, d5, 4, d9)=0A= +=0A= + "li $11, 10 \n\t" // Test DBITSWAP=0A= + r6ck_1dr(dbitswap, d1, d10)=0A= + r6ck_1dr(dbitswap, d11, d11)=0A= +=0A= + "li $11, 11 \n\t" // Test DCLZ=0A= + r6ck_1dr(dclz, d5, d12)=0A= + r6ck_1dr(dclz, d6, d13)=0A= +=0A= + "li $11, 12 \n\t" // Test DCLO=0A= + r6ck_1dr(dclo, d5, d0)=0A= + r6ck_1dr(dclo, dhi, d14)=0A= +=0A= + "li $11, 13 \n\t" // Test DLSA=0A= + r6ck_2r1i(dlsa, 0x82, 0x2000068, 4, 0x2000888)=0A= + r6ck_2dr1i(dlsa, d5, d9, 4, d15)=0A= +=0A= + "li $11, 14 \n\t" // Test DAUI=0A= + r6ck_1dr1i(daui, d5, 0xdead, d16)=0A= + r6ck_1dr1i(daui, d0, 0xc0de, d17)=0A= +=0A= + "li $11, 15 \n\t" // Test DAHI=0A= + r6ck_0dr1i(dahi, d0, 0x1234, d18)=0A= + r6ck_0dr1i(dahi, d16, 0xabce, d19)=0A= +=0A= + "li $11, 16 \n\t" // Test DATI=0A= + r6ck_0dr1i(dati, d0, 0xc0de, d20)=0A= + r6ck_0dr1i(dati, d19, 0x8001, d21)=0A= +=0A= + "li $11, 17 \n\t" // Test LDPC=0A= + "ld $5, dval \n\t"=0A= + "nop \n\t"=0A= + "ldpc $4, dval \n\t"=0A= + fp_assert($4, $5)=0A= +=0A= + "li $11, 18 \n\t" // Test LWUPC=0A= + "lwu $5, dval1 \n\t"=0A= + "lwupc $4, dval1 \n\t"=0A= + fp_assert($4, $5)=0A= + "lwu $5, dval2 \n\t"=0A= + "lwupc $4, dval2 \n\t"=0A= + fp_assert($4, $5)=0A= +=0A= + "li $11, 19 \n\t" // Test LLD=0A= + "ld $5, dval3 \n\t"=0A= + "dla $3, dval4 \n\t"=0A= + "lld $4, -248($3) \n\t"=0A= + fp_assert($4, $5)=0A= +=0A= + "li $11, 20 \n\t" // Test SCD=0A= + "lld $4, -248($3) \n\t"=0A= + "dli $4, 0xafaf \n\t"=0A= + "scd $4, -248($3) \n\t"=0A= + "ld $5, dval3 \n\t"=0A= + "dli $4, 0xafaf \n\t"=0A= + fp_assert($4, $5)=0A= +=0A= + "Lend3: \n\t"=0A= + "li $11, 0 \n\t"=0A= + "58: \n\t"=0A= + "move %[err], $11 \n\t"=0A= + ".set pop \n\t"=0A= + : [err] "+r" (err) // outputs=0A= + : // inputs=0A= + : "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10", "$11" // clobbers= =0A= + );=0A= +=0A= + return err;=0A= +}=0A= +=0A= +int test_r6()=0A= +{=0A= + volatile int err =3D 0;=0A= +=0A= + asm(=0A= + ".set push \n\t"=0A= + ".set noreorder \n\t"=0A= + ".data \n\t"=0A= + "dval_1: .word 0xabcd1234 \n\t"=0A= + "dval_2: .word 0x1234eeff \n\t"=0A= + ".fill 248,1,0 \n\t"=0A= + "dval_3: .word 0x55555555 \n\t"=0A= + ".fill 260,1,0 \n\t"=0A= + "dval_4: .word 0xaaaaaaaa \n\t"=0A= + ".text \n\t"=0A= + "li $11, 1 \n\t" // Te= st MUL=0A= + r6ck_2r(mul, 7, 9, 63)=0A= + r6ck_2r(mul, -7, -9, 63)=0A= + r6ck_2r(mul, 61, -11, -671)=0A= + r6ck_2r(mul, 1001, 1234, 1235234)=0A= + r6ck_2r(mul, 123456789, 999999, 0x7eb1e22b)=0A= + r6ck_2r(mul, 0xaaaabbbb, 0xccccdddd, 0x56787f6f)=0A= + "li $11, 2 \n\t" // Te= st MUH=0A= + r6ck_2r(muh, 61, -11, 0xffffffff)=0A= + r6ck_2r(muh, 1001, 1234, 0)=0A= + r6ck_2r(muh, 123456789, 999999, 0x7048)=0A= + r6ck_2r(muh, 0xaaaabbbb, 0xccccdddd, 0x111107f7)=0A= + "li $11, 3 \n\t" // Te= st MULU=0A= + r6ck_2r(mulu, 7, 9, 63)=0A= + r6ck_2r(mulu, -7, -9, 63)=0A= + r6ck_2r(mulu, 61, -11, -671)=0A= + r6ck_2r(mulu, 1001, 1234, 1235234)=0A= + r6ck_2r(mulu, 123456789, 999999, 0x7eb1e22b)=0A= + r6ck_2r(mulu, 0xaaaabbbb, 0xccccdddd, 0x56787f6f)=0A= + "li $11, 4 \n\t" // Te= st MUHU=0A= + r6ck_2r(muhu, 1001, 1234, 0)=0A= + r6ck_2r(muhu, 123456789, 999999, 0x7048)=0A= + r6ck_2r(muhu, 0xaaaabbbb, 0xccccdddd, 0x8888a18f)=0A= + r6ck_2r(muhu, 0xaaaabbbb, 0xccccdddd, 0x8888a18f)=0A= + "li $11, 5 \n\t" // Te= st DIV=0A= + r6ck_2r(div, 10001, 10, 1000)=0A= + r6ck_2r(div, -123456, 560, -220)=0A= + r6ck_2r(div, 9, 100, 0)=0A= + "li $11, 6 \n\t" // Te= st MOD=0A= + r6ck_2r(mod, 10001, 10, 1)=0A= + r6ck_2r(mod, -123456, 560, 0xffffff00)=0A= + r6ck_2r(mod, 9, 100, 9)=0A= + "li $11, 7 \n\t" // Te= st DIVU=0A= + r6ck_2r(divu, 10001, 10, 1000)=0A= + r6ck_2r(divu, -123456, 560, 0x750674)=0A= + r6ck_2r(divu, 9, 100, 0)=0A= + r6ck_2r(divu, 0xaaaabbbb, 3, 0x38e393e9)=0A= + "li $11, 8 \n\t" // Te= st MODU=0A= + r6ck_2r(modu, 10001, 10, 1)=0A= + r6ck_2r(modu, -123456, 560, 0)=0A= + r6ck_2r(modu, 9, 100, 9)=0A= + r6ck_2r(modu, 0xaaaabbbb, 5, 4)=0A= + "li $11, 9 \n\t" // Te= st LSA=0A= + r6ck_2r1i(lsa, 1, 2, 2, 6)=0A= + r6ck_2r1i(lsa, 0x8000, 0xa000, 1, 0x1a000)=0A= + r6ck_2r1i(lsa, 0x82, 0x2000068, 4, 0x2000888)=0A= + "li $11, 10 \n\t" // T= est AUI=0A= + r6ck_1r1i(aui, 0x0000c0de, 0xdead, 0xdeadc0de)=0A= + r6ck_1r1i(aui, 0x00005678, 0x1234, 0x12345678)=0A= + r6ck_1r1i(aui, 0x0000eeff, 0xabab, 0xababeeff)=0A= + "li $11, 11 \n\t" // T= est SELEQZ=0A= + r6ck_2r(seleqz, 0x1234, 0, 0x1234)=0A= + r6ck_2r(seleqz, 0x1234, 4, 0)=0A= + r6ck_2r(seleqz, 0x80010001, 0, 0x80010001)=0A= + "li $11, 12 \n\t" // T= est SELNEZ=0A= + r6ck_2r(selnez, 0x1234, 0, 0)=0A= + r6ck_2r(selnez, 0x1234, 1, 0x1234)=0A= + r6ck_2r(selnez, 0x80010001, 0xffffffff, 0x80010001)=0A= + "li $11, 13 \n\t" // T= est ALIGN=0A= + r6ck_2r1i(align, 0xaabbccdd, 0xeeff0011, 1, 0xff0011aa)=0A= + r6ck_2r1i(align, 0xaabbccdd, 0xeeff0011, 3, 0x11aabbcc)=0A= + "li $11, 14 \n\t" // T= est BITSWAP=0A= + r6ck_1r(bitswap, 0xaabbccdd, 0x55dd33bb)=0A= + r6ck_1r(bitswap, 0x11884422, 0x88112244)=0A= + "li $11, 15 \n\t" // T= est CLZ=0A= + r6ck_1r(clz, 0x00012340, 15)=0A= + r6ck_1r(clz, 0x80012340, 0)=0A= + r6ck_1r(clz, 0x40012340, 1)=0A= + "li $11, 16 \n\t" // T= est CLO=0A= + r6ck_1r(clo, 0x00123050, 0)=0A= + r6ck_1r(clo, 0xff123050, 8)=0A= + r6ck_1r(clo, 0x8f123050, 1)=0A= + "li $11, 17 \n\t" // Test= ADDIUPC=0A= + //fp_assert($4, $11) // =3D=3D=3D=3D VERIFY: all good till this line.= GetPC_2 call may cause issues =3D=3D=3D=3D=3D=3D=3D=0A= + "jal GetPC_2 \n\t"=0A= + "nop \n\t"=0A= + "addiu $4, $6, 8 \n\t"=0A= + "addiupc $5, 4 \n\t"=0A= + fp_assert($4, $5)=0A= + "li $11, 18 \n\t" // Test= AUIPC=0A= + "jal GetPC_2 \n\t"=0A= + "nop \n\t"=0A= + "addiu $4, $6, 8 \n\t"=0A= + "aui $4, $4, 8 \n\t"=0A= + "auipc $5, 8 \n\t"=0A= + fp_assert($4, $5)=0A= + "li $11, 19 \n\t" // Test= ALUIPC=0A= + "jal GetPC_2 \n\t"=0A= + "nop \n\t"=0A= + "addiu $4, $6, 16 \n\t"=0A= + "aui $4, $4, 8 \n\t"=0A= + "li $7, 0xffff0000 \n\t"=0A= + "and $4, $4, $7 \n\t"=0A= + "aluipc $5, 8 \n\t"=0A= + fp_assert($4, $5)=0A= + "li $11, 20 \n\t" // Test= LWPC=0A= + "lw $5, dval_1 \n\t"=0A= + "lwpc $4, dval_1 \n\t"=0A= + fp_assert($4, $5)=0A= + "lw $5, dval_2 \n\t"=0A= + "lwpc $4, dval_2 \n\t"=0A= + fp_assert($4, $5)=0A= + "li $11, 21 \n\t" // Test= LL !! NOTE: May be redundant LL because SC already contains LL in its test= =0A= + "lw $5, dval_2 \n\t"=0A= + "dla $3, dval_3 \n\t" // amme= ndment: 'la' -> 'dla' to load 64-bit address=0A= + "ll $4, -252($3) \n\t"=0A= + fp_assert($4, $5)=0A= + "li $11, 22 \n\t" // Test= SC=0A= + "ll $4, -252($3) \n\t"=0A= + "li $4, 0xafaf \n\t"=0A= + "sc $4, -252($3) \n\t"=0A= + "lw $5, dval_2 \n\t"=0A= + "li $4, 0xafaf \n\t"=0A= + fp_assert($4, $5)=0A= + "b Lend4 \n\t"=0A= + "nop \n\t"=0A= + "GetPC_2: \n\t"=0A= + "move $6, $31 \n\t"=0A= + "jr $31 \n\t"=0A= + "Lend4: \n\t"=0A= + "li $11, 0 \n\t"=0A= + "58: \n\t"=0A= + "move %[err], $11 \n\t"=0A= + ".set pop \n\t"=0A= + : [err] "+r"(err) // outputs=0A= + : // inputs=0A= + : "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10", "$11", "$31" // c= lobbers=0A= + );=0A= +=0A= + return err;=0A= +}=0A= +=0A= +=0A= +// **bc1eq/eqz are enough=0A= +=0A= +int test_r6_fpu()=0A= +{=0A= + volatile int err =3D 0;=0A= +=0A= + asm(=0A= + ".set push \n\t"=0A= + ".set noreorder \n\t"=0A= + "li $11, 1 \n\t" // Test qNaN format is 75= 4-2008"=0A= + "li $4, 0x0 \n\t"=0A= + "li $5, 0x0 \n\t"=0A= + "li $6, 0x7fc00000 \n\t"=0A= + "mtc1 $4, $f2 \n\t"=0A= + "mtc1 $5, $f4 \n\t"=0A= + "div.s $f6, $f2, $f4 \n\t"=0A= + "mfc1 $8, $f6 \n\t"=0A= + fp_assert($6, $8)=0A= + "li $11, 2 \n\t" // Test maddf.s=0A= + r6ck_3s(maddf.s, 0x0, 0x0, 0x0, 0x0)=0A= + r6ck_3s(maddf.s, 0x3f800000, 0x3f800000, 0x3f800000, 0x40000000)=0A= + r6ck_3s(maddf.s, 0xc0b1f5c3, 0x40490fd0, 0x402df854, 0x403e9f5d)=0A= +=0A= + "li $11, 3 \n\t" // Test maddf.d=0A= + r6ck_3d(maddf.d, 0x0, 0x0, 0x0, 0x0)=0A= + r6ck_3d(maddf.d, 0x3ff0000000000000, 0x3ff0000000000000, 0x3ff0000000000= 000, 0x4000000000000000)=0A= + r6ck_3d(maddf.d, 0xc0163eb851eb851f, 0x400921f9f01b866e, 0x4005bf0a8b249= 19b, 0x4007d3ebc14f6cee)=0A= +=0A= + "li $11, 4 \n\t" // Test msubf.s=0A= + r6ck_3s(msubf.s, 0x0, 0x0, 0x0, 0x0)=0A= + r6ck_3s(msubf.s, 0x3f800000, 0x3f800000, 0x3f800000, 0x0)=0A= + r6ck_3s(msubf.s, 0xc0b1f5c3, 0x40490fd0, 0x402df854, 0xc1619d9a)=0A= +=0A= + "li $11, 5 \n\t" // Test msubf.d=0A= + r6ck_3d(msubf.d, 0x0, 0x0, 0x0, 0x0)=0A= + r6ck_3d(msubf.d, 0x3ff0000000000000, 0x3ff0000000000000, 0x3ff0000000000= 000, 0x0)=0A= + r6ck_3d(msubf.d, 0xc0163eb851eb851f, 0x400921f9f01b866e, 0x4005bf0a8b249= 19b, 0xc02c33b3423f605b)=0A= +=0A= + "li $11, 6 \n\t" // Test cmp.af.s=0A= + r6ck_3s(cmp.af.s, 0x0, 0x3f800000, 0x3f800000, 0x0)=0A= + r6ck_3s(cmp.af.s, 0x0, 0x00000000, 0x3f800000, 0x0)=0A= +=0A= + "li $11, 7 \n\t" // Test cmp.af.d=0A= + r6ck_3d(cmp.af.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0x0)=0A= + r6ck_3d(cmp.af.d, 0x0, 0x0000000000000000, 0x3ff0000000000000, 0x0)=0A= +=0A= + "li $11, 8 \n\t" // Test cmp.eq.s=0A= + r6ck_3s(cmp.eq.s, 0x0, 0x3f800000, 0x3f800000, 0xffffffff)=0A= + r6ck_3s(cmp.eq.s, 0x0, 0x00000000, 0x3f800000, 0x0)=0A= + r6ck_3s(cmp.eq.s, 0x0, 0x80000000, 0x00000000, 0xffffffff)=0A= + r6ck_3s(cmp.eq.s, 0x0, 0x7fc00000, 0x7fc00000, 0x0)=0A= + r6ck_3s(cmp.eq.s, 0x0, 0x7fc00000, 0xffc00000, 0x0)=0A= + r6ck_3s(cmp.eq.s, 0x0, 0x7fa00000, 0x7fa00000, 0x0)=0A= + r6ck_3s(cmp.eq.s, 0x0, 0x7fa00000, 0x7fc00000, 0x0)=0A= + r6ck_3s(cmp.eq.s, 0x0, 0x7f800000, 0x7f800000, 0xffffffff)=0A= + r6ck_3s(cmp.eq.s, 0x0, 0xff800000, 0xff800000, 0xffffffff)=0A= +=0A= + "li $11, 9 \n\t" // Test cmp.eq.d=0A= + r6ck_3d(cmp.eq.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0xfffffff= fffffffff)=0A= + r6ck_3d(cmp.eq.d, 0x0, 0x0000000000000000, 0x3ff0000000000000, 0x0)=0A= + r6ck_3d(cmp.eq.d, 0x0, 0x8000000000000000, 0x0000000000000000, 0xfffffff= fffffffff)=0A= + r6ck_3d(cmp.eq.d, 0x0, 0x7ff8000000000000, 0x7ff8000000000000, 0x0)=0A= + r6ck_3d(cmp.eq.d, 0x0, 0x7ff8000000000000, 0xffc0000000000000, 0x0)=0A= + r6ck_3d(cmp.eq.d, 0x0, 0x7fa0000000000000, 0x7fa0000000000000, 0xfffffff= fffffffff)=0A= + r6ck_3d(cmp.eq.d, 0x0, 0x7fa0000000000000, 0x7ff8000000000000, 0x0)=0A= + r6ck_3d(cmp.eq.d, 0x0, 0x7ff0000000000000, 0x7ff0000000000000, 0xfffffff= fffffffff)=0A= + r6ck_3d(cmp.eq.d, 0x0, 0xfff0000000000000, 0xfff0000000000000, 0xfffffff= fffffffff)=0A= +=0A= + "li $11, 10 \n\t" // Test cmp.ne.s=0A= + r6ck_3s(cmp.ne.s, 0x0, 0x3f800000, 0x3f800000, 0x0)=0A= + r6ck_3s(cmp.ne.s, 0x0, 0x00000000, 0x3f800000, 0xffffffff)=0A= + r6ck_3s(cmp.ne.s, 0x0, 0x80000000, 0x00000000, 0x0)=0A= + r6ck_3s(cmp.ne.s, 0x0, 0x7fc00000, 0x7fc00000, 0x0)=0A= + r6ck_3s(cmp.ne.s, 0x0, 0x7fc00000, 0xffc00000, 0x0)=0A= + r6ck_3s(cmp.ne.s, 0x0, 0x7fa00000, 0x7fa00000, 0x0)=0A= + r6ck_3s(cmp.ne.s, 0x0, 0x7fa00000, 0x7fc00000, 0x0)=0A= + r6ck_3s(cmp.ne.s, 0x0, 0x7f800000, 0x7f800000, 0x0)=0A= + r6ck_3s(cmp.ne.s, 0x0, 0xff800000, 0xff800000, 0x0)=0A= +=0A= + "li $11, 11 \n\t" // Test cmp.ne.d=0A= + r6ck_3d(cmp.ne.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0x0)=0A= + r6ck_3d(cmp.ne.d, 0x0, 0x0000000000000000, 0x3ff0000000000000, 0xfffffff= fffffffff)=0A= + r6ck_3d(cmp.ne.d, 0x0, 0x8000000000000000, 0x0000000000000000, 0x0)=0A= + r6ck_3d(cmp.ne.d, 0x0, 0x7ff8000000000000, 0x7ff8000000000000, 0x0)=0A= + r6ck_3d(cmp.ne.d, 0x0, 0x7ff8000000000000, 0xffc0000000000000, 0x0)=0A= + r6ck_3d(cmp.ne.d, 0x0, 0x7fa0000000000000, 0x7fa0000000000000, 0x0)=0A= + r6ck_3d(cmp.ne.d, 0x0, 0x7fa0000000000000, 0x7ff8000000000000, 0x0)=0A= + r6ck_3d(cmp.ne.d, 0x0, 0x7ff0000000000000, 0x7ff0000000000000, 0x0)=0A= + r6ck_3d(cmp.ne.d, 0x0, 0xfff0000000000000, 0xfff0000000000000, 0x0)=0A= + r6ck_3d(cmp.ne.d, 0x0, 0xab19546120965720, 0x92452014f194abc3, 0xfffffff= fffffffff)=0A= +=0A= + "li $11, 12 \n\t" // Test cmp.lt.s=0A= + r6ck_3s(cmp.lt.s, 0x0, 0x3f800000, 0x3f800000, 0x0)=0A= + r6ck_3s(cmp.lt.s, 0x0, 0x00000000, 0x3f800000, 0xffffffff)=0A= + r6ck_3s(cmp.lt.s, 0x0, 0xbf800000, 0x3f800000, 0xffffffff)=0A= + r6ck_3s(cmp.lt.s, 0x0, 0x3f800000, 0xbf800000, 0x0)=0A= + r6ck_3s(cmp.lt.s, 0x0, 0xff800000, 0xbf800000, 0xffffffff)=0A= + r6ck_3s(cmp.lt.s, 0x0, 0xbf800000, 0x7f800000, 0xffffffff)=0A= + r6ck_3s(cmp.lt.s, 0x0, 0xbf800000, 0xff800000, 0x0)=0A= + r6ck_3s(cmp.lt.s, 0x0, 0x7f800000, 0xbf800000, 0x0)=0A= +=0A= + "li $11, 13 \n\t" // Test cmp.lt.d=0A= + r6ck_3d(cmp.lt.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0x0)=0A= + r6ck_3d(cmp.lt.d, 0x0, 0x0000000000000000, 0x3ff0000000000000, 0xfffffff= fffffffff)=0A= + r6ck_3d(cmp.lt.d, 0x0, 0xbff0000000000000, 0x3ff0000000000000, 0xfffffff= fffffffff)=0A= + r6ck_3d(cmp.lt.d, 0x0, 0x3ff0000000000000, 0xbff0000000000000, 0x0)=0A= + r6ck_3d(cmp.lt.d, 0x0, 0xfff0000000000000, 0xbff0000000000000, 0xfffffff= fffffffff)=0A= + r6ck_3d(cmp.lt.d, 0x0, 0xbff0000000000000, 0x7ff0000000000000, 0xfffffff= fffffffff)=0A= + r6ck_3d(cmp.lt.d, 0x0, 0xbff0000000000000, 0xfff0000000000000, 0x0)=0A= + r6ck_3d(cmp.lt.d, 0x0, 0x7ff0000000000000, 0xbff0000000000000, 0x0)=0A= +=0A= + "li $11, 14 \n\t" // Test cmp.le.s=0A= + r6ck_3s(cmp.le.s, 0x0, 0x3f800000, 0x3f800000, 0xffffffff)=0A= + r6ck_3s(cmp.le.s, 0x0, 0x00000000, 0x3f800000, 0xffffffff)=0A= + r6ck_3s(cmp.le.s, 0x0, 0xbf800000, 0x3f800000, 0xffffffff)=0A= + r6ck_3s(cmp.le.s, 0x0, 0x3f800000, 0xbf800000, 0x0)=0A= + r6ck_3s(cmp.le.s, 0x0, 0xff800000, 0xbf800000, 0xffffffff)=0A= + r6ck_3s(cmp.le.s, 0x0, 0xbf800000, 0x7f800000, 0xffffffff)=0A= + r6ck_3s(cmp.le.s, 0x0, 0xbf800000, 0xff800000, 0x0)=0A= + r6ck_3s(cmp.le.s, 0x0, 0x7f800000, 0xbf800000, 0x0)=0A= +=0A= + "li $11, 15 \n\t" // Test cmp.le.d=0A= + r6ck_3d(cmp.le.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0xfffffff= fffffffff)=0A= + r6ck_3d(cmp.le.d, 0x0, 0x0000000000000000, 0x3ff0000000000000, 0xfffffff= fffffffff)=0A= + r6ck_3d(cmp.le.d, 0x0, 0xbff0000000000000, 0x3ff0000000000000, 0xfffffff= fffffffff)=0A= + r6ck_3d(cmp.le.d, 0x0, 0x3ff0000000000000, 0xbff0000000000000, 0x0)=0A= + r6ck_3d(cmp.le.d, 0x0, 0xfff0000000000000, 0xbff0000000000000, 0xfffffff= fffffffff)=0A= + r6ck_3d(cmp.le.d, 0x0, 0xbff0000000000000, 0x7ff0000000000000, 0xfffffff= fffffffff)=0A= + r6ck_3d(cmp.le.d, 0x0, 0xbff0000000000000, 0xfff0000000000000, 0x0)=0A= + r6ck_3d(cmp.le.d, 0x0, 0x7ff0000000000000, 0xbff0000000000000, 0x0)=0A= +=0A= + "li $11, 16 \n\t" // Test cmp.un.s=0A= + r6ck_3s(cmp.un.s, 0x0, 0x3f800000, 0x3f800000, 0x0)=0A= + r6ck_3s(cmp.un.s, 0x0, 0x3f800000, 0xbf800000, 0x0)=0A= + r6ck_3s(cmp.un.s, 0x0, 0x3f800000, 0x7fc00000, 0xffffffff)=0A= + r6ck_3s(cmp.un.s, 0x0, 0x7fc01234, 0x7fc00000, 0xffffffff)=0A= + r6ck_3s(cmp.un.s, 0x0, 0x7fc00000, 0x7fc00000, 0xffffffff)=0A= + r6ck_3s(cmp.un.s, 0x0, 0x3f800000, 0xff800000, 0x0)=0A= + r6ck_3s(cmp.un.s, 0x0, 0x3f800000, 0x7f800000, 0x0)=0A= +=0A= + "li $11, 17 \n\t" // Test cmp.un.d=0A= + r6ck_3d(cmp.un.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0x0)=0A= + r6ck_3d(cmp.un.d, 0x0, 0x3ff0000000000000, 0xbff0000000000000, 0x0)=0A= + r6ck_3d(cmp.un.d, 0x0, 0x3ff0000000000000, 0x7ff8000000000000, 0xfffffff= fffffffff)=0A= + r6ck_3d(cmp.un.d, 0x0, 0x7fc0123400000000, 0x7ff8000000000000, 0xfffffff= fffffffff)=0A= + r6ck_3d(cmp.un.d, 0x0, 0x7ff8000000000000, 0x7ff8000000000000, 0xfffffff= fffffffff)=0A= + r6ck_3d(cmp.un.d, 0x0, 0x3ff0000000000000, 0xfff0000000000000, 0x0)=0A= + r6ck_3d(cmp.un.d, 0x0, 0x3ff0000000000000, 0x7ff0000000000000, 0x0)=0A= +=0A= + "li $11, 18 \n\t" // Test cmp.or.s=0A= + r6ck_3s(cmp.or.s, 0x0, 0x3f800000, 0x3f800000, 0xffffffff)=0A= + r6ck_3s(cmp.or.s, 0x0, 0xbf800000, 0x3f800000, 0xffffffff)=0A= + r6ck_3s(cmp.or.s, 0x0, 0x3f800000, 0x7fc00000, 0x0)=0A= + r6ck_3s(cmp.or.s, 0x0, 0x7fc00000, 0x3f800000, 0x0)=0A= + r6ck_3s(cmp.or.s, 0x0, 0xffc00000, 0x3f800000, 0x0)=0A= + r6ck_3s(cmp.or.s, 0x0, 0x7fc01234, 0x7fc00000, 0x0)=0A= + r6ck_3s(cmp.or.s, 0x0, 0xff800000, 0x00000000, 0xffffffff)=0A= + r6ck_3s(cmp.or.s, 0x0, 0x00000000, 0x7f800000, 0xffffffff)=0A= + r6ck_3s(cmp.or.s, 0x0, 0x00000000, 0xff800000, 0xffffffff)=0A= + r6ck_3s(cmp.or.s, 0x0, 0x7f800000, 0x00000000, 0xffffffff)=0A= + r6ck_3s(cmp.or.s, 0x0, 0x7f800000, 0x00000000, 0xffffffff)=0A= +=0A= + "li $11, 19 \n\t" // Test cmp.or.d=0A= + r6ck_3d(cmp.or.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0xfffffff= fffffffff)=0A= + r6ck_3d(cmp.or.d, 0x0, 0xbff0000000000000, 0x3ff0000000000000, 0xfffffff= fffffffff)=0A= + r6ck_3d(cmp.or.d, 0x0, 0x3ff0000000000000, 0x7ff8000000000000, 0x0)=0A= + r6ck_3d(cmp.or.d, 0x0, 0x7ff8000000000000, 0x3ff0000000000000, 0x0)=0A= + r6ck_3d(cmp.or.d, 0x0, 0xfff8000000000000, 0x3ff0000000000000, 0x0)=0A= + r6ck_3d(cmp.or.d, 0x0, 0x7ff8123492134352, 0x7ff8000000000000, 0x0)=0A= + r6ck_3d(cmp.or.d, 0x0, 0xfff0000000000000, 0x0000000000000000, 0xfffffff= fffffffff)=0A= + r6ck_3d(cmp.or.d, 0x0, 0x0000000000000000, 0x7ff0000000000000, 0xfffffff= fffffffff)=0A= + r6ck_3d(cmp.or.d, 0x0, 0x0000000000000000, 0xfff0000000000000, 0xfffffff= fffffffff)=0A= + r6ck_3d(cmp.or.d, 0x0, 0x7ff0000000000000, 0x0000000000000000, 0xfffffff= fffffffff)=0A= + r6ck_3d(cmp.or.d, 0x0, 0x7ff0000000000000, 0x0000000000000000, 0xfffffff= fffffffff)=0A= +=0A= + "li $11, 20 \n\t" // Test cmp.ueq.s=0A= + r6ck_3s(cmp.ueq.s, 0x0, 0x3f800000, 0x00000000, 0x0)=0A= + r6ck_3s(cmp.ueq.s, 0x0, 0x3f800000, 0x7fc00000, 0xffffffff)=0A= + r6ck_3s(cmp.ueq.s, 0x0, 0x7fc00000, 0x7fc00000, 0xffffffff)=0A= + r6ck_3s(cmp.ueq.s, 0x0, 0x3f800000, 0x3f800000, 0xffffffff)=0A= + r6ck_3s(cmp.ueq.s, 0x0, 0x00000000, 0x3f800000, 0x0)=0A= + r6ck_3s(cmp.ueq.s, 0x0, 0x80000000, 0x00000000, 0xffffffff)=0A= + r6ck_3s(cmp.ueq.s, 0x0, 0x7f800000, 0x7fc00000, 0xffffffff)=0A= + r6ck_3s(cmp.ueq.s, 0x0, 0xff800000, 0xff800000, 0xffffffff)=0A= +=0A= + "li $11, 21 \n\t" // Test cmp.ueq.d=0A= + r6ck_3d(cmp.ueq.d, 0x0, 0x3ff0000000000000, 0x0000000000000000, 0x0)=0A= + r6ck_3d(cmp.ueq.d, 0x0, 0x3ff0000000000000, 0x7ff8000000000000, 0xffffff= ffffffffff)=0A= + r6ck_3d(cmp.ueq.d, 0x0, 0x7ff8000000000000, 0x7ff8000000000000, 0xffffff= ffffffffff)=0A= + r6ck_3d(cmp.ueq.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0xffffff= ffffffffff)=0A= + r6ck_3d(cmp.ueq.d, 0x0, 0x0000000000000000, 0x3ff0000000000000, 0x0)=0A= + r6ck_3d(cmp.ueq.d, 0x0, 0x8000000000000000, 0x0000000000000000, 0xffffff= ffffffffff)=0A= + r6ck_3d(cmp.ueq.d, 0x0, 0x7ff0000000000000, 0x7ff8000000000000, 0xffffff= ffffffffff)=0A= + r6ck_3d(cmp.ueq.d, 0x0, 0xfff0000000000000, 0xfff0000000000000, 0xffffff= ffffffffff)=0A= +=0A= + "li $11, 22 \n\t" // Test cmp.une.s=0A= + r6ck_3s(cmp.une.s, 0x0, 0x3f800000, 0x3f800000, 0x0)=0A= + r6ck_3s(cmp.une.s, 0x0, 0x3f800000, 0x7fc00000, 0xffffffff)=0A= + r6ck_3s(cmp.une.s, 0x0, 0x7fc00000, 0x7fc00000, 0xffffffff)=0A= + r6ck_3s(cmp.une.s, 0x0, 0x3f800000, 0x3f800000, 0x0)=0A= + r6ck_3s(cmp.une.s, 0x0, 0x00000000, 0x3f800000, 0xffffffff)=0A= + r6ck_3s(cmp.une.s, 0x0, 0x80000000, 0x00000000, 0x0)=0A= + r6ck_3s(cmp.une.s, 0x0, 0x7f800000, 0x7fc00000, 0xffffffff)=0A= + r6ck_3s(cmp.une.s, 0x0, 0xff800000, 0xff800000, 0x0)=0A= +=0A= + "li $11, 23 \n\t" // Test cmp.une.d=0A= + r6ck_3d(cmp.une.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0x0)=0A= + r6ck_3d(cmp.une.d, 0x0, 0x3ff0000000000000, 0x7ff8000000000000, 0xffffff= ffffffffff)=0A= + r6ck_3d(cmp.une.d, 0x0, 0x7ff8000000000000, 0x7ff8000000000000, 0xffffff= ffffffffff)=0A= + r6ck_3d(cmp.une.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0x0)=0A= + r6ck_3d(cmp.une.d, 0x0, 0x0000000000000000, 0x3ff0000000000000, 0xffffff= ffffffffff)=0A= + r6ck_3d(cmp.une.d, 0x0, 0x8000000000000000, 0x0000000000000000, 0x0)=0A= + r6ck_3d(cmp.une.d, 0x0, 0x7ff0000000000000, 0x7ff8000000000000, 0xffffff= ffffffffff)=0A= + r6ck_3d(cmp.une.d, 0x0, 0xfff0000000000000, 0xfff0000000000000, 0x0)=0A= +=0A= + "li $11, 24 \n\t" // Test cmp.ult.s=0A= + r6ck_3s(cmp.ult.s, 0x0, 0x3f800000, 0x3f800000, 0x0)=0A= + r6ck_3s(cmp.ult.s, 0x0, 0x3f800000, 0x7fc00000, 0xffffffff)=0A= + r6ck_3s(cmp.ult.s, 0x0, 0x7fc00000, 0x7fc00000, 0xffffffff)=0A= + r6ck_3s(cmp.ult.s, 0x0, 0x00000000, 0x3f800000, 0xffffffff)=0A= + r6ck_3s(cmp.ult.s, 0x0, 0xbf800000, 0x3f800000, 0xffffffff)=0A= + r6ck_3s(cmp.ult.s, 0x0, 0x3f800000, 0xbf800000, 0x0)=0A= +=0A= + "li $11, 25 \n\t" // Test cmp.ult.d=0A= + r6ck_3d(cmp.ult.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0x0)=0A= + r6ck_3d(cmp.ult.d, 0x0, 0x3ff0000000000000, 0x7ff8000000000000, 0xffffff= ffffffffff)=0A= + r6ck_3d(cmp.ult.d, 0x0, 0x7ff8000000000000, 0x7ff8000000000000, 0xffffff= ffffffffff)=0A= + r6ck_3d(cmp.ult.d, 0x0, 0x0000000000000000, 0x3ff0000000000000, 0xffffff= ffffffffff)=0A= + r6ck_3d(cmp.ult.d, 0x0, 0xbff0000000000000, 0x3ff0000000000000, 0xffffff= ffffffffff)=0A= + r6ck_3d(cmp.ult.d, 0x0, 0x3ff0000000000000, 0xbff0000000000000, 0x0)=0A= +=0A= + "li $11, 26 \n\t" // Test cmp.ule.s=0A= + r6ck_3s(cmp.ule.s, 0x0, 0x3f800000, 0x7fc00000, 0xffffffff)=0A= + r6ck_3s(cmp.ule.s, 0x0, 0x7fc00000, 0x7fc00000, 0xffffffff)=0A= + r6ck_3s(cmp.ule.s, 0x0, 0x3f800000, 0x3f800000, 0xffffffff)=0A= + r6ck_3s(cmp.ule.s, 0x0, 0x00000000, 0x3f800000, 0xffffffff)=0A= + r6ck_3s(cmp.ule.s, 0x0, 0xbf800000, 0x3f800000, 0xffffffff)=0A= + r6ck_3s(cmp.ule.s, 0x0, 0x3f800000, 0xbf800000, 0x0)=0A= + r6ck_3s(cmp.ule.s, 0x0, 0x3f800000, 0xff800000, 0x0)=0A= +=0A= + "li $11, 27 \n\t" // Test cmp.ule.d=0A= + r6ck_3d(cmp.ule.d, 0x0, 0x3ff0000000000000, 0x7ff8000000000000, 0xffffff= ffffffffff)=0A= + r6ck_3d(cmp.ule.d, 0x0, 0x7ff8000000000000, 0x7ff8000000000000, 0xffffff= ffffffffff)=0A= + r6ck_3d(cmp.ule.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0xffffff= ffffffffff)=0A= + r6ck_3d(cmp.ule.d, 0x0, 0x0000000000000000, 0x3ff0000000000000, 0xffffff= ffffffffff)=0A= + r6ck_3d(cmp.ule.d, 0x0, 0xbff0000000000000, 0x3ff0000000000000, 0xffffff= ffffffffff)=0A= + r6ck_3d(cmp.ule.d, 0x0, 0x3ff0000000000000, 0xbff0000000000000, 0x0)=0A= + r6ck_3d(cmp.ule.d, 0x0, 0x3ff0000000000000, 0xfff0000000000000, 0x0)=0A= +=0A= + "li $11, 281 \n\t" // Test rint.s=0A= + r6ck_2s(rint.s, 0x0, 0x3fbf10cb, 0x3f800000)=0A= + "li $11, 282 \n\t" // Test rint.s=0A= + r6ck_2s(rint.s, 0x0, 0xb9011423, 0x0)=0A= + "li $11, 283 \n\t" // Test rint.s=0A= + r6ck_2s(rint.s, 0x0, 0x43fa4687, 0x43fa8000)=0A= + "li $11, 284 \n\t" // Test rint.s=0A= + r6ck_2s(rint.s, 0x0, 0x41380000, 0x41400000)=0A= + "li $11, 285 \n\t" // Test rint.s=0A= + r6ck_2s(rint.s, 0x0, 0x3ff33333, 0x40000000)=0A= +=0A= + "li $11, 291 \n\t" // Test rint.d=0A= + r6ck_2d(rint.d, 0x0, 0x3ff1f9a6b50b0f28, 0x3ff0000000000000)=0A= + "li $11, 292 \n\t" // Test rint.d=0A= + r6ck_2d(rint.d, 0x0, 0xbf543bf727136a40, 0x0)=0A= + "li $11, 293 \n\t" // Test rint.d=0A= + r6ck_2d(rint.d, 0x0, 0x407f48d0e5604189, 0x407f500000000000)=0A= + "li $11, 294 \n\t" // Test rint.d=0A= + r6ck_2d(rint.d, 0x0, 0x5b7c2d43b93b0a8c, 0x5b7c2d43b93b0a8c)=0A= +=0A= + "li $11, 30 \n\t" // Test class.s=0A= + r6ck_2s(class.s, 0x0, 0x7f800010, 0x1)=0A= + r6ck_2s(class.s, 0x0, 0x7fc00000, 0x2)=0A= + r6ck_2s(class.s, 0x0, 0xff800000, 0x4)=0A= + r6ck_2s(class.s, 0x0, 0xbf800000, 0x8)=0A= + r6ck_2s(class.s, 0x0, 0x80000001, 0x10)=0A= + r6ck_2s(class.s, 0x0, 0x80000000, 0x20)=0A= + r6ck_2s(class.s, 0x0, 0x7f800000, 0x40)=0A= + r6ck_2s(class.s, 0x0, 0x3f800000, 0x80)=0A= + r6ck_2s(class.s, 0x0, 0x00000001, 0x100)=0A= + r6ck_2s(class.s, 0x0, 0x00000000, 0x200)=0A= +=0A= + "li $11, 31 \n\t" // Test class.d=0A= + r6ck_2d(class.d, 0x0, 0x7ff0000000000010, 0x1)=0A= + r6ck_2d(class.d, 0x0, 0x7ff8000000000000, 0x2)=0A= + r6ck_2d(class.d, 0x0, 0xfff0000000000000, 0x4)=0A= + r6ck_2d(class.d, 0x0, 0xbff0000000000000, 0x8)=0A= + r6ck_2d(class.d, 0x0, 0x8000000000000001, 0x10)=0A= + r6ck_2d(class.d, 0x0, 0x8000000000000000, 0x20)=0A= + r6ck_2d(class.d, 0x0, 0x7ff0000000000000, 0x40)=0A= + r6ck_2d(class.d, 0x0, 0x3ff0000000000000, 0x80)=0A= + r6ck_2d(class.d, 0x0, 0x0000000000000001, 0x100)=0A= + r6ck_2d(class.d, 0x0, 0x0000000000000000, 0x200)=0A= +=0A= + "li $11, 32 \n\t" // Test min.s=0A= + r6ck_3s(min.s, 0x0, 0x3f800000, 0x0, 0x0)=0A= + r6ck_3s(min.s, 0x0, 0x0, 0x3f800000, 0x0)=0A= + r6ck_3s(min.s, 0x0, 0x7f800000, 0x3f800000, 0x3f800000)=0A= + r6ck_3s(min.s, 0x0, 0x3f800000, 0x7f800000, 0x3f800000)=0A= + r6ck_3s(min.s, 0x0, 0xff800000, 0xbf800000, 0xff800000)=0A= + r6ck_3s(min.s, 0x0, 0xbf800000, 0xff800000, 0xff800000)=0A= + r6ck_3s(min.s, 0x0, 0x7fffffff, 0x3f800000, 0x3f800000)=0A= + r6ck_3s(min.s, 0x0, 0x3f800000, 0x7fffffff, 0x3f800000)=0A= +=0A= + "li $11, 33 \n\t" // Test min.d=0A= + r6ck_3d(min.d, 0x0, 0x3ff0000000000000, 0x0, 0x0)=0A= + r6ck_3d(min.d, 0x0, 0x0, 0x3ff0000000000000, 0x0)=0A= + r6ck_3d(min.d, 0x0, 0x7ff0000000000000, 0x3ff0000000000000, 0x3ff0000000= 000000)=0A= + r6ck_3d(min.d, 0x0, 0x3ff0000000000000, 0x7ff0000000000000, 0x3ff0000000= 000000)=0A= + r6ck_3d(min.d, 0x0, 0xfff0000000000000, 0xbff0000000000000, 0xfff0000000= 000000)=0A= + r6ck_3d(min.d, 0x0, 0xbff0000000000000, 0xfff0000000000000, 0xfff0000000= 000000)=0A= + r6ck_3d(min.d, 0x0, 0x7fffffffffffffff, 0x3ff0000000000000, 0x3ff0000000= 000000)=0A= + r6ck_3d(min.d, 0x0, 0x3ff0000000000000, 0x7fffffffffffffff, 0x3ff0000000= 000000)=0A= +=0A= + "li $11, 34 \n\t" // Test max.s=0A= + r6ck_3s(max.s, 0x0, 0x3f800000, 0x0, 0x3f800000)=0A= + r6ck_3s(max.s, 0x0, 0x0, 0x3f800000, 0x3f800000)=0A= + r6ck_3s(max.s, 0x0, 0x7f800000, 0x3f800000, 0x7f800000)=0A= + r6ck_3s(max.s, 0x0, 0x3f800000, 0x7f800000, 0x7f800000)=0A= + r6ck_3s(max.s, 0x0, 0xff800000, 0xbf800000, 0xbf800000)=0A= + r6ck_3s(max.s, 0x0, 0xbf800000, 0xff800000, 0xbf800000)=0A= + r6ck_3s(max.s, 0x0, 0x7fffffff, 0x3f800000, 0x3f800000)=0A= + r6ck_3s(max.s, 0x0, 0x3f800000, 0x7fffffff, 0x3f800000)=0A= +=0A= + "li $11, 35 \n\t" // Test max.d=0A= + r6ck_3d(max.d, 0x0, 0x3ff0000000000000, 0x0, 0x3ff0000000000000)=0A= + r6ck_3d(max.d, 0x0, 0x0, 0x3ff0000000000000, 0x3ff0000000000000)=0A= + r6ck_3d(max.d, 0x0, 0x7ff0000000000000, 0x3ff0000000000000, 0x7ff0000000= 000000)=0A= + r6ck_3d(max.d, 0x0, 0x3ff0000000000000, 0x7ff0000000000000, 0x7ff0000000= 000000)=0A= + r6ck_3d(max.d, 0x0, 0xfff0000000000000, 0xbff0000000000000, 0xbff0000000= 000000)=0A= + r6ck_3d(max.d, 0x0, 0xbff0000000000000, 0xfff0000000000000, 0xbff0000000= 000000)=0A= + r6ck_3d(max.d, 0x0, 0x7fffffffffffffff, 0x3ff0000000000000, 0x3ff0000000= 000000)=0A= + r6ck_3d(max.d, 0x0, 0x3ff0000000000000, 0x7fffffffffffffff, 0x3ff0000000= 000000)=0A= +=0A= + "li $11, 36 \n\t" // Test mina.s=0A= + r6ck_3s(mina.s, 0x0, 0x3f800000, 0x0, 0x0)=0A= + r6ck_3s(mina.s, 0x0, 0x0, 0x3f800000, 0x0)=0A= + r6ck_3s(mina.s, 0x0, 0x7f800000, 0x3f800000, 0x3f800000)=0A= + r6ck_3s(mina.s, 0x0, 0x3f800000, 0x7f800000, 0x3f800000)=0A= + r6ck_3s(mina.s, 0x0, 0xff800000, 0xbf800000, 0xbf800000)=0A= + r6ck_3s(mina.s, 0x0, 0xbf800000, 0xff800000, 0xbf800000)=0A= + r6ck_3s(mina.s, 0x0, 0x7fffffff, 0x3f800000, 0x3f800000)=0A= + r6ck_3s(mina.s, 0x0, 0x3f800000, 0x7fffffff, 0x3f800000)=0A= + r6ck_3s(mina.s, 0x0, 0xc0000000, 0x3f800000, 0x3f800000)=0A= + r6ck_3s(mina.s, 0x0, 0x3f800000, 0xc0000000, 0x3f800000)=0A= +=0A= + "li $11, 37 \n\t" // Test mina.d=0A= + r6ck_3d(mina.d, 0x0, 0x3ff0000000000000, 0x0, 0x0)=0A= + r6ck_3d(mina.d, 0x0, 0x0, 0x3ff0000000000000, 0x0)=0A= + r6ck_3d(mina.d, 0x0, 0x7ff0000000000000, 0x3ff0000000000000, 0x3ff000000= 0000000)=0A= + r6ck_3d(mina.d, 0x0, 0x3ff0000000000000, 0x7ff0000000000000, 0x3ff000000= 0000000)=0A= + r6ck_3d(mina.d, 0x0, 0xfff0000000000000, 0xbff0000000000000, 0xbff000000= 0000000)=0A= + r6ck_3d(mina.d, 0x0, 0xbff0000000000000, 0xfff0000000000000, 0xbff000000= 0000000)=0A= + r6ck_3d(mina.d, 0x0, 0x7fffffffffffffff, 0x3ff0000000000000, 0x3ff000000= 0000000)=0A= + r6ck_3d(mina.d, 0x0, 0x3ff0000000000000, 0x7fffffffffffffff, 0x3ff000000= 0000000)=0A= + r6ck_3d(mina.d, 0x0, 0xc000000000000000, 0x3ff0000000000000, 0x3ff000000= 0000000)=0A= + r6ck_3d(mina.d, 0x0, 0x3ff0000000000000, 0xc000000000000000, 0x3ff000000= 0000000)=0A= +=0A= + "li $11, 38 \n\t" // Test maxa.s=0A= + r6ck_3s(maxa.s, 0x0, 0x3f800000, 0x0, 0x3f800000)=0A= + r6ck_3s(maxa.s, 0x0, 0x0, 0x3f800000, 0x3f800000)=0A= + r6ck_3s(maxa.s, 0x0, 0x7f800000, 0x3f800000, 0x7f800000)=0A= + r6ck_3s(maxa.s, 0x0, 0x3f800000, 0x7f800000, 0x7f800000)=0A= + r6ck_3s(maxa.s, 0x0, 0xff800000, 0xbf800000, 0xff800000)=0A= + r6ck_3s(maxa.s, 0x0, 0xbf800000, 0xff800000, 0xff800000)=0A= + r6ck_3s(maxa.s, 0x0, 0x7fffffff, 0x3f800000, 0x3f800000)=0A= + r6ck_3s(maxa.s, 0x0, 0x3f800000, 0x7fffffff, 0x3f800000)=0A= + r6ck_3s(maxa.s, 0x0, 0xc0000000, 0x3f800000, 0xc0000000)=0A= + r6ck_3s(maxa.s, 0x0, 0x3f800000, 0xc0000000, 0xc0000000)=0A= +=0A= + "li $11, 39 \n\t" // Test maxa.d=0A= + r6ck_3d(maxa.d, 0x0, 0x3ff0000000000000, 0x0, 0x3ff0000000000000)=0A= + r6ck_3d(maxa.d, 0x0, 0x0, 0x3ff0000000000000, 0x3ff0000000000000)=0A= + r6ck_3d(maxa.d, 0x0, 0x7ff0000000000000, 0x3ff0000000000000, 0x7ff000000= 0000000)=0A= + r6ck_3d(maxa.d, 0x0, 0x3ff0000000000000, 0x7ff0000000000000, 0x7ff000000= 0000000)=0A= + r6ck_3d(maxa.d, 0x0, 0xfff0000000000000, 0xbff0000000000000, 0xfff000000= 0000000)=0A= + r6ck_3d(maxa.d, 0x0, 0xbff0000000000000, 0xfff0000000000000, 0xfff000000= 0000000)=0A= + r6ck_3d(maxa.d, 0x0, 0x7fffffffffffffff, 0x3ff0000000000000, 0x3ff000000= 0000000)=0A= + r6ck_3d(maxa.d, 0x0, 0x3ff0000000000000, 0x7fffffffffffffff, 0x3ff000000= 0000000)=0A= + r6ck_3d(maxa.d, 0x0, 0xc000000000000000, 0x3ff0000000000000, 0xc00000000= 0000000)=0A= + r6ck_3d(maxa.d, 0x0, 0x3ff0000000000000, 0xc000000000000000, 0xc00000000= 0000000)=0A= +=0A= + "li $11, 40 \n\t" // Test sel.s=0A= + r6ck_3s(sel.s, 0x0, 0xabcdef12, 0x12345678, 0xabcdef12)=0A= + r6ck_3s(sel.s, 0x1, 0xdeadbeef, 0xcafe1234, 0xcafe1234)=0A= + r6ck_3s(sel.s, 0xfffffffe, 0xbadcafe0, 0x12345678, 0xbadcafe0)=0A= + r6ck_3s(sel.s, 0xffffffff, 0xdeadbeef, 0xcadf00ab, 0xcadf00ab)=0A= +=0A= + "li $11, 41 \n\t" // Test sel.d=0A= + r6ck_3d(sel.d, 0x0, 0xabcdef123456789, 0x12345678abcdefa, 0xabcdef123456= 789)=0A= + r6ck_3d(sel.d, 0x1, 0xdeadbeef1534567, 0xcafe12340145279, 0xcafe12340145= 279)=0A= + r6ck_3d(sel.d, 0xfffffffffffffffe, 0xbadcafe00efacdab, 0x123456788765432= 1, 0xbadcafe00efacdab)=0A= + r6ck_3d(sel.d, 0xffffffffffffffff, 0xdeadbeeffeebdaed, 0xcadf00abba00fda= c, 0xcadf00abba00fdac)=0A= +=0A= + "li $11, 42 \n\t" // Test seleqz.s=0A= + r6ck_3s(seleqz.s, 0x0, 0x1234abcd, 0x0, 0x1234abcd)=0A= + r6ck_3s(seleqz.s, 0x0, 0xabcdef01, 0x1, 0x0)=0A= + r6ck_3s(seleqz.s, 0x0, 0xffeebbcc, 0xfffffffe, 0xffeebbcc)=0A= + r6ck_3s(seleqz.s, 0x0, 0x12345678, 0xffffffff, 0)=0A= +=0A= + "li $11, 43 \n\t" // Test seleqz.d=0A= + r6ck_3d(seleqz.d, 0x0, 0x1234abcddcba4321, 0x0, 0x1234abcddcba4321)=0A= + r6ck_3d(seleqz.d, 0x0, 0xabcdef0110fedcba, 0x1, 0x0)=0A= + r6ck_3d(seleqz.d, 0x0, 0xffeebbccccbbeeff, 0xfffffffffffffffe, 0xffeebbc= cccbbeeff)=0A= + r6ck_3d(seleqz.d, 0x0, 0x1234567887654321, 0xffffffffffffffff, 0x0)=0A= +=0A= + "li $11, 44 \n\t" // Test selnez.s=0A= + r6ck_3s(selnez.s, 0x0, 0x1234abcd, 0x0, 0x0)=0A= + r6ck_3s(selnez.s, 0x0, 0xabcdef01, 0x1, 0xabcdef01)=0A= + r6ck_3s(selnez.s, 0x0, 0xffeebbcc, 0xfffffffe, 0x0)=0A= + r6ck_3s(selnez.s, 0x0, 0x12345678, 0xffffffff, 0x12345678)=0A= +=0A= + "li $11, 45 \n\t" // Test selnez.d=0A= + r6ck_3d(selnez.d, 0x0, 0x1234abcddcba4321, 0x0, 0x0)=0A= + r6ck_3d(selnez.d, 0x0, 0xabcdef0110fedcba, 0x1, 0xabcdef0110fedcba)=0A= + r6ck_3d(selnez.d, 0x0, 0xffeebbccccbbeeff, 0xfffffffffffffffe, 0x0)=0A= + r6ck_3d(selnez.d, 0x0, 0x1234567887654321, 0xffffffffffffffff, 0x1234567= 887654321)=0A= +=0A= + "li $11, 46 \n\t" // Test bc1eqz"=0A= + "li $10, 0x01 \n\t"=0A= + "mtc1 $10, $f2 \n\t"=0A= + "mtc1 $0, $f4 \n\t"=0A= + "bc1eqz $f2, 58f \n\t"=0A= + "nop \n\t"=0A= + "bc1eqz $f4, L62 \n\t"=0A= + "nop \n\t"=0A= + "b 58f \n\t"=0A= + "nop \n\t"=0A= +"L62: \n\t"=0A= + "li $11, 47 \n\t" // Test bc1nez=0A= + "bc1nez $f4, 58f \n\t"=0A= + "nop \n\t"=0A= + "bc1nez $f2, Lend8 \n\t"=0A= + "nop \n\t"=0A= + "b 58f \n\t"=0A= + "nop \n\t"=0A= +"Lend8: \n\t"=0A= + "li $11, 0 \n\t"=0A= + "58: \n\t"=0A= + "move %[err], $11 \n\t"=0A= + ".set pop \n\t"=0A= + : [err] "+r"(err) // outputs=0A= + : // inputs=0A= + : "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10", "$11", "$31", "= $s0", "$f2", "$f4", "$f6" // clobbers=0A= + );=0A= +=0A= + return err;=0A= +}=0A= +=0A= +=0A= +=0A= +=0A= +// R6 specific tests for mips64 (64-bit)=0A= +int test_r6_llsc_dp()=0A= +{=0A= + volatile int err =3D 0;=0A= +=0A= + asm(=0A= + ".set push \n\t"=0A= + ".set noreorder \n\t"=0A= + ".data \n\t"=0A= + ".align 16 \n\t"=0A= + "test_data: \n\t"=0A= + ".word 0xaaaaaaaa \n\t"=0A= + ".word 0xbbbbbbbb \n\t"=0A= + ".word 0xcccccccc \n\t"=0A= + ".word 0xdddddddd \n\t"=0A= + ".align 16 \n\t"=0A= + "end_check: \n\t"=0A= + ".byte 0 \n\t"=0A= + ".byte 0 \n\t"=0A= + ".byte 0 \n\t"=0A= + ".byte 0x1 \n\t"=0A= + ".text \n\t"=0A= + "li $11, 1 \n\t" // Test LL= WP=0A= + "llwp $2, $3, test_data \n\t"=0A= + checkpair_dword($2, $3, test_data, end_check)=0A= + "sll $2, $2, 1 \n\t"=0A= + "srl $3, $3, 1 \n\t"=0A= + "move $s0, $2 \n\t"=0A= + "scwp $2, $3, test_data \n\t"=0A= + check32($2, 1)=0A= + checkpair_dword($s0, $3, test_data, end_check)=0A= + "li $11, 2 \n\t" // Test SC= WP, done=0A= + "li $11, 3 \n\t" // Test LL= DP=0A= + "lldp $2, $3, test_data \n\t"=0A= + checkpair_qword($2, $3, test_data, end_check)=0A= + "dsll $2, $2, 1 \n\t"=0A= + "dsrl $3, $3, 1 \n\t"=0A= + "move $s0, $2 \n\t"=0A= + "scdp $2, $3, test_data \n\t"=0A= + check32($2, 1)=0A= + checkpair_qword($s0, $3, test_data, end_check)=0A= + "li $11, 4 \n\t" // Test SC= DP, done=0A= + "Lend5: \n\t"=0A= + "li $11, 0 \n\t"=0A= + "58: \n\t"=0A= + "move %[err], $11 \n\t"=0A= + ".set pop \n\t"=0A= + : [err] "+r"(err) // outputs=0A= + : // inputs=0A= + : "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10", "$11", "$31",= "$s0" // clobbers=0A= + );=0A= +=0A= + return err;=0A= +}=0A= +=0A= +=0A= +/* R6 specific tests for mips32 (32-bit) */=0A= +int test_r6_llsc_wp()=0A= +{=0A= + volatile int err =3D 0;=0A= +=0A= + asm(=0A= + ".set push \n\t"= =0A= + ".set noreorder \n\t"= =0A= + ".data \n\t"= =0A= + ".align 8 \n\t" = // p2align=0A= + "test_data_2: \n\t"= =0A= + ".word 0xaaaaaaaa \n\t"= =0A= + ".word 0xbbbbbbbb \n\t"= =0A= + ".align 8 \n\t"= =0A= + "end_check_2: \n\t"= =0A= + ".byte 0 \n\t"= =0A= + ".byte 0 \n\t"= =0A= + ".byte 0 \n\t"= =0A= + ".byte 0x1 \n\t"= =0A= + ".text \n\t"= =0A= + "li $11, 1 \n\t" = // Test LLWP=0A= + "llwp $2, $3, test_data_2 \n\t"= =0A= + checkpair_dword($2, $3, test_data_2, end_check_2)=0A= + "sll $2, $2, 1 \n\t"= =0A= + "srl $3, $3, 1 \n\t"= =0A= + "move $s0, $2 \n\t"= =0A= + "scwp $2, $3, test_data_2 \n\t"= =0A= + check32($2, 1)=0A= + checkpair_dword($s0, $3, test_data_2, end_check_2)=0A= + "li $11, 2 \n\t" = // Test SCWP, done=0A= + "Lend6: \n\t"= =0A= + "li $11, 0 \n\t"= =0A= + "58: \n\t"= =0A= + "move %[err], $11 \n\t"= =0A= + ".set pop \n\t"= =0A= + : [err] "+r"(err) // outputs=0A= + : // inputs=0A= + : "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10", "$11", "$31",= "$s0" // clobbers=0A= + );=0A= +=0A= + return err;=0A= +}=0A= +=0A= +=0A= +=0A= +/*=0A= + * Any test_r6_* function returns non-zero =3D> failure=0A= + */=0A= +#define EXPECT(X) if ((X)) abort ();=0A= +=0A= +=0A= +main ()=0A= +{=0A= + EXPECT(test_r6_branch());=0A= +=0A= + EXPECT(test_r6_forbidden());=0A= +=0A= + EXPECT(test_r6_64());=0A= +=0A= + EXPECT(test_r6());=0A= +=0A= + EXPECT(test_r6_fpu());=0A= +=0A= +=0A= + EXPECT(test_r6_llsc_dp());=0A= +=0A= +=0A= + EXPECT(test_r6_llsc_wp());=0A= +}=0A= diff --git a/gdb/testsuite/gdb.arch/mips-64-r6.exp b/gdb/testsuite/gdb.arch= /mips-64-r6.exp=0A= new file mode 100644=0A= index 00000000000..1ab04daddd5=0A= --- /dev/null=0A= +++ b/gdb/testsuite/gdb.arch/mips-64-r6.exp=0A= @@ -0,0 +1,99 @@=0A= +# Copyright (C) 2012-2023 Free Software Foundation, Inc.=0A= +=0A= +# This program is free software; you can redistribute it and/or modify=0A= +# it under the terms of the GNU General Public License as published by=0A= +# the Free Software Foundation; either version 3 of the License, or=0A= +# (at your option) any later version.=0A= +#=0A= +# This program is distributed in the hope that it will be useful,=0A= +# but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= +# GNU General Public License for more details.=0A= +#=0A= +# You should have received a copy of the GNU General Public License=0A= +# along with this program; if not, see .=0A= +=0A= +# Test mips release 6 patch.=0A= +=0A= +require {istarget "*mips*"}=0A= +=0A= +proc single_step {} {=0A= + global gdb_prompt=0A= +=0A= + send_gdb "si\n"=0A= + gdb_expect {=0A= + -re "$gdb_prompt \$" {=0A= + return 1=0A= + }=0A= + -re ".*Breakpoint.*test_.*" {=0A= + return 2=0A= + }=0A= + -re ".*exited normally.*" {=0A= + return 3=0A= + }=0A= + -re ".*The program is not being run.*" {=0A= + return 4=0A= + }=0A= + }=0A= + return 0=0A= +}=0A= +=0A= +set testfile "mips-64-r6"=0A= +set srcfile ${testfile}.c=0A= +set binfile ${objdir}/${subdir}/${testfile}=0A= +=0A= +verbose -log "\[DEBUG\] testfile=3D${testfile}\n"=0A= +verbose -log "\[DEBUG\] srcfile=3D${srcfile}\n"=0A= +verbose -log "\[DEBUG\] binfile=3D${binfile}\n"=0A= +verbose -log "\[DEBUG\] srcdir/subdir/srcfile=3D${srcdir}/${subdir}/${srcf= ile}\n\n"=0A= +=0A= +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executabl= e {debug nowarnings}] !=3D "" } {=0A= + fail "compilation"=0A= + return=0A= +}=0A= +=0A= +pass "compilation"=0A= +=0A= +clean_restart $binfile=0A= +# Native needs run.=0A= +runto_main=0A= +=0A= +set tests ""=0A= +foreach n [list "r6_branch" "r6_forbidden" "r6_64" "r6" "r6_fpu" "r6_llsc_= dp" "r6_llsc_wp"] {=0A= + lappend tests "test_$n"=0A= +}=0A= +=0A= +# put breakpoint on each test-function=0A= +foreach func $tests {=0A= + gdb_test "break $func" "Breakpoint.*at.*" "set breakpoint on $func"=0A= +}=0A= +=0A= +=0A= +set rt [single_step]=0A= +if { $rt =3D=3D 0 } {=0A= + fail "single_step returned $rt"=0A= +}=0A= +=0A= +set start [timestamp]=0A= +global timeout=0A= +while { $rt !=3D 0 && [timestamp] - $start < 3*$timeout } {=0A= +=0A= + if { $rt =3D=3D 3 } {=0A= + pass "all tests are fine"=0A= + return=0A= + } elseif { $rt =3D=3D 4 } {=0A= + fail "Program exited abnormally"=0A= + return=0A= + }=0A= +# elseif { $rt =3D=3D 1 || $rt =3D=3D 2 } { # 1->got gdb_prompt ; 2->hi= t breakpoint=0A= +# verbose -log "\[DEBUG_\] 'single_step' returned rt=3D$rt ; timeout = =3D $timeout"=0A= +# }=0A= +=0A= + set rt [single_step]=0A= +}=0A= +=0A= +if {$rt =3D=3D 0 } {=0A= + fail "stepi"=0A= +}=0A= +=0A= +=0A= -- =0A= 2.34.1=0A= =0A=