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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BY5PR12MB4965.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 071a53c3-bf2b-4d7b-36da-08db2f808759 X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Mar 2023 11:35:27.6020 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: sybjxMrlUq2whI+LRJeKqGJ0oTYYKerBCIMovDEOiSfJgUnxrdEaFop/CZtY9BO0yTIgEU1YM/dHv2UzDSVUag== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5242 X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: [Public] Thanks, John, Aleksandar, for making the changes. LGTM except for a few nit= s (mentioned below). * Nit: In gdbsupport/x86-xstate.h, the following line: 50 #define X86_XSTATE_PKRU (1ULL << 9) could be changed to: 50 #define X86_XSTATE_PKRU (1ULL << X86_XSTATE_PKRU_ID) * Nit: Also X86_XSTATE_PT_ID (line 32) remains unused. So should we keep t= he following line ? +#define X86_XSTATE_PT_ID 8 * In i387-tdep.c (line 954), instead of the following line, /* AMD Ryzen 9 CPUs supporting PKRU. */ You can mention /* AMD CPUs supporting PKRU. */ Or /* AMD Zen3 (and above) CPUs supporting PKRU. */ Thanks Jini. >>-----Original Message----- >>From: Gdb-patches >bounces+jigeorge=3Damd.com@sourceware.org> On Behalf Of John Baldwin >>Sent: Saturday, March 18, 2023 6:39 AM >>To: gdb-patches@sourceware.org >>Cc: Aleksandar Paunovic >>Subject: [PATCH v4 01/13] x86: Add an x86_xsave_layout structure to handl= e >>variable XSAVE layouts. >> >>Caution: This message originated from an External Source. Use proper caut= ion >>when opening attachments, clicking links, or responding. >> >> >>The standard layout of the XSAVE extended state area consists of three re= gions. >>The first 512 bytes (legacy region) match the layout of the FXSAVE instru= ction >>including floating point registers, MMX registers, and SSE registers. Th= e next 64 >>bytes (XSAVE header) contains a header with a fixed layout. The final re= gion >>(extended region) contains zero or more optional state components. Examp= les >>of these include the upper 128 bits of YMM registers for AVX. >> >>These optional state components generally have an architecturally-fixed s= ize, >>but they are not assigned architectural offsets in the extended region. = Instead, >>processors provide additional CPUID leafs describing the size and offset = of each >>component in the "standard" layout for a given CPU. (There is also a "co= mpact" >>format which uses an alternate layout, but existing OS's currently export= the >>"standard" layout when exporting XSAVE data via >>ptrace() and core dumps.) >> >>To date, GDB has assumed the layout used on current Intel processors for = state >>components in the extended region and hardcoded those offsets in the tabl= es in >>i387-tdep.c and i387-fp.cc. However, this fails on recent AMD processors= which >>use a different layout. >>Specifically, AMD Ryzen 9 processors at least do not leave space for the = MPX >>register set in between the AVX and AVX512 register sets. It is not know= n if >>other AMD processors are effected, but seems probable. >> >>To rectify this, add an x86_xsave_layout structure which contains the tot= al size >>of the XSAVE extended state area as well as the offset of each known opti= onal >>state component. This structure is stored in i386_gdbarch_tdep and is fe= tched >>from the current target in i386_gdbarch_init as a >>TARGET_OBJECT_X86_XSAVE_LAYOUT object. >> >>Subsequent commits will modify XSAVE parsing to use x86_xsave_layout. >> >>Co-authored-by: Aleksandar Paunovic >>--- >> gdb/i386-tdep.c | 36 +++++++++++++++++++++++++- >> gdb/i386-tdep.h | 4 +++ >> gdb/target.h | 2 ++ >> gdbsupport/x86-xstate.h | 57 +++++++++++++++++++++++++++++++++++------ >> 4 files changed, 90 insertions(+), 9 deletions(-) >> >>diff --git a/gdb/i386-tdep.c b/gdb/i386-tdep.c index 96c04c1a3d6..5c2d9e4= 2d8d >>100644 >>--- a/gdb/i386-tdep.c >>+++ b/gdb/i386-tdep.c >>@@ -8493,19 +8493,51 @@ i386_type_align (struct gdbarch *gdbarch, struct >>type *type) } >> >> >>+/* Fetch the XSAVE layout for the current target. */ >>+ >>+static struct x86_xsave_layout >>+i386_fetch_xsave_layout () >>+{ >>+ struct x86_xsave_layout layout; >>+ LONGEST len =3D target_read (current_inferior ()->top_target (), >>+ TARGET_OBJECT_X86_XSAVE_LAYOUT, nullptr, >>+ (gdb_byte *) &layout, 0, sizeof (layout)); >>+ if (len !=3D sizeof (layout)) >>+ return {}; >>+ >>+ return layout; >>+} >>+ >> /* Note: This is called for both i386 and amd64. */ >> >> static struct gdbarch * >> i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches= ) { >> const struct target_desc *tdesc; >>+ struct x86_xsave_layout xsave_layout; >> int mm0_regnum; >> int ymm0_regnum; >> int bnd0_regnum; >> int num_bnd_cooked; >> >>+ xsave_layout =3D i386_fetch_xsave_layout (); >>+ >> /* If there is already a candidate, use it. */ >>- arches =3D gdbarch_list_lookup_by_info (arches, &info); >>+ for (arches =3D gdbarch_list_lookup_by_info (arches, &info); >>+ arches !=3D NULL; >>+ arches =3D gdbarch_list_lookup_by_info (arches->next, &info)) >>+ { >>+ /* Check that the XSAVE layout of ARCHES matches the layout for >>+ the current target. */ >>+ i386_gdbarch_tdep *other_tdep >>+ =3D (i386_gdbarch_tdep *) gdbarch_tdep (arches->gdbarch); >>+ >>+ if (other_tdep->xsave_layout !=3D xsave_layout) >>+ continue; >>+ >>+ break; >>+ } >>+ >> if (arches !=3D NULL) >> return arches->gdbarch; >> >>@@ -8762,6 +8794,8 @@ i386_gdbarch_init (struct gdbarch_info info, struct >>gdbarch_list *arches) >> gdbarch_free (gdbarch); >> return NULL; >> } >>+ if (tdep->xcr0 !=3D 0) >>+ tdep->xsave_layout =3D xsave_layout; >> >> num_bnd_cooked =3D (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0); >> >>diff --git a/gdb/i386-tdep.h b/gdb/i386-tdep.h index 371bce72369..e41e0ff= ebed >>100644 >>--- a/gdb/i386-tdep.h >>+++ b/gdb/i386-tdep.h >>@@ -23,6 +23,7 @@ >> #include "gdbarch.h" >> #include "infrun.h" >> #include "expression.h" >>+#include "gdbsupport/x86-xstate.h" >> >> class frame_info_ptr; >> struct gdbarch; >>@@ -145,6 +146,9 @@ struct i386_gdbarch_tdep : gdbarch_tdep_base >> /* Offset of XCR0 in XSAVE extended state. */ >> int xsave_xcr0_offset =3D 0; >> >>+ /* Layout of the XSAVE area extended region. */ x86_xsave_layout >>+ xsave_layout; >>+ >> /* Register names. */ >> const char * const *register_names =3D nullptr; >> >>diff --git a/gdb/target.h b/gdb/target.h index 2dac86c394d..779e111daef >>100644 >>--- a/gdb/target.h >>+++ b/gdb/target.h >>@@ -205,6 +205,8 @@ enum target_object >> TARGET_OBJECT_FREEBSD_VMMAP, >> /* FreeBSD process strings. */ >> TARGET_OBJECT_FREEBSD_PS_STRINGS, >>+ /* x86 XSAVE area layout. */ >>+ TARGET_OBJECT_X86_XSAVE_LAYOUT, >> /* Possible future objects: TARGET_OBJECT_FILE, ... */ }; >> >>diff --git a/gdbsupport/x86-xstate.h b/gdbsupport/x86-xstate.h index >>b8740fd8701..2b517a6dce3 100644 >>--- a/gdbsupport/x86-xstate.h >>+++ b/gdbsupport/x86-xstate.h >>@@ -20,23 +20,64 @@ >> #ifndef COMMON_X86_XSTATE_H >> #define COMMON_X86_XSTATE_H >> >>+/* The extended state feature IDs in the state component bitmap. */ >>+#define X86_XSTATE_X87_ID 0 >>+#define X86_XSTATE_SSE_ID 1 >>+#define X86_XSTATE_AVX_ID 2 >>+#define X86_XSTATE_BNDREGS_ID 3 >>+#define X86_XSTATE_BNDCFG_ID 4 >>+#define X86_XSTATE_K_ID 5 >>+#define X86_XSTATE_ZMM_H_ID 6 >>+#define X86_XSTATE_ZMM_ID 7 >>+#define X86_XSTATE_PT_ID 8 >>+#define X86_XSTATE_PKRU_ID 9 >>+ >> /* The extended state feature bits. */ >>-#define X86_XSTATE_X87 (1ULL << 0) >>-#define X86_XSTATE_SSE (1ULL << 1) >>-#define X86_XSTATE_AVX (1ULL << 2) >>-#define X86_XSTATE_BNDREGS (1ULL << 3) >>-#define X86_XSTATE_BNDCFG (1ULL << 4) >>+#define X86_XSTATE_X87 (1ULL << X86_XSTATE_X87_ID) >>+#define X86_XSTATE_SSE (1ULL << X86_XSTATE_SSE_ID) >>+#define X86_XSTATE_AVX (1ULL << X86_XSTATE_AVX_ID) >>+#define X86_XSTATE_BNDREGS (1ULL << X86_XSTATE_BNDREGS_ID) >>+#define X86_XSTATE_BNDCFG (1ULL << X86_XSTATE_BNDCFG_ID) >> #define X86_XSTATE_MPX (X86_XSTATE_BNDREGS | X86_XSTATE_BNDCFG) >> >> /* AVX 512 adds three feature bits. All three must be enabled. */ >>-#define X86_XSTATE_K (1ULL << 5) >>-#define X86_XSTATE_ZMM_H (1ULL << 6) >>-#define X86_XSTATE_ZMM (1ULL << 7) >>+#define X86_XSTATE_K (1ULL << X86_XSTATE_K_ID) >>+#define X86_XSTATE_ZMM_H (1ULL << X86_XSTATE_ZMM_H_ID) >>+#define X86_XSTATE_ZMM (1ULL << X86_XSTATE_ZMM_ID) >> #define X86_XSTATE_AVX512 (X86_XSTATE_K | X86_XSTATE_ZMM_H \ >> | X86_XSTATE_ZMM) >> >> #define X86_XSTATE_PKRU (1ULL << 9) >> >>+/* Size and offsets of register states in the XSAVE area extended >>+ region. Offsets are set to 0 to indicate the absence of the >>+ associated registers. */ >>+ >>+struct x86_xsave_layout >>+{ >>+ int sizeof_xsave =3D 0; >>+ int avx_offset =3D 0; >>+ int bndregs_offset =3D 0; >>+ int bndcfg_offset =3D 0; >>+ int k_offset =3D 0; >>+ int zmm_h_offset =3D 0; >>+ int zmm_offset =3D 0; >>+ int pkru_offset =3D 0; >>+ >>+ bool operator!=3D (const x86_xsave_layout &other) >>+ { >>+ return sizeof_xsave !=3D other.sizeof_xsave >>+ || avx_offset !=3D other.avx_offset >>+ || bndregs_offset !=3D other.bndregs_offset >>+ || bndcfg_offset !=3D other.bndcfg_offset >>+ || k_offset !=3D other.k_offset >>+ || zmm_h_offset !=3D other.zmm_h_offset >>+ || zmm_offset !=3D other.zmm_offset >>+ || pkru_offset !=3D other.pkru_offset; >>+ } >>+}; >>+ >>+ >> /* Supported mask and size of the extended state. */ >> #define X86_XSTATE_X87_MASK X86_XSTATE_X87 >> #define X86_XSTATE_SSE_MASK (X86_XSTATE_X87 | X86_XSTATE_SSE) >>-- >>2.39.1