From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam08on2073.outbound.protection.outlook.com [40.107.101.73]) by sourceware.org (Postfix) with ESMTPS id 264C43858C56 for ; Mon, 28 Mar 2022 11:28:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 264C43858C56 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=f/RSdKwWJ4AA0lo8w0QP7CRTVZPCvh26aKTj93tGte7ZHV1h5al4rnTGIydRRZTSPMM23QkdsCb76/45IXeLjd3fiamRHPi1txwZq97pbWIdzyevK17U7IDCpkqBvCDTBFulHaaBUpMb810Qqvf9r9B7xOvfaIi4yukXiQGOCg3JbjtokL+lzG+3aOomzgOzuMGw4LOF2PDHimQB0RjxhRPhBEPE4qeyp3EL3+Xk4ry4/p4nrRedrA31d2RfWH8GkQP59fJn02gLqDJGda5R5BYsPYM5ow/6FnPfVXgkRFCNX1cP96VK+qG2SZr1eTTguSoLHI0k6z6y//mNj6WiDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=sSuqb38E1dnUNsRcmnrgkisftKFJK2CDssfvpuK50gg=; b=QhYz09lr2p+dcyp1U7FObHb35NpHlsJr20TFyfrocTq8w7fY7qOF/qk6ttNEtP/osW+KsZKHLDe7s/xtag5ol5fuPXMs/gyNbf153gRr1LCcw3RvkpyB99k8xXNu2sFKqVGqJcJ3KHMaB4Sh0JCN2FcxKIzS3hiUK1L9lmbf59bRw0IQBZ0jKUsC+cDfdJJKupyp2NVgVIdQtorG2ZlpAyn8SOY1GvhIceu1/H3ms9E/DjD4BiOa5iZStObFg7BcNjuge5vM0d42WPfmJNP+DsFYSoDKKmM67oGxNBQXOkN4GpEzSMgaYcn0Hpx0oBedAcUV0hJy+Mi6RQK50eVTNw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none Received: from BY5PR12MB4965.namprd12.prod.outlook.com (2603:10b6:a03:1c4::16) by BL0PR12MB4851.namprd12.prod.outlook.com (2603:10b6:208:1c1::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5102.18; Mon, 28 Mar 2022 11:28:53 +0000 Received: from BY5PR12MB4965.namprd12.prod.outlook.com ([fe80::2dcf:1f8c:9872:e2d8]) by BY5PR12MB4965.namprd12.prod.outlook.com ([fe80::2dcf:1f8c:9872:e2d8%7]) with mapi id 15.20.5102.023; Mon, 28 Mar 2022 11:28:51 +0000 From: "George, Jini Susan" To: John Baldwin , "gdb-patches@sourceware.org" CC: "Willgerodt@sourceware.org" , "Sharma, Alok Kumar" Subject: RE: [RFC PATCH v2 2/5] core: Support fetching TARGET_OBJECT_X86_XSAVE_LAYOUT from architectures. Thread-Topic: [RFC PATCH v2 2/5] core: Support fetching TARGET_OBJECT_X86_XSAVE_LAYOUT from architectures. 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BY5PR12MB4965.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: cfbcaab5-670d-4ac6-ca69-08da10ae227c X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Mar 2022 11:28:51.4054 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: hSblT2/PIxxs4DOvV62eArr7DOFf9a7VuXGTSy8yiRHOTU0Z0Uhg8fhwZptVEM4WyRTE5dVnzig8H0W4kSaW2w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4851 X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Mar 2022 11:29:02 -0000 [Public] Thanks for making these changes, John. I am not a gdb maintainer, but I am = inclined to be in favor of these changes till we have modifications in the = kernel to store the xsave layout indicators in the coredump. AFAIK, yes, AM= D CPUs never implemented MPX, and hence the gap wrt the xsave layout of Int= el. (There is an additional unaccounted gap of 128 bytes too). I am not sur= e as to why there is no space reserved in the standard form for MPX, but it= is for AVX-512 in CPUs where AVX-512 is not implemented. I am trying to fi= nd this out, but at this point, I don't have answers for this. Are these changes catering to corefile debugging only ? If so, are you plan= ning to make changes for live debugging ? If not, could you please let me k= now ? If you plan to proceed with the corresponding changes for Linux, I wo= uld be interested in looking at that patch too. One comment that I have is for the code in i387_set_xsave_layout(). Since t= he hardware provides a finer granularity in setting the individual xfeature= mask bits for MPX and AVX-512, I am wondering if it might be better to con= sider more scenarios like: ... else if (HAS_AVX512(xcr0) && xsave_size =3D=3D 2432) /* AMD CPUs with AVX-= 512 */ ... else if (HAS_AVX512_ZMM_HI(xcr0) && xsave_size =3D=3D 1408) ... else if (HAS_AVX512_ZMM_KREGS(xcr0) && xsave_size =3D=3D 896) ... etc. (though I don't know under what circumstances, you can have only certain co= mponents of AVX-512 or MPX turned on) -- but this would be in line with the= rest of the code changes. We also might be able to make the code simpler s= ince the post MPX xsave extended feature offsets (from opmask onwards) of A= MD would be at an offset which is 256 bytes lesser than the corresponding o= nes of Intel. AMD processors based on the Bulldozer architecture have the Light Weight Pr= ofiling regs placed at offset 832 in the xsave area -- but I believe we can= safely disregard that. Thanks, Jini. >>-----Original Message----- >>From: Gdb-patches >bounces+jigeorge=3Damd.com@sourceware.org> On Behalf Of John Baldwin >>Sent: Friday, March 18, 2022 12:06 AM >>To: gdb-patches@sourceware.org >>Cc: Willgerodt@sourceware.org >>Subject: [RFC PATCH v2 2/5] core: Support fetching >>TARGET_OBJECT_X86_XSAVE_LAYOUT from architectures. >> >>[CAUTION: External Email] >> >>Add gdbarch_core_xfer_x86_xsave_layout to fetch the x86 XSAVE layout >>structure from a core file. >> >>Current OS's do not export the offsets of XSAVE state components in core >>dumps, so provide an i387_set_xsave_layout helper function to set offsets >>based on known combinations of XCR0 masks and total state sizes. Eventua= lly >>when core dumps do contain this information this function should only be = used >>as a fall back for older core dumps. >>--- >> gdb/corelow.c | 22 +++++++++++++++++ >> gdb/gdbarch-components.py | 13 ++++++++++ >> gdb/gdbarch-gen.h | 10 ++++++++ >> gdb/gdbarch.c | 32 ++++++++++++++++++++++++ >> gdb/i387-tdep.c | 51 +++++++++++++++++++++++++++++++++++++++ >> gdb/i387-tdep.h | 7 ++++++ >> 6 files changed, 135 insertions(+) >> >>diff --git a/gdb/corelow.c b/gdb/corelow.c index 001c4f147fc..71bfdcff9dd >>100644 >>--- a/gdb/corelow.c >>+++ b/gdb/corelow.c >>@@ -987,6 +987,28 @@ core_target::xfer_partial (enum target_object object= , >>const char *annex, >> } >> return TARGET_XFER_E_IO; >> >>+ case TARGET_OBJECT_X86_XSAVE_LAYOUT: >>+ if (readbuf) >>+ { >>+ if (m_core_gdbarch !=3D nullptr >>+ && gdbarch_core_xfer_x86_xsave_layout_p (m_core_gdbarch)) >>+ { >>+ LONGEST l =3D gdbarch_core_xfer_x86_xsave_layout (m_core_g= dbarch, >>+ readbuf, o= ffset, >>+ len); >>+ >>+ if (l >=3D 0) >>+ { >>+ *xfered_len =3D l; >>+ if (l =3D=3D 0) >>+ return TARGET_XFER_EOF; >>+ else >>+ return TARGET_XFER_OK; >>+ } >>+ } >>+ } >>+ return TARGET_XFER_E_IO; >>+ >> default: >> return this->beneath ()->xfer_partial (object, annex, readbuf, >> writebuf, offset, len, diff = --git a/gdb/gdbarch- >>components.py b/gdb/gdbarch-components.py index >>c820ddae764..99eaca7f7e2 100644 >>--- a/gdb/gdbarch-components.py >>+++ b/gdb/gdbarch-components.py >>@@ -1584,6 +1584,19 @@ of bytes read (zero indicates EOF, a negative valu= e >>indicates failure). >> invalid=3DTrue, >> ) >> >>+Method( >>+ comment=3D""" >>+Read offset OFFSET of TARGET_OBJECT_X86_XSAVE_LAYOUT from core file >>+into buffer READBUF with length LEN. Return the number of bytes read >>+(zero indicates EOF, a negative value indicates failure). >>+""", >>+ type=3D"LONGEST", >>+ name=3D"core_xfer_x86_xsave_layout", >>+ params=3D[("gdb_byte *", "readbuf"), ("ULONGEST", "offset"), ("ULONG= EST", >>"len")], >>+ predicate=3DTrue, >>+ invalid=3DTrue, >>+) >>+ >> Value( >> comment=3D""" >> BFD target to use when generating a core file. >>diff --git a/gdb/gdbarch-gen.h b/gdb/gdbarch-gen.h index >>7a8721328ab..82292f9c954 100644 >>--- a/gdb/gdbarch-gen.h >>+++ b/gdb/gdbarch-gen.h >>@@ -921,6 +921,16 @@ typedef LONGEST (gdbarch_core_xfer_siginfo_ftype) >>(struct gdbarch *gdbarch, gdb_ extern LONGEST gdbarch_core_xfer_siginfo >>(struct gdbarch *gdbarch, gdb_byte *readbuf, ULONGEST offset, ULONGEST >>len); extern void set_gdbarch_core_xfer_siginfo (struct gdbarch *gdbarch= , >>gdbarch_core_xfer_siginfo_ftype *core_xfer_siginfo); >> >>+/* Read offset OFFSET of TARGET_OBJECT_X86_XSAVE_LAYOUT from core file >>+ into buffer READBUF with length LEN. Return the number of bytes read >>+ (zero indicates EOF, a negative value indicates failure). */ >>+ >>+extern bool gdbarch_core_xfer_x86_xsave_layout_p (struct gdbarch >>+*gdbarch); >>+ >>+typedef LONGEST (gdbarch_core_xfer_x86_xsave_layout_ftype) (struct >>+gdbarch *gdbarch, gdb_byte *readbuf, ULONGEST offset, ULONGEST len); >>+extern LONGEST gdbarch_core_xfer_x86_xsave_layout (struct gdbarch >>+*gdbarch, gdb_byte *readbuf, ULONGEST offset, ULONGEST len); extern >>+void set_gdbarch_core_xfer_x86_xsave_layout (struct gdbarch *gdbarch, >>+gdbarch_core_xfer_x86_xsave_layout_ftype *core_xfer_x86_xsave_layout); >>+ >> /* BFD target to use when generating a core file. */ >> >> extern bool gdbarch_gcore_bfd_target_p (struct gdbarch *gdbarch); diff -= -git >>a/gdb/gdbarch.c b/gdb/gdbarch.c index 9fdcf1505fe..e8681d8930b 100644 >>--- a/gdb/gdbarch.c >>+++ b/gdb/gdbarch.c >>@@ -176,6 +176,7 @@ struct gdbarch >> gdbarch_core_pid_to_str_ftype *core_pid_to_str; >> gdbarch_core_thread_name_ftype *core_thread_name; >> gdbarch_core_xfer_siginfo_ftype *core_xfer_siginfo; >>+ gdbarch_core_xfer_x86_xsave_layout_ftype *core_xfer_x86_xsave_layout; >> const char * gcore_bfd_target; >> int vtable_function_descriptors; >> int vbit_in_delta; >>@@ -532,6 +533,7 @@ verify_gdbarch (struct gdbarch *gdbarch) >> /* Skip verify of core_pid_to_str, has predicate. */ >> /* Skip verify of core_thread_name, has predicate. */ >> /* Skip verify of core_xfer_siginfo, has predicate. */ >>+ /* Skip verify of core_xfer_x86_xsave_layout, has predicate. */ >> /* Skip verify of gcore_bfd_target, has predicate. */ >> /* Skip verify of vtable_function_descriptors, invalid_p =3D=3D 0 */ >> /* Skip verify of vbit_in_delta, invalid_p =3D=3D 0 */ @@ -1126,6 +112= 8,12 @@ >>gdbarch_dump (struct gdbarch *gdbarch, struct ui_file *file) >> fprintf_filtered (file, >> "gdbarch_dump: core_xfer_siginfo =3D <%s>\n", >> host_address_to_string (gdbarch->core_xfer_siginfo= )); >>+ fprintf_filtered (file, >>+ "gdbarch_dump: gdbarch_core_xfer_x86_xsave_layout_= p() =3D >>%d\n", >>+ gdbarch_core_xfer_x86_xsave_layout_p (gdbarch)); >>+ fprintf_filtered (file, >>+ "gdbarch_dump: core_xfer_x86_xsave_layout =3D <%s>= \n", >>+ host_address_to_string >>+ (gdbarch->core_xfer_x86_xsave_layout)); >> fprintf_filtered (file, >> "gdbarch_dump: gdbarch_gcore_bfd_target_p() =3D %d= \n", >> gdbarch_gcore_bfd_target_p (gdbarch)); @@ -3864,6 = +3872,30 >>@@ set_gdbarch_core_xfer_siginfo (struct gdbarch *gdbarch, >> gdbarch->core_xfer_siginfo =3D core_xfer_siginfo; } >> >>+bool >>+gdbarch_core_xfer_x86_xsave_layout_p (struct gdbarch *gdbarch) { >>+ gdb_assert (gdbarch !=3D NULL); >>+ return gdbarch->core_xfer_x86_xsave_layout !=3D NULL; } >>+ >>+LONGEST >>+gdbarch_core_xfer_x86_xsave_layout (struct gdbarch *gdbarch, gdb_byte >>+*readbuf, ULONGEST offset, ULONGEST len) { >>+ gdb_assert (gdbarch !=3D NULL); >>+ gdb_assert (gdbarch->core_xfer_x86_xsave_layout !=3D NULL); >>+ if (gdbarch_debug >=3D 2) >>+ fprintf_unfiltered (gdb_stdlog, "gdbarch_core_xfer_x86_xsave_layout >>+called\n"); >>+ return gdbarch->core_xfer_x86_xsave_layout (gdbarch, readbuf, offset, >>+len); } >>+ >>+void >>+set_gdbarch_core_xfer_x86_xsave_layout (struct gdbarch *gdbarch, >>+ >>+gdbarch_core_xfer_x86_xsave_layout_ftype core_xfer_x86_xsave_layout) { >>+ gdbarch->core_xfer_x86_xsave_layout =3D core_xfer_x86_xsave_layout; } >>+ >> bool >> gdbarch_gcore_bfd_target_p (struct gdbarch *gdbarch) { diff --git a/gdb= /i387- >>tdep.c b/gdb/i387-tdep.c index 2f0b6509457..83df8a7fb0f 100644 >>--- a/gdb/i387-tdep.c >>+++ b/gdb/i387-tdep.c >>@@ -898,6 +898,57 @@ static int xsave_pkeys_offset[] =3D >> (xsave + xsave_pkeys_offset[regnum - I387_PKRU_REGNUM (tdep)]) >> >> >>+/* See i387-tdep.h. */ >>+ >>+void >>+i387_set_xsave_layout (uint64_t xcr0, size_t xsave_size, >>+ x86_xsave_layout *layout) { >>+ layout->sizeof_xsave =3D xsave_size; >>+ if (HAS_PKRU(xcr0) && xsave_size =3D=3D 2696) >>+ { >>+ /* Intel CPUs supporting PKRU. */ >>+ layout->avx_offset =3D 576; >>+ layout->bndregs_offset =3D 960; >>+ layout->bndcfg_offset =3D 1024; >>+ layout->avx512_k_offset =3D 1088; >>+ layout->avx512_zmm_h_offset =3D 1152; >>+ layout->avx512_zmm_offset =3D 1664; >>+ layout->pkru_offset =3D 2688; >>+ } >>+ else if (HAS_PKRU(xcr0) && xsave_size =3D=3D 2440) >>+ { >>+ /* AMD Ryzen 9 CPUs supporting PKRU. */ >>+ layout->avx_offset =3D 576; >>+ layout->avx512_k_offset =3D 832; >>+ layout->avx512_zmm_h_offset =3D 896; >>+ layout->avx512_zmm_offset =3D 1408; >>+ layout->pkru_offset =3D 2432; >>+ } >>+ else if (HAS_AVX512(xcr0) && xsave_size =3D=3D 2688) >>+ { >>+ /* Intel CPUs supporting AVX512. */ >>+ layout->avx_offset =3D 576; >>+ layout->bndregs_offset =3D 960; >>+ layout->bndcfg_offset =3D 1024; >>+ layout->avx512_k_offset =3D 1088; >>+ layout->avx512_zmm_h_offset =3D 1152; >>+ layout->avx512_zmm_offset =3D 1664; >>+ } >>+ else if (HAS_MPX(xcr0) && xsave_size =3D=3D 1088) >>+ { >>+ /* Intel CPUs supporting MPX. */ >>+ layout->avx_offset =3D 576; >>+ layout->bndregs_offset =3D 960; >>+ layout->bndcfg_offset =3D 1024; >>+ } >>+ else if (HAS_AVX(xcr0) && xsave_size =3D=3D 832) >>+ { >>+ /* Intel and AMD CPUs supporting AVX. */ >>+ layout->avx_offset =3D 576; >>+ } >>+} >>+ >> /* Extract from XSAVE a bitset of the features that are available on the >> target, but which have not yet been enabled. */ >> >>diff --git a/gdb/i387-tdep.h b/gdb/i387-tdep.h index 698ff2ee206..4e1403a= a753 >>100644 >>--- a/gdb/i387-tdep.h >>+++ b/gdb/i387-tdep.h >>@@ -25,6 +25,7 @@ struct frame_info; >> struct regcache; >> struct type; >> struct ui_file; >>+struct x86_xsave_layout; >> >> /* Number of i387 floating point registers. */ #define I387_NUM_REGS = 16 >>@@ -138,6 +139,12 @@ extern void i387_collect_fsave (const struct regcach= e >>*regcache, int regnum, extern void i387_supply_fxsave (struct regcache >>*regcache, int regnum, >> const void *fxsave); >> >>+/* Select an XSAVE layout based on the XCR0 bitmask and total XSAVE >>+ extended state size. */ >>+ >>+extern void i387_set_xsave_layout (uint64_t xcr0, size_t xsave_size, >>+ x86_xsave_layout *layout); >>+ >> /* Similar to i387_supply_fxsave, but use XSAVE extended state. */ >> >> extern void i387_supply_xsave (struct regcache *regcache, int regnum, >>-- >>2.34.1