From: Greg Savin <greg.savin@sifive.com>
To: Andrew Burgess <aburgess@redhat.com>
Cc: Greg Savin via Gdb-patches <gdb-patches@sourceware.org>,
Andrew Burgess <andrew.burgess@embecosm.com>,
John Baldwin <jhb@freebsd.org>
Subject: Re: [PATCH v2] RISC-V: support for vector register accesses via ptrace() in RISC-V Linux native
Date: Fri, 11 Aug 2023 09:41:10 -0700 [thread overview]
Message-ID: <CADdv1FpH6YSN6dFXFwVwCMgFWU63X-FtVhSYANo9sJsNvTd-Zw@mail.gmail.com> (raw)
In-Reply-To: <87msyxd57t.fsf@redhat.com>
[-- Attachment #1: Type: text/plain, Size: 724 bytes --]
> Based on some of the other emails, I guess kernel support for some of
> this is still WIP, so I guess there's not "easy" way to test this? Does
> QEMU have vector support yet?
>
> I've used a QEMU build that models RISC-V vectors, and tried out this GDB
patch interactively (mostly via "info reg vector" but also accesses through
dollar sign syntax with specific register values, reading and writing).
Though the QEMU I use for that is from a non-upstream fork, and I'm not
sure if upstream QEMU has all the capabilities for running RISCV-V vector
configurations yet. I'll ask the people who provided the QEMU build I've
been using.
Thanks Andrew, I'll take a closer look at your other review comments on
this.
--Greg
next prev parent reply other threads:[~2023-08-11 16:41 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-03 23:01 [PATCH] " Greg Savin
2023-08-04 0:21 ` John Baldwin
2023-08-08 22:50 ` [PATCH v2] " Greg Savin
2023-08-11 14:27 ` Andrew Burgess
2023-08-11 16:41 ` Greg Savin [this message]
2023-08-09 9:21 ` [PATCH] " Maciej W. Rozycki
2023-08-09 18:11 ` Greg Savin
2023-08-09 23:09 ` Maciej W. Rozycki
2023-08-10 10:35 ` Andy Chiu
2023-08-10 11:40 ` Maciej W. Rozycki
2023-08-10 13:55 ` Maciej W. Rozycki
2023-08-10 17:23 ` Andy Chiu
2023-08-10 21:08 ` Palmer Dabbelt
2023-08-10 21:21 ` Maciej W. Rozycki
2023-08-11 11:28 ` Andy Chiu
2023-08-10 14:05 ` Andy Chiu
2023-08-10 20:51 ` Maciej W. Rozycki
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