From: Jim Wilson <jimw@sifive.com>
To: Jim Wilson <jimw@sifive.com>,
gdb-patches@sourceware.org, Kito Cheng <kito.cheng@gmail.com>
Subject: Re: [PATCH 03/24] RISC-V sim: Atomic fixes.
Date: Wed, 21 Apr 2021 16:00:55 -0700 [thread overview]
Message-ID: <CAFyWVaYOY4ayj47nOe-2oGqUUv62zP5h+i8p7fA62c6996J21w@mail.gmail.com> (raw)
In-Reply-To: <YHz/XemFpNfU+UsW@vapier>
On Sun, Apr 18, 2021 at 8:56 PM Mike Frysinger <vapier@gentoo.org> wrote:
> On 17 Apr 2021 10:58, Jim Wilson wrote:
> > Handle aq and rl. Fix wrong value when rd is zero register. Fix
> > amoswap when rd and rs2 are the same register.
>
> lgtm. can you add tests for these things, and for the other fixes ?
>
Tests for these amo issues would be useful, as this isn't well tested by
the gcc testsuite. I will look into that.
Most of the other stuff is well tested just by running the gcc testsuite.
I'm working on the gdb sim as a side project while working on other
projects, and if I have to write a lot of tests there could be a
significant delay in completing the patch set. I'd prefer if some of this
stuff could be handled with follow up patches.
Jim
next prev parent reply other threads:[~2021-04-21 23:01 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-17 17:58 [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain Jim Wilson
2021-04-17 17:58 ` [PATCH 01/24] RISC-V sim: Fix fence.i Jim Wilson
2021-04-17 20:36 ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 02/24] RISC-V sim: Fix for jalr Jim Wilson
2021-04-19 3:41 ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 03/24] RISC-V sim: Atomic fixes Jim Wilson
2021-04-19 3:56 ` Mike Frysinger
2021-04-21 23:00 ` Jim Wilson [this message]
2021-04-22 0:09 ` Mike Frysinger
2021-04-22 3:12 ` Jim Wilson
2021-04-17 17:58 ` [PATCH 04/24] RISC-V sim: More atomic fixes Jim Wilson
2021-04-19 3:57 ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 05/24] RISC-V sim: Fix stack pointer alignment Jim Wilson
2021-04-19 3:58 ` Mike Frysinger
2021-04-21 22:39 ` Jim Wilson
2021-04-17 17:58 ` [PATCH 06/24] RISC-V: Add fp support Jim Wilson
2021-04-19 4:08 ` Mike Frysinger
2021-04-21 23:34 ` Jim Wilson
2021-04-17 17:58 ` [PATCH 07/24] RISC-V sim: Add link syscall support Jim Wilson
2021-04-19 4:09 ` Mike Frysinger
2021-04-21 23:36 ` Jim Wilson
2021-04-17 17:58 ` [PATCH 08/24] RISC-V sim: Add brk syscall Jim Wilson
2021-04-19 5:24 ` Mike Frysinger
2021-04-21 23:51 ` Jim Wilson
2021-04-17 17:58 ` [PATCH 09/24] RISC-V sim: Fix syscall fallback Jim Wilson
2021-04-21 23:38 ` Jim Wilson
2021-04-22 3:23 ` Mike Frysinger
2021-04-23 20:35 ` Jim Wilson
2021-04-17 17:58 ` [PATCH 10/24] RISC-V sim: Fix ebreak Jim Wilson
2021-04-19 4:20 ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 11/24] RISC-V sim: Fix ebreak, part 2 Jim Wilson
2021-04-19 4:20 ` Mike Frysinger
2021-04-21 23:41 ` Jim Wilson
2021-04-17 17:58 ` [PATCH 12/24] RISC-V sim: Add compressed support Jim Wilson
2021-04-19 4:13 ` Mike Frysinger
2021-04-21 23:42 ` Jim Wilson
2021-04-17 17:58 ` [PATCH 13/24] RISC-V sim: Add gettimeofday Jim Wilson
2021-04-19 4:19 ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 14/24] RISC-V sim: Add csrr*i instructions Jim Wilson
2021-04-19 4:26 ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 15/24] RISC-V sim: Improve cycle and instret counts Jim Wilson
2021-04-19 4:25 ` Mike Frysinger
2021-04-22 2:26 ` Jim Wilson
2021-04-17 17:58 ` [PATCH 16/24] RISC-V sim: Check sbrk argument Jim Wilson
2021-04-19 5:33 ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 17/24] RISC-V sim: Fix tracing typo Jim Wilson
2021-04-19 4:26 ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 18/24] RISC-V sim: Improve branch tracing Jim Wilson
2021-04-19 4:27 ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 19/24] RISC-V sim: Improve tracing for slt* instructions Jim Wilson
2021-04-19 4:27 ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 20/24] RISC-V sim: Set brk to _end if possible Jim Wilson
2021-04-19 5:41 ` Mike Frysinger
2021-04-22 2:45 ` Jim Wilson
2021-04-17 17:58 ` [PATCH 21/24] RISC-V sim: Fix mingw builds Jim Wilson
2021-04-19 4:12 ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 22/24] RISC-V sim: Support compressed FP instructions Jim Wilson
2021-04-19 4:27 ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 23/24] RISC-V sim: Add zicsr support Jim Wilson
2021-04-19 5:13 ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 24/24] RISC-V sim: Fix divw and remw Jim Wilson
2021-04-19 5:10 ` Mike Frysinger
2021-04-17 20:38 ` [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain Mike Frysinger
2021-04-19 2:33 ` Jim Wilson
2021-04-19 3:23 ` Mike Frysinger
2021-04-19 4:32 ` Jim Wilson
2021-04-19 3:42 ` Mike Frysinger
2021-04-19 4:37 ` Jim Wilson
2021-04-21 15:47 ` Andrew Burgess
2021-04-21 17:49 ` Andrew Burgess
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