[PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain.

[PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain.

[Jim Wilson]

These are mostly patches extracted from riscv-gnu-toolchain with minor
changes to apply to current FSF GDB sim.  I was careful to maintain the
original author info, and the original commit logs when reasonable.
There are also a few extra patches from me added in, as I noticed some
problems when reviewing the patches, and debugging issues.  Note that
Kito and Monk were at Andes when they wrote these patches, and are now
at SiFive.  So this is mostly Andes work, and they should get credit
for this work.  I kept their original email addresses even though they
won't work anymore.  We will need permission from Andes to merge the
patches into FSF GDB.  Hopefully Kuan-Lin can do that for us.  The patches
from Palmer and myself were written at SiFive.

I tested this with a gcc make check using riscv-gnu-toolchain and pulling
in FSF GDB sim with my patches applied.  I get 13 gcc unexpected failures
for rv32imac/ilp32 and 24 gcc unexpected failures for rv64gc/lp64d which
matches the old simulator port in riscv-gnu-toolchain.  I did have one
problem with the GNUC code in mulhu function producing the wrong result,
but I think that is a bug in the Ubuntu 16.04 gcc-4.8 on my server.  If
this is still broken with newer gcc versions I will take another look at
that.

This code can probably use some cleanup.  I'd like to see the extensions
in canonical arch order for instance.  But dealing with this many patches
is unwieldy, and I wanted to retain the original authorship for the
patches, so I'd rather do cleanup work as follow on patches.

Jim

Jim Wilson (6):
  RISC-V sim: Fix fence.i.
  RISC-V sim: More atomic fixes.
  RISC-V sim: Fix ebreak, part 2.
  RISC-V sim: Fix mingw builds.
  RISC-V sim: Support compressed FP instructions.
  RISC-V sim: Add zicsr support.

Kito Cheng (9):
  RISC-V sim: Atomic fixes.
  RISC-V sim: Fix syscall fallback.
  RISC-V sim: Add csrr*i instructions.
  RISC-V sim: Improve cycle and instret counts.
  RISC-V sim: Check sbrk argument.
  RISC-V sim: Improve branch tracing.
  RISC-V sim: Improve tracing for slt* instructions.
  RISC-V sim: Set brk to _end if possible.
  RISC-V sim: Fix divw and remw.

Kuan-Lin Chen (5):
  RISC-V sim: Fix stack pointer alignment.
  RISC-V sim: Add link syscall support.
  RISC-V sim: Add brk syscall.
  RISC-V sim: Add gettimeofday.
  RISC-V sim: Fix tracing typo.

Monk Chiang (3):
  RISC-V: Add fp support.
  RISC-V sim: Fix ebreak.
  RISC-V sim: Add compressed support.

Palmer Dabbelt (1):
  RISC-V sim: Fix for jalr.

 sim/riscv/interp.c   |   45 ++
 sim/riscv/sim-main.c | 1790 ++++++++++++++++++++++++++++++++++++++++++++++----
 sim/riscv/sim-main.h |   16 +-
 3 files changed, 1733 insertions(+), 118 deletions(-)

-- 
2.7.4

[PATCH 01/24] RISC-V sim: Fix fence.i.

[Jim Wilson]

The fence.i instruction was moved to the zifencei extension.

	sim/riscv/
	* sim-main.c (execute_i): Drop MATCH_FENCE_I here.
	(execute_zifencei): New function, with MATCH_FENCE_I support.
	(execute_one): Call execute_zifencei.
---
 sim/riscv/sim-main.c | 25 ++++++++++++++++++++++---
 1 file changed, 22 insertions(+), 3 deletions(-)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index ff328a0..ccab3ba 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -580,9 +580,6 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
     case MATCH_FENCE:
       TRACE_INSN (cpu, "fence;");
       break;
-    case MATCH_FENCE_I:
-      TRACE_INSN (cpu, "fence.i;");
-      break;
     case MATCH_SBREAK:
       TRACE_INSN (cpu, "sbreak;");
       /* GDB expects us to step over SBREAK.  */
@@ -922,6 +919,26 @@ execute_a (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 }
 
 static sim_cia
+execute_zifencei (SIM_CPU *cpu, unsigned_word iw,
+		  const struct riscv_opcode *op)
+{
+  SIM_DESC sd = CPU_STATE (cpu);
+  sim_cia pc = cpu->pc + 4;
+
+  switch (op->match)
+    {
+    case MATCH_FENCE_I:
+      TRACE_INSN (cpu, "fence.i;");
+      break;
+    default:
+      TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
+      sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
+    }
+
+  return pc;
+}
+
+static sim_cia
 execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 {
   SIM_DESC sd = CPU_STATE (cpu);
@@ -939,6 +956,8 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
       return execute_i (cpu, iw, op);
     case INSN_CLASS_M:
       return execute_m (cpu, iw, op);
+    case INSN_CLASS_ZIFENCEI:
+      return execute_zifencei (cpu, iw, op);
     default:
       TRACE_INSN (cpu, "UNHANDLED EXTENSION: %d", op->insn_class);
       sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
-- 
2.7.4

Re: [PATCH 01/24] RISC-V sim: Fix fence.i.

[Mike Frysinger]

On 17 Apr 2021 10:58, Jim Wilson wrote:
> The fence.i instruction was moved to the zifencei extension.

lgtm, thanks
-mike

[PATCH 02/24] RISC-V sim: Fix for jalr.

[Jim Wilson]

From: Palmer Dabbelt <palmer@dabbelt.com>

When rd and rs1 are the same reg, must read rs1 before writing rd.
Jal is also fixed for consistency.

	sim/riscv/
	* sim-main.c (execute_i): In case MATCH_JAL, move store_rd call
	after assignment to pc.  In case MATCH_JALR, likewise.
---
 sim/riscv/sim-main.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index ccab3ba..ddc1060 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -417,14 +417,14 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
     case MATCH_JAL:
       TRACE_INSN (cpu, "jal %s, %" PRIiTW ";", rd_name,
 		  EXTRACT_JTYPE_IMM (iw));
-      store_rd (cpu, rd, cpu->pc + 4);
       pc = cpu->pc + EXTRACT_JTYPE_IMM (iw);
+      store_rd (cpu, rd, cpu->pc + 4);
       TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
       break;
     case MATCH_JALR:
       TRACE_INSN (cpu, "jalr %s, %s, %" PRIiTW ";", rd_name, rs1_name, i_imm);
-      store_rd (cpu, rd, cpu->pc + 4);
       pc = cpu->regs[rs1] + i_imm;
+      store_rd (cpu, rd, cpu->pc + 4);
       TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
       break;
 
-- 
2.7.4

Re: [PATCH 02/24] RISC-V sim: Fix for jalr.

[Mike Frysinger]

On 17 Apr 2021 10:58, Jim Wilson wrote:
> When rd and rs1 are the same reg, must read rs1 before writing rd.
> Jal is also fixed for consistency.

lgtm, thanks
-mike

[PATCH 03/24] RISC-V sim: Atomic fixes.

[Jim Wilson]

From: Kito Cheng <kito.cheng@gmail.com>

Handle aq and rl.  Fix wrong value when rd is zero register.  Fix
amoswap when rd and rs2 are the same register.

	sim/riscv/
	* sim-main.c (execute_a): New locals aqrl_mask and rs2_val.
	Use aqrl_mask in switches, and rs2_val to replace cpu->regs[rs2].
---
 sim/riscv/sim-main.c | 24 +++++++++++++-----------
 1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index ddc1060..eaf0da2 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -800,11 +800,13 @@ execute_a (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
   const char *rs1_name = riscv_gpr_names_abi[rs1];
   const char *rs2_name = riscv_gpr_names_abi[rs2];
   struct atomic_mem_reserved_list *amo_prev, *amo_curr;
+  insn_t aqrl_mask = (OP_MASK_AQ << OP_SH_AQ) | (OP_MASK_RL << OP_SH_RL);
   unsigned_word tmp;
+  unsigned_word rs2_val = cpu->regs[rs2];
   sim_cia pc = cpu->pc + 4;
 
   /* Handle these two load/store operations specifically.  */
-  switch (op->match)
+  switch (op->match & ~aqrl_mask)
     {
     case MATCH_LR_W:
       TRACE_INSN (cpu, "%s %s, (%s);", op->name, rd_name, rs1_name);
@@ -866,43 +868,43 @@ execute_a (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 					       cpu->regs[rs1]));
   store_rd (cpu, rd, tmp);
 
-  switch (op->match)
+  switch (op->match & ~aqrl_mask)
     {
     case MATCH_AMOADD_D:
     case MATCH_AMOADD_W:
-      tmp = cpu->regs[rd] + cpu->regs[rs2];
+      tmp = tmp + cpu->regs[rs2];
       break;
     case MATCH_AMOAND_D:
     case MATCH_AMOAND_W:
-      tmp = cpu->regs[rd] & cpu->regs[rs2];
+      tmp = tmp & cpu->regs[rs2];
       break;
     case MATCH_AMOMAX_D:
     case MATCH_AMOMAX_W:
-      tmp = MAX ((signed_word) cpu->regs[rd], (signed_word) cpu->regs[rs2]);
+      tmp = MAX ((signed_word) tmp, (signed_word) cpu->regs[rs2]);
       break;
     case MATCH_AMOMAXU_D:
     case MATCH_AMOMAXU_W:
-      tmp = MAX ((unsigned_word) cpu->regs[rd], (unsigned_word) cpu->regs[rs2]);
+      tmp = MAX ((unsigned_word) tmp, (unsigned_word) cpu->regs[rs2]);
       break;
     case MATCH_AMOMIN_D:
     case MATCH_AMOMIN_W:
-      tmp = MIN ((signed_word) cpu->regs[rd], (signed_word) cpu->regs[rs2]);
+      tmp = MIN ((signed_word) tmp, (signed_word) cpu->regs[rs2]);
       break;
     case MATCH_AMOMINU_D:
     case MATCH_AMOMINU_W:
-      tmp = MIN ((unsigned_word) cpu->regs[rd], (unsigned_word) cpu->regs[rs2]);
+      tmp = MIN ((unsigned_word) tmp, (unsigned_word) cpu->regs[rs2]);
       break;
     case MATCH_AMOOR_D:
     case MATCH_AMOOR_W:
-      tmp = cpu->regs[rd] | cpu->regs[rs2];
+      tmp = tmp | cpu->regs[rs2];
       break;
     case MATCH_AMOSWAP_D:
     case MATCH_AMOSWAP_W:
-      tmp = cpu->regs[rs2];
+      tmp = rs2_val;
       break;
     case MATCH_AMOXOR_D:
     case MATCH_AMOXOR_W:
-      tmp = cpu->regs[rd] ^ cpu->regs[rs2];
+      tmp = tmp ^ cpu->regs[rs2];
       break;
     default:
       TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
-- 
2.7.4

Re: [PATCH 03/24] RISC-V sim: Atomic fixes.

[Mike Frysinger]

On 17 Apr 2021 10:58, Jim Wilson wrote:
> Handle aq and rl.  Fix wrong value when rd is zero register.  Fix
> amoswap when rd and rs2 are the same register.

lgtm.  can you add tests for these things, and for the other fixes ?
-mike

Re: [PATCH 03/24] RISC-V sim: Atomic fixes.

[Jim Wilson]

On Sun, Apr 18, 2021 at 8:56 PM Mike Frysinger <vapier@gentoo.org> wrote:

> On 17 Apr 2021 10:58, Jim Wilson wrote:
> > Handle aq and rl.  Fix wrong value when rd is zero register.  Fix
> > amoswap when rd and rs2 are the same register.
>
> lgtm.  can you add tests for these things, and for the other fixes ?
>

Tests for these amo issues would be useful, as this isn't well tested by
the gcc testsuite.  I will look into that.

Most of the other stuff is well tested just by running the gcc testsuite.
I'm working on the gdb sim as a side project while working on other
projects, and if I have to write a lot of tests there could be a
significant delay in completing the patch set.  I'd prefer if some of this
stuff could be handled with follow up patches.

Jim

Re: [PATCH 03/24] RISC-V sim: Atomic fixes.

[Mike Frysinger]

On 21 Apr 2021 16:00, Jim Wilson wrote:
> On Sun, Apr 18, 2021 at 8:56 PM Mike Frysinger wrote:
> > On 17 Apr 2021 10:58, Jim Wilson wrote:
> > > Handle aq and rl.  Fix wrong value when rd is zero register.  Fix
> > > amoswap when rd and rs2 are the same register.
> >
> > lgtm.  can you add tests for these things, and for the other fixes ?
> 
> Tests for these amo issues would be useful, as this isn't well tested by
> the gcc testsuite.  I will look into that.
> 
> Most of the other stuff is well tested just by running the gcc testsuite.

imo, "just run the gcc testsuite" is not reasonable.  it is extremely large
and slow and not conducive to iterative/fast development.   it happening to
hit a bug sometimes depending on the current codegen behavior isn't the same
as having good targetted logic.

that isn't to say the gcc testsuite isn't valuable.  it certainly is as a
large stress when you're pretty confident that the sim/whatever is ready to
run against it.  but i'm not running it every day (or even some months) when
working on the sim, and most projects i've worked on run it daily at best on
servers.

that said, i'm not advocating for 1000% coverage on the sim side.  having a
few important high level things to start with is fine, and then taking the
approach like gcc where we fill it out based on regressions.

> I'm working on the gdb sim as a side project while working on other
> projects, and if I have to write a lot of tests there could be a
> significant delay in completing the patch set.  I'd prefer if some of this
> stuff could be handled with follow up patches.

my concern is that this becomes a convenient "we'll get to it later" and then
later never comes.  i'm not saying you don't have good intentions, but they
often don't last with real world pressures.  the only carrot/leverage that
exists is not yet being merged.

so maybe, maybe, you get a pass now, but this isn't the status quo moving
forward.
-mike

Re: [PATCH 03/24] RISC-V sim: Atomic fixes.

[Jim Wilson]

On Wed, Apr 21, 2021 at 5:09 PM Mike Frysinger <vapier@gentoo.org> wrote:

> > Most of the other stuff is well tested just by running the gcc testsuite.
>
> imo, "just run the gcc testsuite" is not reasonable.  it is extremely large
> and slow and not conducive to iterative/fast development.   it happening to
> hit a bug sometimes depending on the current codegen behavior isn't the
> same
> as having good targetted logic.
>

I agree that the sim should have good testcases.  It is only a question of
how we get there.  I'm stretched thin.  If you want me to work on this, it
will likely take a while.  Meanwhile, the RISC-V sim won't be very useful
until most of these patches get merged in.  Some of the syscall stuff could
just be dropped from this patch set if you don't like them, they aren't
critical.  Most of the rest is necessary to get a working simulator.

my concern is that this becomes a convenient "we'll get to it later" and
> then
> later never comes.  i'm not saying you don't have good intentions, but they
> often don't last with real world pressures.  the only carrot/leverage that
> exists is not yet being merged.
>
> so maybe, maybe, you get a pass now, but this isn't the status quo moving
> forward.
>

I'm helping maintain about 8 different software packages, 3 documents, and
doing support on multiple mailing lists and social media channels for 3
organizations.  So yes, there is risk that stuff may get delayed or
dropped.  But I've been doing GNU toolchain work for 34 years now, so I'm
not going away tomorrow unless maybe I have a heart attack or something.
And I'm hoping that more people start helping maintain this stuff as RISC-V
gets more mainstream.  Meanwhile, I'd much rather have a useful RISC-V sim
upstream than the one we have now.  I think others are more likely to help
if we have a working simulator upstream.  Also, part of the plan here is to
kill off the github riscv/riscv-binutils-gdb tree to force people to work
upstream.  But that gets more complicated if riscv-binutils-gdb has a
working simulator, and FSF gdb does not.  These gdb sim patches are the
only major non-ISA-extension work that hasn't been upstreamed yet.  And we
have separate plans for the ISA-extension work to put them on development
branches in the FSF trees.

Jim

[PATCH 04/24] RISC-V sim: More atomic fixes.

[Jim Wilson]

Last patch was incomplete, as all amo instructions need fix for when
rd and rs2 are the same register.

	sim/riscv/
	* sim-main.c (execute_a): Use rs2_val instead of cpu->regs[rs2]
	in more cases.
---
 sim/riscv/sim-main.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index eaf0da2..b6ae060 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -802,6 +802,8 @@ execute_a (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
   struct atomic_mem_reserved_list *amo_prev, *amo_curr;
   insn_t aqrl_mask = (OP_MASK_AQ << OP_SH_AQ) | (OP_MASK_RL << OP_SH_RL);
   unsigned_word tmp;
+  /* We need the original value of rs2.  Might change if rd and rs2 are
+     the same register.  */
   unsigned_word rs2_val = cpu->regs[rs2];
   sim_cia pc = cpu->pc + 4;
 
@@ -872,31 +874,31 @@ execute_a (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
     {
     case MATCH_AMOADD_D:
     case MATCH_AMOADD_W:
-      tmp = tmp + cpu->regs[rs2];
+      tmp = tmp + rs2_val;
       break;
     case MATCH_AMOAND_D:
     case MATCH_AMOAND_W:
-      tmp = tmp & cpu->regs[rs2];
+      tmp = tmp & rs2_val;
       break;
     case MATCH_AMOMAX_D:
     case MATCH_AMOMAX_W:
-      tmp = MAX ((signed_word) tmp, (signed_word) cpu->regs[rs2]);
+      tmp = MAX ((signed_word) tmp, (signed_word) rs2_val);
       break;
     case MATCH_AMOMAXU_D:
     case MATCH_AMOMAXU_W:
-      tmp = MAX ((unsigned_word) tmp, (unsigned_word) cpu->regs[rs2]);
+      tmp = MAX ((unsigned_word) tmp, (unsigned_word) rs2_val);
       break;
     case MATCH_AMOMIN_D:
     case MATCH_AMOMIN_W:
-      tmp = MIN ((signed_word) tmp, (signed_word) cpu->regs[rs2]);
+      tmp = MIN ((signed_word) tmp, (signed_word) rs2_val);
       break;
     case MATCH_AMOMINU_D:
     case MATCH_AMOMINU_W:
-      tmp = MIN ((unsigned_word) tmp, (unsigned_word) cpu->regs[rs2]);
+      tmp = MIN ((unsigned_word) tmp, (unsigned_word) rs2_val);
       break;
     case MATCH_AMOOR_D:
     case MATCH_AMOOR_W:
-      tmp = tmp | cpu->regs[rs2];
+      tmp = tmp | rs2_val;
       break;
     case MATCH_AMOSWAP_D:
     case MATCH_AMOSWAP_W:
@@ -904,7 +906,7 @@ execute_a (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
       break;
     case MATCH_AMOXOR_D:
     case MATCH_AMOXOR_W:
-      tmp = tmp ^ cpu->regs[rs2];
+      tmp = tmp ^ rs2_val;
       break;
     default:
       TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
-- 
2.7.4

Re: [PATCH 04/24] RISC-V sim: More atomic fixes.

[Mike Frysinger]

On 17 Apr 2021 10:58, Jim Wilson wrote:
> Last patch was incomplete, as all amo instructions need fix for when
> rd and rs2 are the same register.

lgtm.  semi on the fence about just squashing, but i guess if two different
people authored these, then OK.
-mike

[PATCH 05/24] RISC-V sim: Fix stack pointer alignment.

[Jim Wilson]

From: Kuan-Lin Chen <rufus@andestech.com>

Initialize stack pointer to 16-byte aligned in both rv32 and rv64 as
per the ABI.

	sim/riscv/
	* sim-main.c (initialize_env): Call align_down when setting sp.
---
 sim/riscv/sim-main.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index b6ae060..1b9fb89 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -1210,6 +1210,8 @@ initialize_env (SIM_DESC sd, const char * const *argv, const char * const *env)
   sp = sp_flat - ((argc + 1 + envc + 1) * sizeof (address_word));
   /* Then the argc.  */
   sp -= sizeof (unsigned_word);
+  /* Synchronize sp alignment with GCC's STACK_BOUNDARY.  */
+  sp = align_down (sp, 16);
 
   /* Set up the regs the libgloss crt0 expects.  */
   cpu->a0 = argc;
-- 
2.7.4

Re: [PATCH 05/24] RISC-V sim: Fix stack pointer alignment.

[Mike Frysinger]

On 17 Apr 2021 10:58, Jim Wilson wrote:
> Initialize stack pointer to 16-byte aligned in both rv32 and rv64 as
> per the ABI.

this is good ...

> +  /* Synchronize sp alignment with GCC's STACK_BOUNDARY.  */

... this is not.  this should state the reason as ABI requirements, not a
random toolchain implementation.

otherwise change is fine of course.
-mike

Re: [PATCH 05/24] RISC-V sim: Fix stack pointer alignment.

[Jim Wilson]

On Sun, Apr 18, 2021 at 8:58 PM Mike Frysinger <vapier@gentoo.org> wrote:

> > +  /* Synchronize sp alignment with GCC's STACK_BOUNDARY.  */
>
> ... this is not.  this should state the reason as ABI requirements, not a
> random toolchain implementation.
>

OK.  I rewrote the comment as
  /* Align stack as per ABI requirement.  16 bytes for rv32i and rv64i.  */

JIm

[PATCH 06/24] RISC-V: Add fp support.

[Jim Wilson]

From: Monk Chiang <monk@andestech.com>

Add F and D instruction support.

	sim/riscv/
	* sim-main.c: Include sim-fpu.h.
	(store_frd, store_frd64, execute_d, execute_f): New functions.
	(execute_i): Call new execute functions.
	* sim-main.h (union FRegisterValue): New.
	(struct _sim_cpu): Change fpregs to use FRegisterValue.
---
 sim/riscv/sim-main.c | 662 +++++++++++++++++++++++++++++++++++++++++++++++++++
 sim/riscv/sim-main.h |  15 +-
 2 files changed, 676 insertions(+), 1 deletion(-)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 1b9fb89..de76089 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -27,6 +27,7 @@
 #include <time.h>
 
 #include "sim-main.h"
+#include "sim-fpu.h"
 #include "sim-syscall.h"
 
 #include "opcode/riscv.h"
@@ -72,6 +73,18 @@ store_rd (SIM_CPU *cpu, int rd, unsigned_word val)
     }
 }
 
+static INLINE void
+store_frd (SIM_CPU *cpu, int rd, unsigned_word val)
+{
+  cpu->fpregs[rd].w[0] = val;
+}
+
+static inline void
+store_frd64 (SIM_CPU *cpu, int rd, uint64_t val)
+{
+  cpu->fpregs[rd].v[0] = val;
+}
+
 static INLINE unsigned_word
 fetch_csr (SIM_CPU *cpu, const char *name, int csr, unsigned_word *reg)
 {
@@ -144,6 +157,651 @@ ashiftrt64 (unsigned_word val, unsigned_word shift)
 }
 
 static sim_cia
+execute_d (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
+{
+  SIM_DESC sd = CPU_STATE (cpu);
+  unsigned int mask_arithmetic = MASK_FADD_D;
+  unsigned int mask_mul_add = MASK_FMADD_S;
+  unsigned int mask_convert = MASK_FCVT_S_W;
+
+  static const int round_modes[] =
+  {
+      sim_fpu_round_near, sim_fpu_round_zero,
+      sim_fpu_round_down, sim_fpu_round_up,
+      sim_fpu_round_default, sim_fpu_round_default,
+      sim_fpu_round_default
+  };
+
+  int rd = (iw >> OP_SH_RD) & OP_MASK_RD;
+  int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1;
+  int rs2 = (iw >> OP_SH_RS2) & OP_MASK_RS2;
+  int rs3 = (iw >> OP_SH_RS3) & OP_MASK_RS3;
+  const char *frd_name = riscv_fpr_names_abi[rd];
+  const char *frs1_name = riscv_fpr_names_abi[rs1];
+  const char *frs2_name = riscv_fpr_names_abi[rs2];
+  const char *frs3_name = riscv_fpr_names_abi[rs3];
+  const char *rd_name = riscv_gpr_names_abi[rd];
+  const char *rs1_name = riscv_gpr_names_abi[rs1];
+  unsigned_word i_imm = EXTRACT_ITYPE_IMM (iw);
+  unsigned_word s_imm = EXTRACT_STYPE_IMM (iw);
+  uint32_t u32;
+  int32_t i32;
+  uint64_t u64;
+  int64_t i64;
+  sim_cia pc = cpu->pc + 4;
+
+  /* Rounding mode.  */
+  int rm = (iw >> OP_SH_RM) & OP_MASK_RM;
+  int rounding = round_modes[rm];
+
+  sim_fpu sft, sft2;
+  sim_fpu sfa, sfb, sfc;
+  sim_fpu_64to (&sfa, cpu->fpregs[rs1].v[0]);
+  sim_fpu_64to (&sfb, cpu->fpregs[rs2].v[0]);
+
+  switch (op->match & mask_mul_add)
+    {
+    case MATCH_FMADD_D:
+      TRACE_INSN (cpu, "fmadd.d %s, %s, %s, %s",
+		  frd_name, frs1_name, frs2_name, frs3_name);
+      sim_fpu_64to (&sfc, cpu->fpregs[rs3].v[0]);
+      sim_fpu_mul (&sft2, &sfa, &sfb);
+      sim_fpu_add (&sft, &sfc, &sft2);
+      sim_fpu_round_64 (&sft, rounding, sim_fpu_denorm_default);
+      sim_fpu_to64 (&cpu->fpregs[rd].v[0], &sft);
+      goto done;
+    case MATCH_FMSUB_D:
+      TRACE_INSN (cpu, "fmsub.d %s, %s, %s, %s",
+		  frd_name, frs1_name, frs2_name, frs3_name);
+      sim_fpu_64to (&sfc, cpu->fpregs[rs3].v[0]);
+      sim_fpu_mul (&sft2, &sfa, &sfb);
+      sim_fpu_sub (&sft, &sft2, &sfc);
+      sim_fpu_round_64 (&sft, rounding, sim_fpu_denorm_default);
+      sim_fpu_to64 (&cpu->fpregs[rd].v[0], &sft);
+      goto done;
+    case MATCH_FNMADD_D:
+      TRACE_INSN (cpu, "fnmadd.d %s, %s, %s, %s",
+		  frd_name, frs1_name, frs2_name, frs3_name);
+      sim_fpu_64to (&sfc, cpu->fpregs[rs3].v[0]);
+      sim_fpu_mul (&sft2, &sfa, &sfb);
+      sim_fpu_add (&sft, &sfc, &sft2);
+      sim_fpu_neg (&sft, &sft);
+      sim_fpu_round_64 (&sft, rounding, sim_fpu_denorm_default);
+      sim_fpu_to64 (&cpu->fpregs[rd].v[0], &sft);
+      goto done;
+    case MATCH_FNMSUB_D:
+      TRACE_INSN (cpu, "fnmsub.d %s, %s, %s, %s",
+		  frd_name, frs1_name, frs2_name, frs3_name);
+      sim_fpu_64to (&sfc, cpu->fpregs[rs3].v[0]);
+      sim_fpu_mul (&sft2, &sfa, &sfb);
+      sim_fpu_sub (&sft, &sft2, &sfc);
+      sim_fpu_neg (&sft, &sft);
+      sim_fpu_round_64 (&sft, rounding, sim_fpu_denorm_default);
+      sim_fpu_to64 (&cpu->fpregs[rd].v[0], &sft);
+      goto done;
+    }
+
+  switch (op->match & mask_arithmetic)
+    {
+    case MATCH_FADD_D:
+      TRACE_INSN (cpu, "fadd.d %s, %s, %s",
+		  frd_name, frs1_name, frs2_name);
+      sim_fpu_add (&sft, &sfa, &sfb);
+      sim_fpu_round_64 (&sft, rounding, sim_fpu_denorm_default);
+      sim_fpu_to64 (&cpu->fpregs[rd].v[0], &sft);
+      goto done;
+    case MATCH_FSUB_D:
+      TRACE_INSN (cpu, "fsub.d %s, %s, %s",
+		  frd_name, frs1_name, frs2_name);
+      sim_fpu_sub (&sft, &sfa, &sfb);
+      sim_fpu_round_64 (&sft, rounding, sim_fpu_denorm_default);
+      sim_fpu_to64 (&cpu->fpregs[rd].v[0], &sft);
+      goto done;
+    case MATCH_FMUL_D:
+      TRACE_INSN (cpu, "fmul.d %s, %s, %s",
+		  frd_name, frs1_name, frs2_name);
+      sim_fpu_mul (&sft, &sfa, &sfb);
+      sim_fpu_round_64 (&sft, rounding, sim_fpu_denorm_default);
+      sim_fpu_to64 (&cpu->fpregs[rd].v[0], &sft);
+      goto done;
+    case MATCH_FDIV_D:
+      TRACE_INSN (cpu, "fdiv.d %s, %s, %s",
+		  frd_name, frs1_name, frs2_name);
+      sim_fpu_div (&sft, &sfa, &sfb);
+      sim_fpu_round_64 (&sft, rounding, sim_fpu_denorm_default);
+      sim_fpu_to64 (&cpu->fpregs[rd].v[0], &sft);
+      goto done;
+    case MATCH_FSQRT_D:
+      TRACE_INSN (cpu, "fsqrt.d %s, %s",
+		  frd_name, frs1_name);
+      sim_fpu_sqrt (&sft, &sfa);
+      sim_fpu_round_64 (&sft, rounding, sim_fpu_denorm_default);
+      sim_fpu_to64 (&cpu->fpregs[rd].v[0], &sft);
+      goto done;
+    }
+
+  switch (op->match & mask_convert)
+    {
+    case MATCH_FCVT_W_D:
+      TRACE_INSN (cpu, "fcvt.w.d %s, %s",
+		  rd_name, frs1_name);
+      sim_fpu_to32i (&i32, &sfa, rounding);
+      cpu->regs[rd] = i32;
+      goto done;
+    case MATCH_FCVT_WU_D:
+      TRACE_INSN (cpu, "fcvt.wu.d %s, %s",
+		  rd_name, frs1_name);
+      sim_fpu_to32u (&u32, &sfa, rounding);
+      i32 = u32;
+      cpu->regs[rd] = i32;
+      goto done;
+    case MATCH_FCVT_D_W:
+      TRACE_INSN (cpu, "fcvt.d.w %s, %s",
+		  frd_name, rs1_name);
+      sim_fpu_i32to (&sft, cpu->regs[rs1], rounding);
+      sim_fpu_to64 ((unsigned64 *) (cpu->fpregs + rd), &sft);
+      goto done;
+    case MATCH_FCVT_D_WU:
+      TRACE_INSN (cpu, "fcvt.d.wu %s, %s",
+		  frd_name, rs1_name);
+      sim_fpu_u32to (&sft, cpu->regs[rs1], rounding);
+      sim_fpu_to64 ((unsigned64 *) (cpu->fpregs + rd), &sft);
+      goto done;
+    case MATCH_FCVT_S_D:
+      TRACE_INSN (cpu, "fcvt.s.d %s, %s",
+		  frd_name, frs1_name);
+      sft = sfa;
+      sim_fpu_round_32 (&sft, sim_fpu_round_near, sim_fpu_denorm_default);
+      sim_fpu_to32 ((unsigned32 *) (cpu -> fpregs + rd), &sft);
+      goto done;
+    case MATCH_FCVT_D_S:
+      TRACE_INSN (cpu, "fcvt.d.s %s, %s",
+		  frd_name, frs1_name);
+      sim_fpu_32to (&sft, cpu->fpregs[rs1].w[0]);
+      sim_fpu_to64 (&cpu->fpregs[rd].v[0], &sft);
+      goto done;
+    case MATCH_FCVT_L_D:
+      TRACE_INSN (cpu, "fcvt.l.d %s, %s",
+		  rd_name, frs1_name);
+      cpu->regs[rd] = (int64_t) cpu->fpregs[rs1].D[0];
+      goto done;
+    case MATCH_FCVT_LU_D:
+      TRACE_INSN (cpu, "fcvt.lu.d %s, %s",
+		  rd_name, frs1_name);
+      cpu->regs[rd] = (uint64_t) cpu->fpregs[rs1].D[0];
+      goto done;
+    case MATCH_FCVT_D_L:
+      TRACE_INSN (cpu, "fcvt.d.l %s, %s",
+		  frd_name, rs1_name);
+      cpu->fpregs[rd].D[0] = (double) ((int64_t) cpu->regs[rs1]);
+      goto done;
+    case MATCH_FCVT_D_LU:
+      TRACE_INSN (cpu, "fcvt.d.lu %s, %s",
+		  frd_name, rs1_name);
+      cpu->fpregs[rd].D[0] = (double) cpu->regs[rs1];
+      goto done;
+    }
+
+  switch (op->match)
+    {
+    case MATCH_FLD:
+      TRACE_INSN (cpu, "fld %s, %" PRIiTW "(%s)",
+		  frd_name, i_imm, rs1_name);
+      store_frd64 (cpu, rd,
+	sim_core_read_unaligned_8 (cpu, cpu->pc, read_map,
+				   cpu->regs[rs1] + i_imm));
+      break;
+    case MATCH_FSD:
+      TRACE_INSN (cpu, "fsd %s, %" PRIiTW "(%s)",
+		  frs2_name, s_imm, rs1_name);
+      sim_core_write_unaligned_8 (cpu, cpu->pc, write_map,
+				  cpu->regs[rs1] + s_imm,
+				  cpu->fpregs[rs2].v[0]);
+      break;
+    case MATCH_FSGNJ_D:
+      TRACE_INSN (cpu, "fsgnj.d %s, %s, %s",
+		  frd_name, frs1_name, frs2_name);
+      u32 = cpu->fpregs[rs1].w[1] & 0x7fffffff;
+      u32 |= cpu->fpregs[rs2].w[1] & 0x80000000;
+      cpu->fpregs[rd].w[1] = u32;
+      cpu->fpregs[rd].w[0] = cpu->fpregs[rs1].w[0];
+      break;
+    case MATCH_FSGNJN_D:
+      TRACE_INSN (cpu, "fsgnjn.d %s, %s, %s",
+		  frd_name, frs1_name, frs2_name);
+      u32 = cpu->fpregs[rs1].w[1] & 0x7fffffff;
+      u32 |= (cpu->fpregs[rs2].w[1] & 0x80000000) ^ 0x80000000;
+      cpu->fpregs[rd].w[1] = u32;
+      cpu->fpregs[rd].w[0] = cpu->fpregs[rs1].w[0];
+      break;
+    case MATCH_FSGNJX_D:
+      TRACE_INSN (cpu, "fsgnjx.d %s, %s, %s",
+		  frd_name, frs1_name, frs2_name);
+      u32 = cpu->fpregs[rs1].w[1] & 0x7fffffff;
+      u32 |= (cpu->fpregs[rs1].w[1] & 0x80000000) ^ (cpu->fpregs[rs2].w[1] & 0x80000000);
+      cpu->fpregs[rd].w[1] = u32;
+      cpu->fpregs[rd].w[0] = cpu->fpregs[rs1].w[0];
+      break;
+    case MATCH_FMIN_D:
+      TRACE_INSN (cpu, "fmin.d %s, %s, %s",
+		  frd_name, frs1_name, frs2_name);
+      if (cpu->fpregs[rs1].D[0] < cpu->fpregs[rs2].D[0])
+	cpu->fpregs[rd].D[0] = cpu->fpregs[rs1].D[0];
+      else
+	cpu->fpregs[rd].D[0] = cpu->fpregs[rs2].D[0];
+      break;
+    case MATCH_FMAX_D:
+      TRACE_INSN (cpu, "fmax.d %s, %s, %s",
+		  frd_name, frs1_name, frs2_name);
+      if (cpu->fpregs[rs1].D[0] > cpu->fpregs[rs2].D[0])
+	cpu->fpregs[rd].D[0] = cpu->fpregs[rs1].D[0];
+      else
+	cpu->fpregs[rd].D[0] = cpu->fpregs[rs2].D[0];
+      break;
+    case MATCH_FMV_X_D:
+      TRACE_INSN (cpu, "fmv.x.d %s, %s",
+		  rd_name, frs1_name);
+      cpu->regs[rd] = cpu->fpregs[rs1].v[0];
+      break;
+    case MATCH_FMV_D_X:
+      TRACE_INSN (cpu, "fmv.d.x %s, %s",
+		  frd_name, frs1_name);
+      cpu->fpregs[rd].v[0] = cpu->regs[rs1];
+      break;
+    case MATCH_FEQ_D:
+      TRACE_INSN (cpu, "feq.d %s, %s, %s",
+		  rd_name, frs1_name, frs2_name);
+      cpu->regs[rd] = sim_fpu_is_eq (&sfa, &sfb);
+      break;
+    case MATCH_FLE_D:
+      TRACE_INSN (cpu, "fle.d %s, %s, %s",
+		  rd_name, frs1_name, frs2_name);
+      cpu->regs[rd] = sim_fpu_is_le (&sfa, &sfb);
+      break;
+    case MATCH_FLT_D:
+      TRACE_INSN (cpu, "flt.d %s, %s, %s",
+		  rd_name, frs1_name, frs2_name);
+      cpu->regs[rd] = sim_fpu_is_lt (&sfa, &sfb);
+      break;
+    case MATCH_FCLASS_D:
+      TRACE_INSN (cpu, "fclass.d %s, %s",
+		  rd_name, frs1_name);
+      switch (sim_fpu_is (&sfa))
+	{
+	case SIM_FPU_IS_NINF:
+	  cpu->regs[rd] = 1;
+	  break;
+	case SIM_FPU_IS_NNUMBER:
+	  cpu->regs[rd] = 1 << 1;
+	  break;
+	case SIM_FPU_IS_NDENORM:
+	  cpu->regs[rd] = 1 << 2;
+	  break;
+	case SIM_FPU_IS_NZERO:
+	  cpu->regs[rd] = 1 << 3;
+	  break;
+	case SIM_FPU_IS_PZERO:
+	  cpu->regs[rd] = 1 << 4;
+	  break;
+	case SIM_FPU_IS_PDENORM:
+	  cpu->regs[rd] = 1 << 5;
+	  break;
+	case SIM_FPU_IS_PNUMBER:
+	  cpu->regs[rd] = 1 << 6;
+	  break;
+	case SIM_FPU_IS_PINF:
+	  cpu->regs[rd] = 1 << 7;
+	  break;
+	case SIM_FPU_IS_SNAN:
+	  cpu->regs[rd] = 1 << 8;
+	  break;
+	case SIM_FPU_IS_QNAN:
+	  cpu->regs[rd] = 1 << 9;
+	  break;
+	}
+      break;
+    default:
+      TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
+      sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
+    }
+
+ done:
+  return pc;
+
+}
+
+static sim_cia
+execute_f (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
+{
+  SIM_DESC sd = CPU_STATE (cpu);
+  unsigned int mask_arithmetic = MASK_FADD_S;
+  unsigned int mask_mul_add = MASK_FMADD_S;
+  unsigned int mask_convert = MASK_FCVT_S_W;
+
+  static const int round_modes[] =
+  {
+      sim_fpu_round_near, sim_fpu_round_zero,
+      sim_fpu_round_down, sim_fpu_round_up,
+      sim_fpu_round_default, sim_fpu_round_default,
+      sim_fpu_round_default
+  };
+
+  int rd = (iw >> OP_SH_RD) & OP_MASK_RD;
+  int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1;
+  int rs2 = (iw >> OP_SH_RS2) & OP_MASK_RS2;
+  int rs3 = (iw >> OP_SH_RS3) & OP_MASK_RS3;
+  const char *frd_name = riscv_fpr_names_abi[rd];
+  const char *frs1_name = riscv_fpr_names_abi[rs1];
+  const char *frs2_name = riscv_fpr_names_abi[rs2];
+  const char *frs3_name = riscv_fpr_names_abi[rs3];
+  const char *rd_name = riscv_gpr_names_abi[rd];
+  const char *rs1_name = riscv_gpr_names_abi[rs1];
+  unsigned_word i_imm = EXTRACT_ITYPE_IMM (iw);
+  unsigned_word s_imm = EXTRACT_STYPE_IMM (iw);
+  uint32_t u32;
+  int32_t i32;
+  int64_t i64;
+  uint64_t u64;
+  sim_cia pc = cpu->pc + 4;
+
+  /* Rounding mode.  */
+  int rm = (iw >> OP_SH_RM) & OP_MASK_RM;
+  int rounding = round_modes[rm];
+
+  sim_fpu sft, sft2;
+  sim_fpu sfa, sfb, sfc;
+  sim_fpu_32to (&sfa, cpu->fpregs[rs1].w[0]);
+  sim_fpu_32to (&sfb, cpu->fpregs[rs2].w[0]);
+
+  switch (op->match & mask_mul_add)
+    {
+    case MATCH_FMADD_S:
+      TRACE_INSN (cpu, "fmadd.s %s, %s, %s, %s",
+		  frd_name, frs1_name, frs2_name, frs3_name);
+      sim_fpu_32to (&sfc, cpu->fpregs[rs3].w[0]);
+      sim_fpu_mul (&sft2, &sfa, &sfb);
+      sim_fpu_add (&sft, &sfc, &sft2);
+      sim_fpu_round_32 (&sft, rounding, sim_fpu_denorm_default);
+      sim_fpu_to32 (&cpu->fpregs[rd].w[0], &sft);
+      goto done;
+    case MATCH_FMSUB_S:
+      TRACE_INSN (cpu, "fmsub.s %s, %s, %s, %s",
+		  frd_name, frs1_name, frs2_name, frs3_name);
+      sim_fpu_32to (&sfc, cpu->fpregs[rs3].w[0]);
+      sim_fpu_mul (&sft2, &sfa, &sfb);
+      sim_fpu_sub (&sft, &sft2, &sfc);
+      sim_fpu_round_32 (&sft, rounding, sim_fpu_denorm_default);
+      sim_fpu_to32 (&cpu->fpregs[rd].w[0], &sft);
+      goto done;
+    case MATCH_FNMADD_S:
+      TRACE_INSN (cpu, "fnmadd.s %s, %s, %s, %s",
+		  frd_name, frs1_name, frs2_name, frs3_name);
+      sim_fpu_32to (&sfc, cpu->fpregs[rs3].w[0]);
+      sim_fpu_mul (&sft2, &sfa, &sfb);
+      sim_fpu_add (&sft, &sfc, &sft2);
+      sim_fpu_neg (&sft, &sft);
+      sim_fpu_round_32 (&sft, rounding, sim_fpu_denorm_default);
+      sim_fpu_to32 (&cpu->fpregs[rd].w[0], &sft);
+      goto done;
+    case MATCH_FNMSUB_S:
+      TRACE_INSN (cpu, "fnmsub.s %s, %s, %s, %s",
+		  frd_name, frs1_name, frs2_name, frs3_name);
+      sim_fpu_32to (&sfc, cpu->fpregs[rs3].w[0]);
+      sim_fpu_mul (&sft2, &sfa, &sfb);
+      sim_fpu_sub (&sft, &sft2, &sfc);
+      sim_fpu_neg (&sft, &sft);
+      sim_fpu_round_32 (&sft, rounding, sim_fpu_denorm_default);
+      sim_fpu_to32 (&cpu->fpregs[rd].w[0], &sft);
+      goto done;
+    }
+
+  switch (op->match & mask_arithmetic)
+    {
+    case MATCH_FADD_S:
+      TRACE_INSN (cpu, "fadd.s %s, %s, %s",
+		  frd_name, frs1_name, frs2_name);
+      sim_fpu_add (&sft, &sfa, &sfb);
+      sim_fpu_round_32 (&sft, rounding, sim_fpu_denorm_default);
+      sim_fpu_to32 (&cpu->fpregs[rd].w[0], &sft);
+      goto done;
+    case MATCH_FSUB_S:
+      TRACE_INSN (cpu, "fsub.s %s, %s, %s",
+		  frd_name, frs1_name, frs2_name);
+      sim_fpu_sub (&sft, &sfa, &sfb);
+      sim_fpu_round_32 (&sft, rounding, sim_fpu_denorm_default);
+      sim_fpu_to32 (&cpu->fpregs[rd].w[0], &sft);
+      goto done;
+    case MATCH_FMUL_S:
+      TRACE_INSN (cpu, "fmul.s %s, %s, %s",
+		  frd_name, frs1_name, frs2_name);
+      sim_fpu_mul (&sft, &sfa, &sfb);
+      sim_fpu_round_64 (&sft, rounding, sim_fpu_denorm_default);
+      sim_fpu_round_32 (&sft, rounding, sim_fpu_denorm_default);
+      sim_fpu_to32 (&cpu->fpregs[rd].w[0], &sft);
+      goto done;
+    case MATCH_FDIV_S:
+      TRACE_INSN (cpu, "fdiv.s %s, %s, %s",
+		  frd_name, frs1_name, frs2_name);
+      sim_fpu_div (&sft, &sfa, &sfb);
+      sim_fpu_round_32 (&sft, rounding, sim_fpu_denorm_default);
+      sim_fpu_to32 (&cpu->fpregs[rd].w[0], &sft);
+      goto done;
+    case MATCH_FSQRT_S:
+      TRACE_INSN (cpu, "fsqrt.s %s, %s, %s",
+		  frd_name, frs1_name, frs2_name);
+      sim_fpu_sqrt (&sft, &sfa);
+      sim_fpu_to32 (&cpu->fpregs[rd].w[0], &sft);
+      goto done;
+    }
+
+  switch (op->match & mask_convert)
+    {
+    case MATCH_FCVT_W_S:
+      TRACE_INSN (cpu, "fcvt.w.s %s, %s",
+		  rd_name, frs1_name);
+      sim_fpu_to32i (&i32, &sfa, rounding);
+      cpu->regs[rd] = i32;
+      goto done;
+    case MATCH_FCVT_WU_S:
+      TRACE_INSN (cpu, "fcvt.wu.s %s, %s",
+		  rd_name, frs1_name);
+      sim_fpu_to32u (&u32, &sfa, rounding);
+      i32 = u32;
+      cpu->regs[rd] = i32;
+      goto done;
+    case MATCH_FCVT_S_W:
+      TRACE_INSN (cpu, "fcvt.s.w %s, %s",
+		  frd_name, rs1_name);
+      sim_fpu_i32to (&sft, cpu->regs[rs1], rounding);
+      sim_fpu_round_32 (&sft, rounding, sim_fpu_denorm_default);
+      sim_fpu_to32 ((unsigned32 *) (cpu->fpregs + rd), &sft);
+      goto done;
+    case MATCH_FCVT_S_WU:
+      TRACE_INSN (cpu, "fcvt.s.wu %s, %s",
+		  frd_name, rs1_name);
+      sim_fpu_u32to (&sft, cpu->regs[rs1], rounding);
+      sim_fpu_round_32 (&sft, rounding, sim_fpu_denorm_default);
+      sim_fpu_to32 ((unsigned32 *) (cpu->fpregs + rd), &sft);
+      goto done;
+    case MATCH_FCVT_L_S:
+      TRACE_INSN (cpu, "fcvt.l.s %s, %s",
+		  rd_name, frs1_name);
+      cpu->regs[rd] = (int64_t) cpu->fpregs[rs1].S[0];
+      goto done;
+    case MATCH_FCVT_LU_S:
+      TRACE_INSN (cpu, "fcvt.lu.s %s, %s",
+		  rd_name, frs1_name);
+      cpu->regs[rd] = (uint64_t) cpu->fpregs[rs1].S[0];
+      goto done;
+    case MATCH_FCVT_S_L:
+      TRACE_INSN (cpu, "fcvt.s.l %s, %s",
+		  frd_name, rs1_name);
+      cpu->fpregs[rd].S[0] = (float) ((int64_t) cpu->regs[rs1]);
+      goto done;
+    case MATCH_FCVT_S_LU:
+      TRACE_INSN (cpu, "fcvt.s.lu %s, %s",
+		  frd_name, rs1_name);
+      cpu->fpregs[rd].S[0] = (float) cpu->regs[rs1];
+      goto done;
+    }
+
+  switch (op->match)
+    {
+    case MATCH_FLW:
+      TRACE_INSN (cpu, "flw %s, %" PRIiTW "(%s)",
+		  frd_name, i_imm, rs1_name);
+      store_frd (cpu, rd, EXTEND32 (
+	sim_core_read_unaligned_4 (cpu, cpu->pc, read_map,
+				   cpu->regs[rs1] + i_imm)));
+      break;
+    case MATCH_FSW:
+      TRACE_INSN (cpu, "fsw %s, %" PRIiTW "(%s)",
+		  frs2_name, s_imm, rs1_name);
+      sim_core_write_unaligned_4 (cpu, cpu->pc, write_map,
+				  cpu->regs[rs1] + s_imm, cpu->fpregs[rs2].w[0]);
+      break;
+    case MATCH_FSGNJ_S:
+      TRACE_INSN (cpu, "fsgnj.s %s, %s, %s",
+		  frd_name, frs1_name, frs2_name);
+      u32 = cpu->fpregs[rs1].w[0] & 0x7fffffff;
+      u32 |= cpu->fpregs[rs2].w[0] & 0x80000000;
+      cpu->fpregs[rd].w[0] = u32;
+      break;
+    case MATCH_FSGNJN_S:
+      TRACE_INSN (cpu, "fsgnjn.s %s, %s, %s",
+		  frd_name, frs1_name, frs2_name);
+      u32 = cpu->fpregs[rs1].w[0] & 0x7fffffff;
+      u32 |= (cpu->fpregs[rs2].w[0] & 0x80000000) ^ 0x80000000;
+      cpu->fpregs[rd].w[0] = u32;
+      break;
+    case MATCH_FSGNJX_S:
+      TRACE_INSN (cpu, "fsgnx.s %s, %s, %s",
+		  frd_name, frs1_name, frs2_name);
+      u32 = cpu->fpregs[rs1].w[0] & 0x7fffffff;
+      u32 |= (cpu->fpregs[rs1].w[0] & 0x80000000) ^ (cpu->fpregs[rs2].w[0] & 0x80000000);
+      cpu->fpregs[rd].w[0] = u32;
+      break;
+    case MATCH_FMIN_S:
+      TRACE_INSN (cpu, "fmin.s %s, %s, %s",
+		  frd_name, frs1_name, frs2_name);
+      if (cpu->fpregs[rs1].S[0] < cpu->fpregs[rs2].S[0])
+	cpu->fpregs[rd].S[0] = cpu->fpregs[rs1].S[0];
+      else
+	cpu->fpregs[rd].S[0] = cpu->fpregs[rs2].S[0];
+      break;
+    case MATCH_FMAX_S:
+      TRACE_INSN (cpu, "fmax.s %s, %s, %s",
+		  frd_name, frs1_name, frs2_name);
+      if (cpu->fpregs[rs1].S[0] > cpu->fpregs[rs2].S[0])
+	cpu->fpregs[rd].S[0] = cpu->fpregs[rs1].S[0];
+      else
+	cpu->fpregs[rd].S[0] = cpu->fpregs[rs2].S[0];
+      break;
+    case MATCH_FMV_X_S:
+      TRACE_INSN (cpu, "fmv.x.s %s, %s",
+		  rd_name, frs1_name);
+      cpu->regs[rd] = cpu->fpregs[rs1].W[0];
+      break;
+    case MATCH_FMV_S_X:
+      TRACE_INSN (cpu, "fmv.s.x %s, %s",
+		  frd_name, rs1_name);
+      cpu->fpregs[rd].w[0] = cpu->regs[rs1];
+      break;
+    case MATCH_FEQ_S:
+      TRACE_INSN (cpu, "feq.s %s, %s, %s",
+		  rd_name, frs1_name, frs2_name);
+      cpu->regs[rd] = sim_fpu_is_eq (&sfa, &sfb);
+      break;
+    case MATCH_FLE_S:
+      TRACE_INSN (cpu, "fle.s %s, %s, %s",
+		  rd_name, frs1_name, frs2_name);
+      cpu->regs[rd] = sim_fpu_is_le (&sfa, &sfb);
+      break;
+    case MATCH_FLT_S:
+      TRACE_INSN (cpu, "flt.s %s, %s, %s",
+		  rd_name, frs1_name, frs2_name);
+      cpu->regs[rd] = sim_fpu_is_lt (&sfa, &sfb);
+      break;
+    case MATCH_FCLASS_S:
+      TRACE_INSN (cpu, "fclass.s %s, %s",
+		  rd_name, frs1_name);
+      switch (sim_fpu_is (&sfa))
+	{
+	case SIM_FPU_IS_NINF:
+	  cpu->regs[rd] = 1;
+	  break;
+	case SIM_FPU_IS_NNUMBER:
+	  cpu->regs[rd] = 1 << 1;
+	  break;
+	case SIM_FPU_IS_NDENORM:
+	  cpu->regs[rd] = 1 << 2;
+	  break;
+	case SIM_FPU_IS_NZERO:
+	  cpu->regs[rd] = 1 << 3;
+	  break;
+	case SIM_FPU_IS_PZERO:
+	  cpu->regs[rd] = 1 << 4;
+	  break;
+	case SIM_FPU_IS_PDENORM:
+	  cpu->regs[rd] = 1 << 5;
+	  break;
+	case SIM_FPU_IS_PNUMBER:
+	  cpu->regs[rd] = 1 << 6;
+	  break;
+	case SIM_FPU_IS_PINF:
+	  cpu->regs[rd] = 1 << 7;
+	  break;
+	case SIM_FPU_IS_SNAN:
+	  cpu->regs[rd] = 1 << 8;
+	  break;
+	case SIM_FPU_IS_QNAN:
+	  cpu->regs[rd] = 1 << 9;
+	  break;
+	}
+      break;
+    case MATCH_FRCSR:
+      TRACE_INSN (cpu, "frcsr %s",
+		  rd_name);
+      store_rd (cpu, rd, fetch_csr (cpu, "fcsr", CSR_FCSR, &cpu->csr.fcsr));
+      break;
+    case MATCH_FSCSR:
+      TRACE_INSN (cpu, "fscsr %s, %sf",
+		  rd_name, rs1_name);
+      store_rd (cpu, rd, fetch_csr (cpu, "fcsr", CSR_FCSR, &cpu->csr.fcsr));
+      store_csr (cpu, "fcsr", CSR_FCSR, &cpu->csr.fcsr, cpu->regs[rs1]);
+      break;
+    case MATCH_FRRM:
+      TRACE_INSN (cpu, "frrm %s",
+		  rd_name);
+      store_rd (cpu, rd, fetch_csr (cpu, "frm", CSR_FRM, &cpu->csr.frm));
+      break;
+    case MATCH_FSRM:
+      TRACE_INSN (cpu, "fsrm %s, %s",
+		  rd_name, rs1_name);
+      store_rd (cpu, rd, fetch_csr (cpu, "frm", CSR_FCSR, &cpu->csr.frm));
+      store_csr (cpu, "frm", CSR_FCSR, &cpu->csr.frm, cpu->regs[rs1]);
+      break;
+    case MATCH_FRFLAGS:
+      TRACE_INSN (cpu, "frflags %s",
+		  rd_name);
+      store_rd (cpu, rd, fetch_csr (cpu, "fflags", CSR_FFLAGS, &cpu->csr.fflags));
+      break;
+    case MATCH_FSFLAGS:
+      TRACE_INSN (cpu, "fsflags %s, %s",
+		  rd_name, frs1_name);
+      store_rd (cpu, rd, fetch_csr (cpu, "fflags", CSR_FFLAGS, &cpu->csr.fflags));
+      store_csr (cpu, "fflags", CSR_FFLAGS, &cpu->csr.fflags, cpu->regs[rs1]);
+      break;
+    default:
+      TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
+      sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
+    }
+
+ done:
+  return pc;
+}
+
+static sim_cia
 execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 {
   SIM_DESC sd = CPU_STATE (cpu);
@@ -960,6 +1618,10 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
       return execute_i (cpu, iw, op);
     case INSN_CLASS_M:
       return execute_m (cpu, iw, op);
+    case INSN_CLASS_D:
+      return execute_d (cpu, iw, op);
+    case INSN_CLASS_F:
+      return execute_f (cpu, iw, op);
     case INSN_CLASS_ZIFENCEI:
       return execute_zifencei (cpu, iw, op);
     default:
diff --git a/sim/riscv/sim-main.h b/sim/riscv/sim-main.h
index 4a1b31e..e53794f 100644
--- a/sim/riscv/sim-main.h
+++ b/sim/riscv/sim-main.h
@@ -25,6 +25,19 @@
 #include "machs.h"
 #include "sim-base.h"
 
+typedef union FRegisterValue
+{
+  uint64_t     v[2];
+  uint32_t     w[4];
+
+  int64_t      V[2];
+  int32_t      W[4];
+
+  float        S[4];
+  double       D[2];
+
+} FRegister;
+
 struct _sim_cpu {
   union {
     unsigned_word regs[32];
@@ -39,7 +52,7 @@ struct _sim_cpu {
     };
   };
   union {
-    unsigned_word fpregs[32];
+    FRegister fpregs[32];
     struct {
       /* These are the ABI names.  */
       unsigned_word ft0, ft1, ft2, ft3, ft4, ft5, ft6, ft7;
-- 
2.7.4

Re: [PATCH 06/24] RISC-V: Add fp support.

[Mike Frysinger]

On 17 Apr 2021 10:58, Jim Wilson wrote:
> Add F and D instruction support.

substance looks fine, just style nits

tests ?

> +execute_d (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
> +{
> ...
> +  static const int round_modes[] =
> +  {
> +      sim_fpu_round_near, sim_fpu_round_zero,
> +      sim_fpu_round_down, sim_fpu_round_up,
> +      sim_fpu_round_default, sim_fpu_round_default,
> +      sim_fpu_round_default
> +  };

hanging indent should be 2 spaces, not 4

> +      u32 |= (cpu->fpregs[rs1].w[1] & 0x80000000) ^ (cpu->fpregs[rs2].w[1] & 0x80000000);

line is too long -- wrap to 80 cols.  i didn't check every line ... this one
just stood out.  so please give it a double check.

> +      switch (sim_fpu_is (&sfa))
> +	{
> +	case SIM_FPU_IS_NINF:
> +	  cpu->regs[rd] = 1;
> +	  break;
> +	case SIM_FPU_IS_NNUMBER:
> +	  cpu->regs[rd] = 1 << 1;

i'm a little surprised all these bits don't have constants for them.  but i
guess binutils wouldn't normally have broken out the FPU state into headers ?

> +static sim_cia
> +execute_f (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
> +{
> ...
> +  static const int round_modes[] =
> +  {
> +      sim_fpu_round_near, sim_fpu_round_zero,
> +      sim_fpu_round_down, sim_fpu_round_up,
> +      sim_fpu_round_default, sim_fpu_round_default,
> +      sim_fpu_round_default
> +  };

use 2 space hanging indent

> +    case MATCH_FCVT_L_S:
> +      TRACE_INSN (cpu, "fcvt.l.s %s, %s",
> +		  rd_name, frs1_name);
> +      cpu->regs[rd] = (int64_t) cpu->fpregs[rs1].S[0];
> +      goto done;
> +    case MATCH_FCVT_LU_S:
> +      TRACE_INSN (cpu, "fcvt.lu.s %s, %s",
> +		  rd_name, frs1_name);
> +      cpu->regs[rd] = (uint64_t) cpu->fpregs[rs1].S[0];
> +      goto done;
> +    case MATCH_FCVT_S_L:
> +      TRACE_INSN (cpu, "fcvt.s.l %s, %s",
> +		  frd_name, rs1_name);
> +      cpu->fpregs[rd].S[0] = (float) ((int64_t) cpu->regs[rs1]);
> +      goto done;
> +    case MATCH_FCVT_S_LU:
> +      TRACE_INSN (cpu, "fcvt.s.lu %s, %s",
> +		  frd_name, rs1_name);
> +      cpu->fpregs[rd].S[0] = (float) cpu->regs[rs1];

these raw casts all feel ... wrong.  are the semantics guaranteed to match
between whatever the host CPU is (e.g. x86_64) and the target (e.g. riscv) ?
or it just seems to mostly work so we aren't going to squint too hard at it ?

> --- a/sim/riscv/sim-main.h
> +++ b/sim/riscv/sim-main.h
>  
> +typedef union FRegisterValue
> +{
> +  uint64_t     v[2];
> +  uint32_t     w[4];
> +
> +  int64_t      V[2];
> +  int32_t      W[4];
> +
> +  float        S[4];
> +  double       D[2];
> +
> +} FRegister;

trim that trailing blank line
-mike

Re: [PATCH 06/24] RISC-V: Add fp support.

[Jim Wilson]

On Sun, Apr 18, 2021 at 9:08 PM Mike Frysinger <vapier@gentoo.org> wrote:

> On 17 Apr 2021 10:58, Jim Wilson wrote:
> > Add F and D instruction support.
>
> substance looks fine, just style nits
>

I fixed the formatting issues.

tests ?
>

These are fairly well tested by the gcc testsuite.  Sim tests would be good
also, but I would prefer to handle that with a follow up patch when I have
time to write the tests, or manage to find someone to write the tests for
me.

> > +      switch (sim_fpu_is (&sfa))
> > +     {
> > +     case SIM_FPU_IS_NINF:
> > +       cpu->regs[rd] = 1;
> > +       break;
> > +     case SIM_FPU_IS_NNUMBER:
> > +       cpu->regs[rd] = 1 << 1;
>
> i'm a little surprised all these bits don't have constants for them.  but i
> guess binutils wouldn't normally have broken out the FPU state into
> headers ?
>

newlib and glibc have macros for them, which of course are named
differently as no one ever thought about that, but we can't easily use
either of those here, and the inconsistent naming could be a problem.
binutils has no need to name these bits.  There is no instruction that
takes these bits as input, so they never appear directly in the assembly
syntax.  Of course, names could potentially be useful for people writing
assembly code, but no one has asked for that yet, or volunteered to write
it yet.  We don't have an assembly language header file for people to
include that could include these constants.  We don't have a proper
assembly language manual either.

> > +    case MATCH_FCVT_L_S:
> > +      TRACE_INSN (cpu, "fcvt.l.s %s, %s",
> > +               rd_name, frs1_name);
> > +      cpu->regs[rd] = (int64_t) cpu->fpregs[rs1].S[0];
> > +      goto done;
> > +    case MATCH_FCVT_LU_S:
> > +      TRACE_INSN (cpu, "fcvt.lu.s %s, %s",
> > +               rd_name, frs1_name);
> > +      cpu->regs[rd] = (uint64_t) cpu->fpregs[rs1].S[0];
> > +      goto done;
> > +    case MATCH_FCVT_S_L:
> > +      TRACE_INSN (cpu, "fcvt.s.l %s, %s",
> > +               frd_name, rs1_name);
> > +      cpu->fpregs[rd].S[0] = (float) ((int64_t) cpu->regs[rs1]);
> > +      goto done;
> > +    case MATCH_FCVT_S_LU:
> > +      TRACE_INSN (cpu, "fcvt.s.lu %s, %s",
> > +               frd_name, rs1_name);
> > +      cpu->fpregs[rd].S[0] = (float) cpu->regs[rs1];
>
> these raw casts all feel ... wrong.  are the semantics guaranteed to match
> between whatever the host CPU is (e.g. x86_64) and the target (e.g. riscv)
> ?
> or it just seems to mostly work so we aren't going to squint too hard at
> it ?
>

Yes, this is probably wrong.  The other FP math is probably also wrong.
RISC-V has canonical NaNs like ARM, but I don't see any obvious canonical
NaN support in common/sim-fpu.c.  I know that qemu handles this correctly.
RISC-V has NaN boxing for FP values smaller than the FP register size, i.e.
the upper bits must all be 1.  I don't see the code doing this, but this
would only matter for broken code so it is less important.  Qemu still got
this wrong last time I looked at it, but it has been a while since I looked
at the qemu code.

Maybe this stuff can be handled with a bug report and follow up patches?

Jim

[PATCH 07/24] RISC-V sim: Add link syscall support.

[Jim Wilson]

From: Kuan-Lin Chen <rufus@andestech.com>

Use callback routines to support more syscalls, add TARGET_SYS_link support.

	sim/riscv/
	* sim-main.c: Include unistd.h.
	(execute_i): In case MATCH_ECALL, Call cb_target_to_host_syscall
	and handle TARGET_sys_link.
---
 sim/riscv/sim-main.c | 37 ++++++++++++++++++++++++++++++++++++-
 1 file changed, 36 insertions(+), 1 deletion(-)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index de76089..03ba79b 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -25,6 +25,7 @@
 
 #include <inttypes.h>
 #include <time.h>
+#include <unistd.h>
 
 #include "sim-main.h"
 #include "sim-fpu.h"
@@ -1245,7 +1246,41 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
       break;
     case MATCH_ECALL:
       TRACE_INSN (cpu, "ecall;");
-      cpu->a0 = sim_syscall (cpu, cpu->a7, cpu->a0, cpu->a1, cpu->a2, cpu->a3);
+      if (cb_target_to_host_syscall (STATE_CALLBACK (sd), cpu->a7) == -1)
+	{
+	  host_callback *cb = STATE_CALLBACK (sd);
+	  CB_SYSCALL sc;
+
+	  CB_SYSCALL_INIT (&sc);
+
+	  sc.arg1 = cpu->a0;
+	  sc.arg2 = cpu->a1;
+	  sc.arg3 = cpu->a2;
+	  sc.arg4 = cpu->a3;
+	  sc.func = cpu->a7;
+
+	  sc.p1 = (PTR) sd;
+	  sc.p2 = (PTR) cpu;
+	  sc.read_mem = sim_syscall_read_mem;
+	  sc.write_mem = sim_syscall_write_mem;
+
+	  switch (cpu->a7)
+	    {
+	    case TARGET_SYS_link:
+	      {
+		char oldpath[1024], newpath[1024];
+		cb_get_string (cb, &sc, oldpath, sizeof (oldpath), sc.arg1);
+		cb_get_string (cb, &sc, newpath, sizeof (newpath), sc.arg2);
+		cpu->a0 = link (oldpath, newpath);
+		break;
+	      }
+	    default:
+	      cpu->a0 = -1;
+	      break;
+	    }
+	}
+      else
+	cpu->a0 = sim_syscall (cpu, cpu->a7, cpu->a0, cpu->a1, cpu->a2, cpu->a3);
       break;
     default:
       TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
-- 
2.7.4

Re: [PATCH 07/24] RISC-V sim: Add link syscall support.

[Mike Frysinger]

On 17 Apr 2021 10:58, Jim Wilson wrote:
> -      cpu->a0 = sim_syscall (cpu, cpu->a7, cpu->a0, cpu->a1, cpu->a2, cpu->a3);
> +      if (cb_target_to_host_syscall (STATE_CALLBACK (sd), cpu->a7) == -1)
> ...
> +	    case TARGET_SYS_link:

why not implement this in common/syscall.c so all ports can benefit ?
-mike

Re: [PATCH 07/24] RISC-V sim: Add link syscall support.

[Jim Wilson]

On Sun, Apr 18, 2021 at 9:09 PM Mike Frysinger <vapier@gentoo.org> wrote:

> On 17 Apr 2021 10:58, Jim Wilson wrote:
> > -      cpu->a0 = sim_syscall (cpu, cpu->a7, cpu->a0, cpu->a1, cpu->a2,
> cpu->a3);
> > +      if (cb_target_to_host_syscall (STATE_CALLBACK (sd), cpu->a7) ==
> -1)
> > ...
> > +         case TARGET_SYS_link:
>
> why not implement this in common/syscall.c so all ports can benefit ?
>

I don't know.  It isn't my patch.  Maybe they didn't want to touch generic
sim code?  That would have made the RISC-V changes messier.  Personally, I
think the link syscall is of limited value.  But moving it to
common/syscall.c sounds reasonable.  Maybe as a bug report and/or follow on
patch?

Jim

[PATCH 08/24] RISC-V sim: Add brk syscall.

[Jim Wilson]

From: Kuan-Lin Chen <rufus@andestech.com>

Add endbrk field to cpu struct.  Set it to highest section end address.
Use it for the brk syscall support.

	sim/riscv/
	* interp.c: Include libiberty.h, bfd.h, and elf-bfd.h.
	(sim_create_inferior): New locals phdr, i, phnum.  Use to
	calculate cpu->endbrk.
	* sim-main.c (execute_i): In case MATCH_ECALL, handle
	TARGET_SYS_brk.
	* sim-main.h (struct _sim_cpu): Add endbrk field.
---
 sim/riscv/interp.c   | 15 +++++++++++++++
 sim/riscv/sim-main.c |  9 +++++++++
 sim/riscv/sim-main.h |  1 +
 3 files changed, 25 insertions(+)

diff --git a/sim/riscv/interp.c b/sim/riscv/interp.c
index 1bf60a4..c98f6ab 100644
--- a/sim/riscv/interp.c
+++ b/sim/riscv/interp.c
@@ -20,6 +20,10 @@
 
 #include "config.h"
 
+#include "libiberty.h"
+#include "bfd.h"
+#include "elf-bfd.h"
+
 #include "sim-main.h"
 #include "sim-options.h"
 \f
@@ -129,6 +133,8 @@ sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
 {
   SIM_CPU *cpu = STATE_CPU (sd, 0);
   SIM_ADDR addr;
+  Elf_Internal_Phdr *phdr;
+  int i, phnum;
 
   /* Set the PC.  */
   if (abfd != NULL)
@@ -137,6 +143,15 @@ sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
     addr = 0;
   sim_pc_set (cpu, addr);
 
+  /* Set endbrk to highest section end address.  */
+  phdr = elf_tdata (abfd)->phdr;
+  phnum = elf_elfheader (abfd)->e_phnum;
+  for (i = 0; i < phnum; i++)
+    {
+      if (phdr[i].p_paddr + phdr[i].p_memsz > cpu->endbrk)
+	cpu->endbrk = phdr[i].p_paddr + phdr[i].p_memsz;
+    }
+
   /* Standalone mode (i.e. `run`) will take care of the argv for us in
      sim_open() -> sim_parse_args().  But in debug mode (i.e. 'target sim'
      with `gdb`), we need to handle it because the user can change the
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 03ba79b..597e9c3 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -1274,6 +1274,15 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 		cpu->a0 = link (oldpath, newpath);
 		break;
 	      }
+	    case TARGET_SYS_brk:
+	      {
+		/* FIXME: Check the invalid access.  */
+		if (cpu->a0 == 0)
+		  cpu->a0 = cpu->endbrk;
+		else
+		  cpu->endbrk = cpu->a0;
+		break;
+	      }
 	    default:
 	      cpu->a0 = -1;
 	      break;
diff --git a/sim/riscv/sim-main.h b/sim/riscv/sim-main.h
index e53794f..9206b94 100644
--- a/sim/riscv/sim-main.h
+++ b/sim/riscv/sim-main.h
@@ -63,6 +63,7 @@ struct _sim_cpu {
     };
   };
   sim_cia pc;
+  sim_cia endbrk;
 
   struct {
 #define DECLARE_CSR(name, ...) unsigned_word name;
-- 
2.7.4

Re: [PATCH 08/24] RISC-V sim: Add brk syscall.

[Mike Frysinger]

On 17 Apr 2021 10:58, Jim Wilson wrote:
> Add endbrk field to cpu struct.  Set it to highest section end address.
> Use it for the brk syscall support.
> ...
> +  /* Set endbrk to highest section end address.  */
> +  phdr = elf_tdata (abfd)->phdr;
> +  phnum = elf_elfheader (abfd)->e_phnum;

the commit message & comments say "sections", but the code isn't operating on
sections, it's operating on program headers which define "segments".  i know
it sounds like i'm being pedantic, but i've seen a lot of ELF parsers that get
confused and use/mix terminology, and it gets hard to untangle the intentions
with the actual code.  especially when digging through bug reports.
-mike

Re: [PATCH 08/24] RISC-V sim: Add brk syscall.

[Jim Wilson]

On Sun, Apr 18, 2021 at 10:24 PM Mike Frysinger <vapier@gentoo.org> wrote:

> On 17 Apr 2021 10:58, Jim Wilson wrote:
> > Add endbrk field to cpu struct.  Set it to highest section end address.
> > Use it for the brk syscall support.
> > ...
> > +  /* Set endbrk to highest section end address.  */
> > +  phdr = elf_tdata (abfd)->phdr;
> > +  phnum = elf_elfheader (abfd)->e_phnum;
>
> the commit message & comments say "sections", but the code isn't operating
> on
> sections, it's operating on program headers which define "segments".  i
> know
> it sounds like i'm being pedantic, but i've seen a lot of ELF parsers that
> get
> confused and use/mix terminology, and it gets hard to untangle the
> intentions
> with the actual code.  especially when digging through bug reports.
>

I fixed the commit message.  The comment gets rewritten in part 20.  I will
fix it there.

Jim

[PATCH 09/24] RISC-V sim: Fix syscall fallback.

[Jim Wilson]

From: Kito Cheng <kito.cheng@gmail.com>

Fall back to sim_syscall if we don't handle this syscall.

	sim/riscv/
	* sim-main.c (execute_i): In case MATCH_ECALL, make default case
	call sim_syscall.
---
 sim/riscv/sim-main.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 597e9c3..48cf27f 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -1284,7 +1284,8 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 		break;
 	      }
 	    default:
-	      cpu->a0 = -1;
+	      cpu->a0 = sim_syscall (cpu, cpu->a7, cpu->a0,
+				     cpu->a1, cpu->a2, cpu->a3);
 	      break;
 	    }
 	}
-- 
2.7.4

Re: [PATCH 09/24] RISC-V sim: Fix syscall fallback.

[Jim Wilson]

On Sat, Apr 17, 2021 at 10:59 AM Jim Wilson <jimw@sifive.com> wrote:

> From: Kito Cheng <kito.cheng@gmail.com>
>
> Fall back to sim_syscall if we don't handle this syscall.
>
>         sim/riscv/
>         * sim-main.c (execute_i): In case MATCH_ECALL, make default case
>         call sim_syscall.
> ---
>  sim/riscv/sim-main.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
> index 597e9c3..48cf27f 100644
> --- a/sim/riscv/sim-main.c
> +++ b/sim/riscv/sim-main.c
> @@ -1284,7 +1284,8 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const
> struct riscv_opcode *op)
>                 break;
>               }
>             default:
> -             cpu->a0 = -1;
> +             cpu->a0 = sim_syscall (cpu, cpu->a7, cpu->a0,
> +                                    cpu->a1, cpu->a2, cpu->a3);
>               break;
>             }
>         }
> --
> 2.7.4
>

This one is missing a review.

Jim

Re: [PATCH 09/24] RISC-V sim: Fix syscall fallback.

[Mike Frysinger]

On 21 Apr 2021 16:38, Jim Wilson wrote:
> This one is missing a review.

there's a lot to unpack in this series :).  i figured we'd merge the ones we
def agree on, then respin the series with the ones left.  it makes it a bit
easier to iterate when there's fewer things to look at all at once, both in
terms of scope, and in terms of patch count.

i'm hoping we can avoid forking the syscall handling logic by implementing all
the syscalls you want in the common code, thus this particular patch wouldn't
be necessary.  i'm not 100% confident we can get there, but i think it's worth
trying.
-mike

Re: [PATCH 09/24] RISC-V sim: Fix syscall fallback.

[Jim Wilson]

On Wed, Apr 21, 2021 at 8:24 PM Mike Frysinger <vapier@gentoo.org> wrote:

> i'm hoping we can avoid forking the syscall handling logic by implementing
> all
> the syscalls you want in the common code, thus this particular patch
> wouldn't
> be necessary.  i'm not 100% confident we can get there, but i think it's
> worth
> trying.
>

OK.  That sounds reasonable.

Jim

[PATCH 10/24] RISC-V sim: Fix ebreak.

[Jim Wilson]

From: Monk Chiang <monk@andestech.com>

Linux kernel no longer adds 4 to epc, and so gdb no longer subtracts 4,
so the simulator should no longer add 4 either.

	sim/riscv/
	* sim-main.c (execute_i): In case MATCH_SBREAK, don't increment
	pc in sim_engine_halt call.
---
 sim/riscv/sim-main.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 48cf27f..710b67d 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -1241,8 +1241,8 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
       break;
     case MATCH_SBREAK:
       TRACE_INSN (cpu, "sbreak;");
-      /* GDB expects us to step over SBREAK.  */
-      sim_engine_halt (sd, cpu, NULL, cpu->pc + 4, sim_stopped, SIM_SIGTRAP);
+      /* GDB expects us to stop at SBREAK.  */
+      sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_stopped, SIM_SIGTRAP);
       break;
     case MATCH_ECALL:
       TRACE_INSN (cpu, "ecall;");
-- 
2.7.4

Re: [PATCH 10/24] RISC-V sim: Fix ebreak.

[Mike Frysinger]

On 17 Apr 2021 10:58, Jim Wilson wrote:
> Linux kernel no longer adds 4 to epc, and so gdb no longer subtracts 4,
> so the simulator should no longer add 4 either.

lgtm, thanks
-mike

[PATCH 11/24] RISC-V sim: Fix ebreak, part 2.

[Jim Wilson]

Sbreak was renamed to ebreak a long time ago.  Fix the references.

	sim/riscv/
	* sim-main.c (execute_i): Rename MATCH_SBREAK to MATCH_EBREAK.
---
 sim/riscv/sim-main.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 710b67d..84f7cb86 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -1239,9 +1239,9 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
     case MATCH_FENCE:
       TRACE_INSN (cpu, "fence;");
       break;
-    case MATCH_SBREAK:
-      TRACE_INSN (cpu, "sbreak;");
-      /* GDB expects us to stop at SBREAK.  */
+    case MATCH_EBREAK:
+      TRACE_INSN (cpu, "ebreak;");
+      /* GDB expects us to stop at EBREAK.  */
       sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_stopped, SIM_SIGTRAP);
       break;
     case MATCH_ECALL:
-- 
2.7.4

Re: [PATCH 11/24] RISC-V sim: Fix ebreak, part 2.

[Mike Frysinger]

On 17 Apr 2021 10:58, Jim Wilson wrote:
> Sbreak was renamed to ebreak a long time ago.  Fix the references.

i'd fix the commit message to be meaningful, otherwise lgtm
-mike

Re: [PATCH 11/24] RISC-V sim: Fix ebreak, part 2.

[Jim Wilson]

On Sun, Apr 18, 2021 at 9:20 PM Mike Frysinger <vapier@gentoo.org> wrote:

> On 17 Apr 2021 10:58, Jim Wilson wrote:
> > Sbreak was renamed to ebreak a long time ago.  Fix the references.
>
> i'd fix the commit message to be meaningful, otherwise lgtm
>

I'm assuming it is the "Fix ebreak, part 2." that you didn't like.  So I
changed it to "Rename sbreak to ebreak."

Jim

[PATCH 12/24] RISC-V sim: Add compressed support.

[Jim Wilson]

From: Monk Chiang <monk@andestech.com>

Add C instruction support.

	sim/riscv/
	* sim-main.c (execute_c): New function.
	(execute_one): Call execute_c.
	(step_once): Handle len == 2.
---
 sim/riscv/sim-main.c | 484 +++++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 474 insertions(+), 10 deletions(-)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 84f7cb86..7262ac1 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -803,6 +803,475 @@ execute_f (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 }
 
 static sim_cia
+execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
+{
+  SIM_DESC sd = CPU_STATE (cpu);
+  const int mask_group_op = 0x3;
+  const int mask_mv_jr = 0xf003;
+  const int match_mv_jr = 0x8002;
+  const int mask_ebk_jalr_add = 0xf003;
+  const int match_ebk_jalr_add = 0x9002;
+
+  int rd = (iw >> OP_SH_RD) & OP_MASK_RD;
+  int crs2 = (iw >> OP_SH_CRS2) & OP_MASK_CRS2;
+  int crs1s = ((iw >> OP_SH_CRS1S) & OP_MASK_CRS1S) | 0x8;
+  int crs2s = ((iw >> OP_SH_CRS2S) & OP_MASK_CRS2S) | 0x8;
+  int ciw_rd = crs2s;
+  unsigned_word rvc_imm = EXTRACT_CITYPE_IMM (iw);
+  unsigned_word tmp;
+  sim_cia pc = cpu->pc + 2;
+
+  const char *rd_name = riscv_gpr_names_abi[rd];
+  const char *crs2_name = riscv_gpr_names_abi[crs2];
+  const char *crs1s_name = riscv_gpr_names_abi[crs1s];
+  const char *crs2s_name = riscv_gpr_names_abi[crs2s];
+  const char *ciw_rd_name = crs2s_name;
+
+  const char *frd_name = riscv_fpr_names_abi[rd];
+  const char *fcrs2_name = riscv_fpr_names_abi[crs2];
+  const char *fcrs1s_name = riscv_fpr_names_abi[crs1s];
+  const char *fcrs2s_name = riscv_fpr_names_abi[crs2s];
+  const char *fciw_rd_name = fcrs2s_name;
+
+  /* Deal with c.mv, c.jr instructons.  */
+  if ((op->match & mask_mv_jr) == match_mv_jr)
+    {
+      if (crs2 != 0)
+	{
+	  /* c.mv */
+	  TRACE_INSN (cpu, "c.mv %s, %s // %s = %s",
+		      rd_name, crs2_name, rd_name, crs2_name);
+	  cpu->regs[rd] = cpu->regs[crs2];
+	}
+      else
+	{
+	  /* c.jr */
+	  TRACE_INSN (cpu, "c.jr %s", rd_name);
+	  pc = cpu->regs[rd];
+	}
+      return pc;
+    }
+
+  /* Deal with c.ebreak, c.jalr, c.add instructions.  */
+  if ((op->match & mask_ebk_jalr_add) == match_ebk_jalr_add)
+    {
+      if (iw == MATCH_C_EBREAK)
+	{
+	  /* c.ebreak */
+	  TRACE_INSN (cpu, "c.break");
+	  sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_stopped, SIM_SIGTRAP);
+	}
+      else if (crs2 == 0)
+	{
+	  /* c.jalr */
+	  TRACE_INSN (cpu, "c.jalr %s", rd_name);
+	  pc = cpu->regs[rd];
+	  store_rd (cpu, X_RA, cpu->pc + 2);
+	}
+      else
+	{
+	  /* c.add */
+	  TRACE_INSN (cpu, "c.add %s, %s // %s += %s",
+		      rd_name, crs2_name, rd_name, crs2_name);
+	  store_rd (cpu, rd, cpu->regs[rd] + cpu->regs[crs2]);
+	}
+      return pc;
+    }
+
+  switch (op->match & mask_group_op)
+    {
+    case 0:
+      switch (op->match)
+	{
+	case MATCH_C_LW:
+	  TRACE_INSN (cpu, "c.lw %s, %" PRIiTW "(%s);"
+			   " // %s = *(%s + %" PRIiTW ")",
+		      crs2s_name, EXTRACT_CLTYPE_LW_IMM (iw), crs1s_name,
+		      crs2s_name, crs1s_name, EXTRACT_CLTYPE_LW_IMM (iw));
+	  store_rd (cpu, crs2s, EXTEND32 (
+	    sim_core_read_unaligned_4 (cpu, cpu->pc, read_map,
+				       cpu->regs[crs1s]
+				       + EXTRACT_CLTYPE_LW_IMM (iw))));
+	  return pc;
+	case MATCH_C_SW:
+	  TRACE_INSN (cpu, "c.sw %s, %" PRIiTW "(%s);"
+			   " // *(%s + %" PRIiTW ") = %s",
+		      crs2s_name, EXTRACT_CLTYPE_LW_IMM (iw), crs1s_name,
+		      crs1s_name, EXTRACT_CLTYPE_LW_IMM (iw), crs2s_name);
+	  sim_core_write_unaligned_4 (cpu, cpu->pc, write_map,
+				      (cpu->regs[crs1s]
+				       + EXTRACT_CLTYPE_LW_IMM (iw)),
+				      cpu->regs[crs2s]);
+	  return pc;
+	case MATCH_C_ADDI4SPN:
+	  TRACE_INSN (cpu, "c.addi4spn %s, %" PRIiTW
+			   " // %s = sp + %" PRIiTW,
+		      ciw_rd_name, EXTRACT_CIWTYPE_ADDI4SPN_IMM (iw),
+		      ciw_rd_name, EXTRACT_CIWTYPE_ADDI4SPN_IMM (iw));
+	  store_rd (cpu, ciw_rd, cpu->sp + EXTRACT_CIWTYPE_ADDI4SPN_IMM (iw));
+	  return pc;
+	case MATCH_C_FLD:
+	  if (RISCV_XLEN (cpu) <= 64)
+	    {
+	      TRACE_INSN (cpu, "c.fld %s, %" PRIiTW "(%s);"
+			       " // %s = *(%s + %" PRIiTW ")",
+			  fcrs2s_name, EXTRACT_CLTYPE_LD_IMM (iw), fcrs1s_name,
+			  fcrs2s_name, fcrs1s_name, EXTRACT_CLTYPE_LD_IMM (iw));
+	      /* rv32/64, c.fld instruction.  */
+	      store_frd64 (cpu, crs2s,
+		sim_core_read_unaligned_8 (cpu, cpu->pc, read_map,
+					   cpu->regs[crs1s]
+					   + EXTRACT_CLTYPE_LD_IMM (iw)));
+	      return pc;
+	    }
+	  else
+	    {
+	      /* rv128, c.lq instruction.  */
+	      TRACE_INSN (cpu, "UNHANDLED RV128 INSN: %s", op->name);
+	      sim_engine_halt (sd, cpu, NULL, cpu->pc,
+			       sim_signalled, SIM_SIGILL);
+	    }
+	case MATCH_C_FLW:
+	  /* rv32: c.flw, rv64: c.ld.  */
+	  if (RISCV_XLEN (cpu) == 32)
+	    {
+	      TRACE_INSN (cpu, "c.flw %s, %" PRIiTW "(%s);"
+			       " // *(%s + %" PRIiTW ") = %s",
+			  fcrs2s_name, EXTRACT_CLTYPE_LW_IMM (iw), crs1s_name,
+			  crs1s_name, EXTRACT_CLTYPE_LW_IMM (iw), fcrs2s_name);
+	      store_frd (cpu, crs2s, EXTEND32 (
+		sim_core_read_unaligned_4 (cpu, cpu->pc, read_map,
+					   cpu->regs[crs1s]
+					   + EXTRACT_CLTYPE_LW_IMM (iw))));
+	    }
+	  else
+	    {
+	      TRACE_INSN (cpu, "c.ld %s, %" PRIiTW "(%s);"
+			       " // *(%s + %" PRIiTW ") = %s",
+			  crs2s_name, EXTRACT_CLTYPE_LD_IMM (iw), crs1s_name,
+			  crs1s_name, EXTRACT_CLTYPE_LD_IMM (iw), crs2s_name);
+	      store_rd (cpu, crs2s,
+		sim_core_read_unaligned_8 (cpu, cpu->pc, read_map,
+					   cpu->regs[crs1s]
+					   + EXTRACT_CLTYPE_LD_IMM (iw)));
+	    }
+	  return pc;
+	case MATCH_C_FSD:
+	  if (RISCV_XLEN (cpu) <= 64)
+	    {
+	      /* rv32/64, c.fsd instruction.  */
+	      TRACE_INSN (cpu, "c.fsd %s, %" PRIiTW "(%s);"
+			       " // *(%s + %" PRIiTW ") = %s",
+			  fcrs2s_name, EXTRACT_CLTYPE_LD_IMM (iw), crs1s_name,
+			  crs1s_name, EXTRACT_CLTYPE_LD_IMM (iw), fcrs2s_name);
+	      sim_core_write_unaligned_8 (cpu, cpu->pc, write_map,
+					  cpu->regs[crs1s]
+					  + EXTRACT_CLTYPE_LD_IMM (iw),
+					  cpu->fpregs[crs2s].v[0]);
+	      return pc;
+	    }
+	  else
+	    {
+	      /* rv128, c.sq instruction.  */
+	      TRACE_INSN (cpu, "UNHANDLED RV128 INSN: %s", op->name);
+	      sim_engine_halt (sd, cpu, NULL, cpu->pc,
+			       sim_signalled, SIM_SIGILL);
+	    }
+	case MATCH_C_FSW:
+	  /* rv32: c.fsw, rv64: c.sd.  */
+	  if (RISCV_XLEN (cpu) == 32)
+	    {
+	      TRACE_INSN (cpu, "c.fsw %s, %" PRIiTW "(%s);"
+			       " // *(%s + %" PRIiTW ") = %s",
+			  fcrs2s_name, EXTRACT_CLTYPE_LW_IMM (iw), crs1s_name,
+			  crs1s_name, EXTRACT_CLTYPE_LW_IMM (iw), fcrs2s_name);
+	      sim_core_write_unaligned_4 (cpu, cpu->pc, write_map,
+					  cpu->regs[crs1s]
+					  + EXTRACT_CLTYPE_LW_IMM (iw),
+					  cpu->fpregs[crs2s].w[0]);
+	    }
+	  else
+	    {
+	      TRACE_INSN (cpu, "c.sd %s, %" PRIiTW "(%s);"
+			       " // *(%s + %" PRIiTW ") = %s",
+			  crs2s_name, EXTRACT_CLTYPE_LD_IMM (iw), crs1s_name,
+			  crs1s_name, EXTRACT_CLTYPE_LD_IMM (iw), crs2s_name);
+	      sim_core_write_unaligned_8 (cpu, cpu->pc, write_map,
+					  cpu->regs[crs1s]
+					  + EXTRACT_CLTYPE_LD_IMM (iw),
+					  cpu->regs[crs2s]);
+	    }
+	  return pc;
+	default:
+	  TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
+	  sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
+	}
+    case 1:
+      switch (op->match)
+	{
+	case MATCH_C_ADDI:
+	  if (rd != 0)
+	    {
+	      /* c.addi */
+	      TRACE_INSN (cpu, "c.addi %s, %" PRIiTW " // %s += %" PRIiTW,
+			  rd_name, rvc_imm, rd_name, rvc_imm);
+	      store_rd (cpu, rd, cpu->regs[rd] + rvc_imm);
+	      return pc;
+	    }
+	  else
+	    {
+	      /* c.nop */
+	      TRACE_INSN (cpu, "c.nop");
+	      return pc;
+	    }
+	case MATCH_C_JAL:
+	  /* In rv32 is c.jal, rv64 c.addiw.  */
+	  if (RISCV_XLEN (cpu) == 32)
+	    {
+	      TRACE_INSN (cpu, "c.jal %" PRIiTW, EXTRACT_CJTYPE_IMM (iw));
+	      store_rd (cpu, X_RA, cpu->pc + 2);
+	      pc = cpu->pc + EXTRACT_CJTYPE_IMM (iw);
+	    }
+	  else
+	    {
+	      TRACE_INSN (cpu, "c.addiw %s, %" PRIiTW " // %s += %" PRIiTW,
+			  rd_name, rvc_imm, rd_name, rvc_imm);
+	      store_rd (cpu, rd, EXTEND32 (cpu->regs[rd] + rvc_imm));
+	    }
+	  return pc;
+	case MATCH_C_LI:
+	  TRACE_INSN (cpu, "c.li %s, %" PRIiTW " // %s = %" PRIiTW,
+		      rd_name, rvc_imm, rd_name, rvc_imm);
+	  store_rd (cpu, rd, rvc_imm);
+	  return pc;
+	case MATCH_C_ADDI16SP:
+	  TRACE_INSN (cpu, "c.addi16sp %s, %" PRIiTW,
+		      rd_name, rvc_imm);
+	  store_rd (cpu, rd, cpu->sp + EXTRACT_CITYPE_ADDI16SP_IMM (iw));
+	  return pc;
+	case MATCH_C_SRLI:
+	  /* rv32: c.srli, rv128: c.srli64.  */
+	  TRACE_INSN (cpu, "c.srli %s, %" PRIiTW,
+		      crs1s_name, EXTRACT_CITYPE_IMM (iw));
+	  if (RISCV_XLEN (cpu) == 32 && EXTRACT_CITYPE_IMM (iw) > 0x1f)
+	    sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
+	  store_rd (cpu, crs1s, cpu->regs[crs1s] >> EXTRACT_CITYPE_IMM (iw));
+	  return pc;
+	case MATCH_C_SRAI:
+	  /* rv32: c.srli, rv128: c.srli64.  */
+	  TRACE_INSN (cpu, "c.srai %s, %" PRIiTW,
+		      crs1s_name, EXTRACT_CITYPE_IMM (iw));
+	  if (RISCV_XLEN (cpu) == 32)
+	    {
+	      if (EXTRACT_CITYPE_IMM (iw) > 0x1f)
+		sim_engine_halt (sd, cpu, NULL, cpu->pc,
+				 sim_signalled, SIM_SIGILL);
+	      tmp = ashiftrt (cpu->regs[crs1s], EXTRACT_CITYPE_IMM (iw));
+	    }
+	  else
+	    tmp = ashiftrt64 (cpu->regs[crs1s], EXTRACT_CITYPE_IMM (iw));
+	  store_rd (cpu, crs1s, tmp);
+	  return pc;
+	case MATCH_C_ANDI:
+	  TRACE_INSN (cpu, "c.andi %s, %" PRIiTW,
+		      crs1s_name, EXTRACT_CITYPE_IMM (iw));
+	  store_rd (cpu, crs1s, cpu->regs[crs1s] & EXTRACT_CITYPE_IMM (iw));
+	  return pc;
+	case MATCH_C_SUB:
+	  TRACE_INSN (cpu, "c.sub %s, %s",
+		      crs1s_name, crs2s_name);
+	  store_rd (cpu, crs1s, cpu->regs[crs1s] - cpu->regs[crs2s]);
+	  return pc;
+	case MATCH_C_XOR:
+	  TRACE_INSN (cpu, "c.xor %s, %s",
+		      crs1s_name, crs2s_name);
+	  store_rd (cpu, crs1s, cpu->regs[crs1s] ^ cpu->regs[crs2s]);
+	  return pc;
+	case MATCH_C_OR:
+	  TRACE_INSN (cpu, "c.or %s, %s",
+		      crs1s_name, crs2s_name);
+	  store_rd (cpu, crs1s, cpu->regs[crs1s] | cpu->regs[crs2s]);
+	  return pc;
+	case MATCH_C_AND:
+	  TRACE_INSN (cpu, "c.and %s, %s",
+		      crs1s_name, crs2s_name);
+	  store_rd (cpu, crs1s, cpu->regs[crs1s] & cpu->regs[crs2s]);
+	  return pc;
+	case MATCH_C_SUBW:
+	  TRACE_INSN (cpu, "c.subw %s, %s",
+		      crs1s_name, crs2s_name);
+	  RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
+	  store_rd (cpu, crs1s, EXTEND32 (cpu->regs[crs1s] - cpu->regs[crs2s]));
+	  return pc;
+	case MATCH_C_ADDW:
+	  TRACE_INSN (cpu, "c.addw %s, %s",
+		      crs1s_name, crs2s_name);
+	  RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
+	  store_rd (cpu, crs1s, EXTEND32 (cpu->regs[crs1s] + cpu->regs[crs2s]));
+	  return pc;
+	case MATCH_C_BEQZ:
+	  TRACE_INSN (cpu, "c.beqz %s, %" PRIiTW,
+		      crs1s_name, cpu->pc + EXTRACT_CBTYPE_IMM (iw));
+	  if (cpu->regs[crs1s] == 0)
+	    pc = cpu->pc + EXTRACT_CBTYPE_IMM (iw);
+	  return pc;
+	case MATCH_C_BNEZ:
+	  TRACE_INSN (cpu, "c.bnez %s, %" PRIiTW,
+		      crs1s_name, cpu->pc + EXTRACT_CBTYPE_IMM (iw));
+	  if (cpu->regs[crs1s] != 0)
+	    pc = cpu->pc + EXTRACT_CBTYPE_IMM (iw);
+	  return pc;
+	case MATCH_C_LUI:
+	  TRACE_INSN (cpu, "c.lui %s, %" PRIiTW,
+		      rd_name, EXTRACT_CITYPE_LUI_IMM (iw));
+	  store_rd (cpu, rd, EXTRACT_CITYPE_LUI_IMM (iw));
+	  return pc;
+	case MATCH_C_J:
+	  TRACE_INSN (cpu, "c.j %" PRIiTW,
+		      cpu->pc + EXTRACT_CJTYPE_IMM (iw));
+	  pc = cpu->pc + EXTRACT_CJTYPE_IMM (iw);
+	  return pc;
+	default:
+	  TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
+	  sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
+	}
+    case 2:
+      switch (op->match)
+	{
+	case MATCH_C_SLLI:
+	  TRACE_INSN (cpu, "c.slli %s, %" PRIiTW,
+		      rd_name, rvc_imm);
+	  /* rv32: c.slli, rv128: c.slli64.  */
+	  if (RISCV_XLEN (cpu) == 32 && rvc_imm > 0x1f)
+	    sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
+	  store_rd (cpu, rd, cpu->regs[rd] << rvc_imm);
+	  return pc;
+	case MATCH_C_LWSP:
+	  TRACE_INSN (cpu, "c.lwsp %s, %" PRIiTW "(sp);"
+			   " // %s = *(sp + %" PRIiTW ")",
+		      rd_name, EXTRACT_CITYPE_LWSP_IMM (iw),
+		      rd_name, EXTRACT_CITYPE_LWSP_IMM (iw));
+	  store_rd (cpu, rd, EXTEND32 (
+	    sim_core_read_unaligned_4 (cpu, cpu->pc, read_map,
+				       cpu->sp
+				       + EXTRACT_CITYPE_LWSP_IMM (iw))));
+	  return pc;
+	case MATCH_C_SWSP:
+	  TRACE_INSN (cpu, "c.swsp %s, %" PRIiTW "(sp);"
+			   " // *(sp + %" PRIiTW ") = %s",
+		      rd_name, EXTRACT_CSSTYPE_SWSP_IMM (iw),
+		      EXTRACT_CSSTYPE_SWSP_IMM (iw), rd_name);
+	  sim_core_write_unaligned_4 (cpu, cpu->pc, write_map,
+				      (cpu->sp + EXTRACT_CSSTYPE_SWSP_IMM (iw)),
+				      cpu->regs[crs2]);
+	  return pc;
+	case MATCH_C_ADD:
+	  TRACE_INSN (cpu, "c.add %s, %s // %s += %s",
+		      rd_name, crs2_name,
+		      rd_name, crs2_name);
+	  store_rd (cpu, rd, cpu->regs[rd] + cpu->regs[crs2]);
+	  return pc;
+	case MATCH_C_FLDSP:
+	  /* rv32/64: c.fldsp, rv128: c.flqsp.  */
+	  if (RISCV_XLEN (cpu) <= 64)
+	    {
+	      TRACE_INSN (cpu, "c.fldsp %s, %" PRIiTW "(sp);"
+			       " // %s = *(sp + %" PRIiTW ")",
+			  frd_name, EXTRACT_CITYPE_LDSP_IMM (iw),
+			  frd_name, EXTRACT_CITYPE_LDSP_IMM (iw));
+	      store_frd64 (cpu, rd,
+		sim_core_read_unaligned_8 (cpu, cpu->pc, read_map,
+					   cpu->sp
+					   + EXTRACT_CITYPE_LDSP_IMM (iw)));
+	      return pc;
+	    }
+	  else
+	    {
+	      TRACE_INSN (cpu, "UNHANDLED RV128 INSN: %s", op->name);
+	      sim_engine_halt (sd, cpu, NULL, cpu->pc,
+			       sim_signalled, SIM_SIGILL);
+	    }
+	case MATCH_C_FLWSP:
+	  /* rv32: c.flwsp, rv64: c.ldsp.  */
+	  if (RISCV_XLEN (cpu) == 32)
+	    {
+	      TRACE_INSN (cpu, "c.flwsp %s, %" PRIiTW "(sp);"
+			       " // %s = *(sp + %" PRIiTW ")",
+			  frd_name, EXTRACT_CITYPE_LWSP_IMM (iw),
+			  frd_name, EXTRACT_CITYPE_LWSP_IMM (iw));
+	      store_frd (cpu, rd, EXTEND32 (
+		sim_core_read_unaligned_4 (cpu, cpu->pc, read_map,
+					   cpu->sp
+					   + EXTRACT_CITYPE_LWSP_IMM (iw))));
+	    }
+	  else
+	    {
+	      TRACE_INSN (cpu, "c.ldsp %s, %" PRIiTW "(sp);"
+			       " // %s = *(sp + %" PRIiTW ")",
+			  rd_name, EXTRACT_CITYPE_LDSP_IMM (iw),
+			  rd_name, EXTRACT_CITYPE_LDSP_IMM (iw));
+	      store_rd (cpu, rd,
+		sim_core_read_unaligned_8 (cpu, cpu->pc, read_map,
+					   cpu->sp
+					   + EXTRACT_CITYPE_LDSP_IMM (iw)));
+	    }
+	  return pc;
+	case MATCH_C_FSDSP:
+	  /* rv32/64: c.fsdsp, rv128: c.fsqsp.  */
+	  if (RISCV_XLEN (cpu) <= 64)
+	    {
+	      TRACE_INSN (cpu, "c.fsdsp %s, %" PRIiTW "(sp);"
+			       " // *(sp + %" PRIiTW ") = %s",
+			  fcrs2_name, EXTRACT_CSSTYPE_SDSP_IMM (iw),
+			  EXTRACT_CSSTYPE_SDSP_IMM (iw), fcrs2_name);
+	      sim_core_write_unaligned_8 (cpu, cpu->pc, write_map,
+					  cpu->sp + EXTRACT_CSSTYPE_SDSP_IMM (iw),
+					  cpu->fpregs[crs2].v[0]);
+	      return pc;
+	    }
+	  else
+	    {
+	      TRACE_INSN (cpu, "UNHANDLED RV128 INSN: %s", op->name);
+	      sim_engine_halt (sd, cpu, NULL, cpu->pc,
+			       sim_signalled, SIM_SIGILL);
+	    }
+	case MATCH_C_FSWSP:
+	  /* rv32: c.fswsp, rv64: c.sdsp.  */
+	  if (RISCV_XLEN (cpu) == 32)
+	    {
+	      TRACE_INSN (cpu, "c.fswsp %s, %" PRIiTW "(sp);"
+			       " // *(sp + %" PRIiTW ") = %s",
+			  fcrs2_name, EXTRACT_CSSTYPE_SWSP_IMM (iw),
+			  EXTRACT_CSSTYPE_SWSP_IMM (iw), fcrs2_name);
+	      sim_core_write_unaligned_4 (cpu, cpu->pc, write_map,
+					  cpu->sp
+					  + EXTRACT_CSSTYPE_SWSP_IMM (iw),
+					  cpu->fpregs[crs2].w[0]);
+	    }
+	  else
+	    {
+	      TRACE_INSN (cpu, "c.sdsp %s, %" PRIiTW "(sp);"
+			       " // *(sp + %" PRIiTW ") = %s",
+			  crs2_name, EXTRACT_CSSTYPE_SDSP_IMM (iw),
+			  EXTRACT_CSSTYPE_SDSP_IMM (iw), crs2_name);
+	      sim_core_write_unaligned_8 (cpu, cpu->pc, write_map,
+					  cpu->sp + EXTRACT_CSSTYPE_SDSP_IMM (iw),
+					  cpu->regs[crs2]);
+	    }
+	  return pc;
+	default:
+	  TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
+	  sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
+	}
+    default:
+      TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
+      sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
+    }
+
+  return pc;
+}
+
+static sim_cia
 execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 {
   SIM_DESC sd = CPU_STATE (cpu);
@@ -1667,6 +2136,8 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
       return execute_d (cpu, iw, op);
     case INSN_CLASS_F:
       return execute_f (cpu, iw, op);
+    case INSN_CLASS_C:
+      return execute_c (cpu, iw, op);
     case INSN_CLASS_ZIFENCEI:
       return execute_zifencei (cpu, iw, op);
     default:
@@ -1693,17 +2164,10 @@ void step_once (SIM_CPU *cpu)
 
   iw = sim_core_read_aligned_2 (cpu, pc, exec_map, pc);
 
-  /* Reject non-32-bit opcodes first.  */
   len = riscv_insn_length (iw);
-  if (len != 4)
-    {
-      sim_io_printf (sd, "sim: bad insn len %#x @ %#" PRIxTA ": %#" PRIxTW "\n",
-		     len, pc, iw);
-      sim_engine_halt (sd, cpu, NULL, pc, sim_signalled, SIM_SIGILL);
-    }
-
-  iw |= ((unsigned_word) sim_core_read_aligned_2 (
-    cpu, pc, exec_map, pc + 2) << 16);
+  if (len == 4)
+    iw |= ((unsigned_word)sim_core_read_aligned_2 (cpu, pc, exec_map, pc + 2)
+	   << 16);
 
   TRACE_CORE (cpu, "0x%08" PRIxTW, iw);
 
-- 
2.7.4

Re: [PATCH 12/24] RISC-V sim: Add compressed support.

[Mike Frysinger]

On 17 Apr 2021 10:58, Jim Wilson wrote:
> Add C instruction support.

lgtm other than missing tests
-mike

Re: [PATCH 12/24] RISC-V sim: Add compressed support.

[Jim Wilson]

On Sun, Apr 18, 2021 at 9:13 PM Mike Frysinger <vapier@gentoo.org> wrote:

> On 17 Apr 2021 10:58, Jim Wilson wrote:
> > Add C instruction support.
>
> lgtm other than missing tests
>

This is well tested by the gcc testsuite.  I'd rather handle missing tests
with bug reports and follow on patches.

Jim

[PATCH 13/24] RISC-V sim: Add gettimeofday.

[Jim Wilson]

From: Kuan-Lin Chen <rufus@andestech.com>

Handle TARGET_SYS_gettimeofday.

	sim/riscv/
	* sim-main.c: Include sys/time.h.
	(execute_i): In MATCH_ECALL case, handle TARGET_sys_gettimeofday.
---
 sim/riscv/sim-main.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 7262ac1..f330ef9 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -26,6 +26,7 @@
 #include <inttypes.h>
 #include <time.h>
 #include <unistd.h>
+#include <sys/time.h>
 
 #include "sim-main.h"
 #include "sim-fpu.h"
@@ -1752,6 +1753,32 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 		  cpu->endbrk = cpu->a0;
 		break;
 	      }
+	    case TARGET_SYS_gettimeofday:
+	      {
+		int rv;
+		struct timeval tv;
+
+		rv = gettimeofday (&tv, 0);
+		if (RISCV_XLEN (cpu) == 32)
+		  {
+		    sim_core_write_unaligned_4 (cpu, cpu->pc, write_map,
+						cpu->a0, tv.tv_sec);
+		    sim_core_write_unaligned_4 (cpu, cpu->pc, write_map,
+						cpu->a0 + 4,
+						tv.tv_usec);
+		  }
+		else
+		  {
+		    sim_core_write_unaligned_8 (cpu, cpu->pc, write_map,
+						cpu->a0, tv.tv_sec);
+		    sim_core_write_unaligned_8 (cpu, cpu->pc, write_map,
+						cpu->a0 + 8,
+						tv.tv_usec);
+		  }
+
+		cpu->a0 = rv;
+		break;
+	      }
 	    default:
 	      cpu->a0 = sim_syscall (cpu, cpu->a7, cpu->a0,
 				     cpu->a1, cpu->a2, cpu->a3);
-- 
2.7.4

Re: [PATCH 13/24] RISC-V sim: Add gettimeofday.

[Mike Frysinger]

On 17 Apr 2021 10:58, Jim Wilson wrote:
> +	    case TARGET_SYS_gettimeofday:
> +	      {
> +		int rv;
> +		struct timeval tv;
> +
> +		rv = gettimeofday (&tv, 0);
> +		if (RISCV_XLEN (cpu) == 32)
> +		  {
> +		    sim_core_write_unaligned_4 (cpu, cpu->pc, write_map,
> +						cpu->a0, tv.tv_sec);
> +		    sim_core_write_unaligned_4 (cpu, cpu->pc, write_map,
> +						cpu->a0 + 4,
> +						tv.tv_usec);
> +		  }
> +		else
> +		  {
> +		    sim_core_write_unaligned_8 (cpu, cpu->pc, write_map,
> +						cpu->a0, tv.tv_sec);
> +		    sim_core_write_unaligned_8 (cpu, cpu->pc, write_map,
> +						cpu->a0 + 8,
> +						tv.tv_usec);
> +		  }

this is incomplete/buggy.  if arg0==0, you'll write to the wrong place.
if arg1!=0, you leave the memory uninitialized.  if rv!=0, you write to
the arg0 struct.  see bfin/interp.c for a "full" implementation.

if we extended host_callback_struct to include a timeval_map, we would be
able to implement this in the common code and do so with full support for
everyone.
-mike

[PATCH 14/24] RISC-V sim: Add csrr*i instructions.

[Jim Wilson]

From: Kito Cheng <kito.cheng@gmail.com>

Implement csrrci, csrrsi, and csrrwi.

	sim/riscv/
	* sim-main.c (execute_i): Handle MATCH_CSRRCI, MATCH_CSRRSI,
	MATCH_CSRRWI.
---
 sim/riscv/sim-main.c | 41 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index f330ef9..42506a9 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -1647,6 +1647,20 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 #undef DECLARE_CSR
 	}
       break;
+    case MATCH_CSRRCI:
+      TRACE_INSN (cpu, "csrrci");
+      switch (csr)
+	{
+#define DECLARE_CSR(name, num, ...) \
+	case num: \
+	  store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
+	  store_csr (cpu, #name, num, &cpu->csr.name, \
+		     cpu->csr.name & !rs1); \
+	  break;
+#include "opcode/riscv-opc.h"
+#undef DECLARE_CSR
+	}
+      break;
     case MATCH_CSRRS:
       TRACE_INSN (cpu, "csrrs");
       switch (csr)
@@ -1661,6 +1675,20 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 #undef DECLARE_CSR
 	}
       break;
+    case MATCH_CSRRSI:
+      TRACE_INSN (cpu, "csrrsi");
+      switch (csr)
+	{
+#define DECLARE_CSR(name, num, ...) \
+	case num: \
+	  store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
+	  store_csr (cpu, #name, num, &cpu->csr.name, \
+		     cpu->csr.name | rs1); \
+	  break;
+#include "opcode/riscv-opc.h"
+#undef DECLARE_CSR
+	}
+      break;
     case MATCH_CSRRW:
       TRACE_INSN (cpu, "csrrw");
       switch (csr)
@@ -1674,6 +1702,19 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 #undef DECLARE_CSR
 	}
       break;
+    case MATCH_CSRRWI:
+      TRACE_INSN (cpu, "csrrwi");
+      switch (csr)
+	{
+#define DECLARE_CSR(name, num, ...) \
+	case num: \
+	  store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
+	  store_csr (cpu, #name, num, &cpu->csr.name, rs1); \
+	  break;
+#include "opcode/riscv-opc.h"
+#undef DECLARE_CSR
+	}
+      break;
 
     case MATCH_RDCYCLE:
       TRACE_INSN (cpu, "rdcycle %s;", rd_name);
-- 
2.7.4

Re: [PATCH 14/24] RISC-V sim: Add csrr*i instructions.

[Mike Frysinger]

On 17 Apr 2021 10:58, Jim Wilson wrote:
> Implement csrrci, csrrsi, and csrrwi.

lgtm, thanks
-mike

[PATCH 15/24] RISC-V sim: Improve cycle and instret counts.

[Jim Wilson]

From: Kito Cheng <kito.cheng@gmail.com>

Update cycleh and instreth in step_once.

	sim/riscv/
	* sim-main.c (step_once): For rv32, handle cycle and instret
	overflow into cycleh and instreth.
---
 sim/riscv/sim-main.c | 20 +++++++++++++++++---
 1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 42506a9..4275ee2 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -2261,10 +2261,20 @@ void step_once (SIM_CPU *cpu)
       break;
     }
 
-  /* TODO: Handle overflow into high 32 bits.  */
   /* TODO: Try to use a common counter and only update on demand (reads).  */
-  ++cpu->csr.cycle;
-  ++cpu->csr.instret;
+  if (RISCV_XLEN (cpu) == 32)
+    {
+      unsigned_word old_cycle = cpu->csr.cycle++;
+
+      /* Increase cycleh if cycle is overflowed.  */
+      if (old_cycle > cpu->csr.cycle)
+	cpu->csr.cycleh++;
+    }
+  else
+    ++cpu->csr.cycle;
+
+  cpu->csr.instret = cpu->csr.cycle;
+  cpu->csr.instreth = cpu->csr.cycleh;
 
   cpu->pc = pc;
 }
@@ -2398,6 +2408,10 @@ initialize_cpu (SIM_DESC sd, SIM_CPU *cpu, int mhartid)
 
   cpu->csr.mimpid = 0x8000;
   cpu->csr.mhartid = mhartid;
+  cpu->csr.cycle = 0;
+  cpu->csr.cycleh = 0;
+  cpu->csr.instret = 0;
+  cpu->csr.instreth = 0;
 }
 \f
 /* Some utils don't like having a NULL environ.  */
-- 
2.7.4

Re: [PATCH 15/24] RISC-V sim: Improve cycle and instret counts.

[Mike Frysinger]

On 17 Apr 2021 10:58, Jim Wilson wrote:
> @@ -2398,6 +2408,10 @@ initialize_cpu (SIM_DESC sd, SIM_CPU *cpu, int mhartid)
>  
>    cpu->csr.mimpid = 0x8000;
>    cpu->csr.mhartid = mhartid;
> +  cpu->csr.cycle = 0;
> +  cpu->csr.cycleh = 0;
> +  cpu->csr.instret = 0;
> +  cpu->csr.instreth = 0;

if this is done so we can re-initialize the CPU and have all the CSR's be
reset, we should do this with a single memset across all of cpu->csr right ?
are there any that should be preserved ?  if there were, i'd argue that cycle
falls into that bucket too.
-mike

Re: [PATCH 15/24] RISC-V sim: Improve cycle and instret counts.

[Jim Wilson]

On Sun, Apr 18, 2021 at 9:25 PM Mike Frysinger <vapier@gentoo.org> wrote:

> On 17 Apr 2021 10:58, Jim Wilson wrote:
> > @@ -2398,6 +2408,10 @@ initialize_cpu (SIM_DESC sd, SIM_CPU *cpu, int
> mhartid)
> >
> >    cpu->csr.mimpid = 0x8000;
> >    cpu->csr.mhartid = mhartid;
> > +  cpu->csr.cycle = 0;
> > +  cpu->csr.cycleh = 0;
> > +  cpu->csr.instret = 0;
> > +  cpu->csr.instreth = 0;
>
> if this is done so we can re-initialize the CPU and have all the CSR's be
> reset, we should do this with a single memset across all of cpu->csr right
> ?
> are there any that should be preserved ?  if there were, i'd argue that
> cycle
> falls into that bucket too.
>

Yes, we should memset the csrs before we start initializing the non-zero
ones.  And while I'm on the subject, we should memset the fprs too, which
we can do by just running memset on the entire cpu structure instead of
just cpu->regs at the start of initialize_cpu.  I'll have to test this
change to make sure it works.

Jim

[PATCH 16/24] RISC-V sim: Check sbrk argument.

[Jim Wilson]

From: Kito Cheng <kito.cheng@gmail.com>

If sbrk arg greater than memory size, then fail.

	sim/riscv/
	* sim-main.c (execute_i): In TARGET_sys_brk, when setting endbrk,
	add check for DEFAULT_MEM_SIZE.
---
 sim/riscv/sim-main.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 4275ee2..15d9876 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -1791,7 +1791,12 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 		if (cpu->a0 == 0)
 		  cpu->a0 = cpu->endbrk;
 		else
-		  cpu->endbrk = cpu->a0;
+		  {
+		    if (cpu->a0 >= DEFAULT_MEM_SIZE)
+		      cpu->a0 = -1;
+		    else
+		      cpu->endbrk = cpu->a0;
+		  }
 		break;
 	      }
 	    case TARGET_SYS_gettimeofday:
-- 
2.7.4

Re: [PATCH 16/24] RISC-V sim: Check sbrk argument.

[Mike Frysinger]

On 17 Apr 2021 10:58, Jim Wilson wrote:
> +		  {
> +		    if (cpu->a0 >= DEFAULT_MEM_SIZE)
> +		      cpu->a0 = -1;
> +		    else
> +		      cpu->endbrk = cpu->a0;
> +		  }

this incorrectly assumes that DEFAULT_MEM_SIZE is always the limit when it's
not: that is simply the default memory size if the user hasn't specified one.
so it could be larger or smaller.  if it were larger, it'd mean the program
would fail w/OOM even if the user had configured the sim specifically to have
more resources.  if it were smaller, it'd return success when the memory isn't
actually available.

your best bet probably is to just probe the memory and see if it exists.  look
at how sim_core_read_buffer is used in riscv/interp.c:sim_open.  it would mean
the code would fail if the user had MMIO at much higher addresses and then the
program passed that address here, but making the code more precise is kind of
hard, especially when you consider the user could just create a bunch of random
memory stripes.
0000-1000: RAM
1000-2000: Nothing
2000-3000: RAM
3000-4000: Nothing
4000-5000: RAM
5000-6000: Nothing
6000-7000: RAM
...

easier to just document this brk behavior and call it a day rather than try to
protect against overtly pathological scenarios.
-mike

[PATCH 17/24] RISC-V sim: Fix tracing typo.

[Jim Wilson]

From: Kuan-Lin Chen <rufus@andestech.com>

MATCH_LHU should print lhu not lbu.

	sim/riscv/
	* sim-main.c (execute_i): In case MATCH_LHU, fix typo in
	TRACE_INSN call.
---
 sim/riscv/sim-main.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 15d9876..70af81f 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -1587,7 +1587,7 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 				   cpu->regs[rs1] + i_imm)));
       break;
     case MATCH_LHU:
-      TRACE_INSN (cpu, "lbu %s, %" PRIiTW "(%s);",
+      TRACE_INSN (cpu, "lhu %s, %" PRIiTW "(%s);",
 		  rd_name, i_imm, rs1_name);
       store_rd (cpu, rd,
 	sim_core_read_unaligned_2 (cpu, cpu->pc, read_map,
-- 
2.7.4

Re: [PATCH 17/24] RISC-V sim: Fix tracing typo.

[Mike Frysinger]

On 17 Apr 2021 10:58, Jim Wilson wrote:
> MATCH_LHU should print lhu not lbu.

lgtm, thanks
-mike

[PATCH 18/24] RISC-V sim: Improve branch tracing.

[Jim Wilson]

From: Kito Cheng <kito.cheng@gmail.com>

Print target address not offset to target.

	sim/riscv/
	* sim-main.c (execute_i): In cases MATCH_BEQ, MATCH_BLT, MATCH_BLTU,
	MATCH_BGE, and MATCH_BNE, print target address instead of offset.
---
 sim/riscv/sim-main.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 70af81f..13adfa9 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -1486,7 +1486,8 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
     case MATCH_BEQ:
       TRACE_INSN (cpu, "beq %s, %s, %#" PRIxTW ";  "
 		       "// if (%s == %s) goto %#" PRIxTW,
-		  rs1_name, rs2_name, sb_imm, rs1_name, rs2_name, sb_imm);
+		  rs1_name, rs2_name, sb_imm, rs1_name, rs2_name,
+		  cpu->pc + sb_imm);
       if (cpu->regs[rs1] == cpu->regs[rs2])
 	{
 	  pc = cpu->pc + sb_imm;
@@ -1496,7 +1497,8 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
     case MATCH_BLT:
       TRACE_INSN (cpu, "blt %s, %s, %#" PRIxTW ";  "
 		       "// if (%s < %s) goto %#" PRIxTW,
-		  rs1_name, rs2_name, sb_imm, rs1_name, rs2_name, sb_imm);
+		  rs1_name, rs2_name, sb_imm, rs1_name, rs2_name,
+		  cpu->pc + sb_imm);
       if ((signed_word) cpu->regs[rs1] < (signed_word) cpu->regs[rs2])
 	{
 	  pc = cpu->pc + sb_imm;
@@ -1506,7 +1508,8 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
     case MATCH_BLTU:
       TRACE_INSN (cpu, "bltu %s, %s, %#" PRIxTW ";  "
 		       "// if (%s < %s) goto %#" PRIxTW,
-		  rs1_name, rs2_name, sb_imm, rs1_name, rs2_name, sb_imm);
+		  rs1_name, rs2_name, sb_imm, rs1_name, rs2_name,
+		  cpu->pc + sb_imm);
       if ((unsigned_word) cpu->regs[rs1] < (unsigned_word) cpu->regs[rs2])
 	{
 	  pc = cpu->pc + sb_imm;
@@ -1516,7 +1519,8 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
     case MATCH_BGE:
       TRACE_INSN (cpu, "bge %s, %s, %#" PRIxTW ";  "
 		       "// if (%s >= %s) goto %#" PRIxTW,
-		  rs1_name, rs2_name, sb_imm, rs1_name, rs2_name, sb_imm);
+		  rs1_name, rs2_name, sb_imm, rs1_name, rs2_name,
+		  cpu->pc + sb_imm);
       if ((signed_word) cpu->regs[rs1] >= (signed_word) cpu->regs[rs2])
 	{
 	  pc = cpu->pc + sb_imm;
@@ -1526,7 +1530,8 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
     case MATCH_BGEU:
       TRACE_INSN (cpu, "bgeu %s, %s, %#" PRIxTW ";  "
 		       "// if (%s >= %s) goto %#" PRIxTW,
-		  rs1_name, rs2_name, sb_imm, rs1_name, rs2_name, sb_imm);
+		  rs1_name, rs2_name, sb_imm, rs1_name, rs2_name,
+		  cpu->pc + sb_imm);
       if ((unsigned_word) cpu->regs[rs1] >= (unsigned_word) cpu->regs[rs2])
 	{
 	  pc = cpu->pc + sb_imm;
@@ -1536,7 +1541,8 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
     case MATCH_BNE:
       TRACE_INSN (cpu, "bne %s, %s, %#" PRIxTW ";  "
 		       "// if (%s != %s) goto %#" PRIxTW,
-		  rs1_name, rs2_name, sb_imm, rs1_name, rs2_name, sb_imm);
+		  rs1_name, rs2_name, sb_imm, rs1_name, rs2_name,
+		  cpu->pc + sb_imm);
       if (cpu->regs[rs1] != cpu->regs[rs2])
 	{
 	  pc = cpu->pc + sb_imm;
-- 
2.7.4

Re: [PATCH 18/24] RISC-V sim: Improve branch tracing.

[Mike Frysinger]

On 17 Apr 2021 10:58, Jim Wilson wrote:
> Print target address not offset to target.

lgtm, thanks
-mike

[PATCH 19/24] RISC-V sim: Improve tracing for slt* instructions.

[Jim Wilson]

From: Kito Cheng <kito.cheng@gmail.com>

Print args for slt* instructions, and reformat a few lines to improve
style.

	sim/riscv/
	* sim-main.c (execute_i): In case MATCH_sraiw, fix formatting.
	In cases MATCH_SLT, MATCH_SLTU, MATCBH_SLTI, MATCH_SLTIU, add
	instruction args to TRACE_INSN, and fix formatting.
---
 sim/riscv/sim-main.c | 25 +++++++++++++------------
 1 file changed, 13 insertions(+), 12 deletions(-)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 13adfa9..ac0e910 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -1455,28 +1455,29 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
       TRACE_INSN (cpu, "sraiw %s, %s, %" PRIiTW ";  // %s = %s >>> %#" PRIxTW,
 		  rd_name, rs1_name, shamt_imm, rd_name, rs1_name, shamt_imm);
       RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
-      store_rd (cpu, rd, EXTEND32 (
-	ashiftrt ((signed32) cpu->regs[rs1], shamt_imm)));
+      store_rd (cpu, rd,
+		EXTEND32 (ashiftrt ((signed32) cpu->regs[rs1], shamt_imm)));
       break;
     case MATCH_SLT:
-      TRACE_INSN (cpu, "slt");
+      TRACE_INSN (cpu, "slt %s, %s, %s", rd_name, rs1_name, rs2_name);
       store_rd (cpu, rd,
 		!!((signed_word) cpu->regs[rs1] < (signed_word) cpu->regs[rs2]));
       break;
     case MATCH_SLTU:
-      TRACE_INSN (cpu, "sltu");
-      store_rd (cpu, rd, !!((unsigned_word) cpu->regs[rs1] <
-			    (unsigned_word) cpu->regs[rs2]));
+      TRACE_INSN (cpu, "sltu %s, %s, %s", rd_name, rs1_name, rs2_name);
+      store_rd (cpu, rd,
+		!!((unsigned_word) cpu->regs[rs1]
+		   < (unsigned_word) cpu->regs[rs2]));
       break;
     case MATCH_SLTI:
-      TRACE_INSN (cpu, "slti");
-      store_rd (cpu, rd, !!((signed_word) cpu->regs[rs1] <
-			    (signed_word) i_imm));
+      TRACE_INSN (cpu, "slti %s, %s, %" PRIiTW, rd_name, rs1_name, i_imm);
+      store_rd (cpu, rd,
+		!!((signed_word) cpu->regs[rs1] < (signed_word) i_imm));
       break;
     case MATCH_SLTIU:
-      TRACE_INSN (cpu, "sltiu");
-      store_rd (cpu, rd, !!((unsigned_word) cpu->regs[rs1] <
-			    (unsigned_word) i_imm));
+      TRACE_INSN (cpu, "sltiu %s, %s, %" PRIiTW, rd_name, rs1_name, i_imm);
+      store_rd (cpu, rd,
+		!!((unsigned_word) cpu->regs[rs1] < (unsigned_word) i_imm));
       break;
     case MATCH_AUIPC:
       TRACE_INSN (cpu, "auipc %s, %" PRIiTW ";  // %s = pc + %" PRIiTW,
-- 
2.7.4

Re: [PATCH 19/24] RISC-V sim: Improve tracing for slt* instructions.

[Mike Frysinger]

On 17 Apr 2021 10:58, Jim Wilson wrote:
> Print args for slt* instructions, and reformat a few lines to improve
> style.

lgtm, thanks
-mike

[PATCH 20/24] RISC-V sim: Set brk to _end if possible.

[Jim Wilson]

From: Kito Cheng <kito.cheng@gmail.com>

Search the symbol table for the address of _end and use it to initialize
brk.  Otherwise, set it to the end of the section with the highest address.

	sim/riscv/
	* interp.c (riscv_get_symbol): New.
	(sim_create_inferior): Call riscv_get_symbol to get address of
	_end.  Use it to set cpu->endbrk.
---
 sim/riscv/interp.c | 46 ++++++++++++++++++++++++++++++++++++++--------
 1 file changed, 38 insertions(+), 8 deletions(-)

diff --git a/sim/riscv/interp.c b/sim/riscv/interp.c
index c98f6ab..7af97d5 100644
--- a/sim/riscv/interp.c
+++ b/sim/riscv/interp.c
@@ -127,14 +127,35 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback,
   return sd;
 }
 \f
+/* Search the symbol table for the symbol SYM, and return its address.  */
+
+static bfd_vma
+riscv_get_symbol (SIM_DESC sd, const char *sym)
+{
+  long symcount = STATE_PROG_SYMS_COUNT (sd);
+  asymbol **symtab = STATE_PROG_SYMS (sd);
+  int i;
+
+  for (i = 0;i < symcount; ++i)
+    {
+      if (strcmp (sym, bfd_asymbol_name (symtab[i])) == 0)
+	{
+	  bfd_vma sa;
+	  sa = bfd_asymbol_value (symtab[i]);
+	  return sa;
+	}
+    }
+
+  /* Symbol not found.  */
+  return 0;
+}
+
 SIM_RC
 sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
 		     char * const *argv, char * const *env)
 {
   SIM_CPU *cpu = STATE_CPU (sd, 0);
   SIM_ADDR addr;
-  Elf_Internal_Phdr *phdr;
-  int i, phnum;
 
   /* Set the PC.  */
   if (abfd != NULL)
@@ -143,13 +164,22 @@ sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
     addr = 0;
   sim_pc_set (cpu, addr);
 
-  /* Set endbrk to highest section end address.  */
-  phdr = elf_tdata (abfd)->phdr;
-  phnum = elf_elfheader (abfd)->e_phnum;
-  for (i = 0; i < phnum; i++)
+  /* Try to find _end symbol, and set it to the end of brk.  */
+  trace_load_symbols (sd);
+  cpu->endbrk = riscv_get_symbol (sd, "_end");
+
+  /* If not found, set end of brk to end of all section.  */
+  if (cpu->endbrk == 0)
     {
-      if (phdr[i].p_paddr + phdr[i].p_memsz > cpu->endbrk)
-	cpu->endbrk = phdr[i].p_paddr + phdr[i].p_memsz;
+      Elf_Internal_Phdr *phdr = elf_tdata (abfd)->phdr;
+      int phnum = elf_elfheader (abfd)->e_phnum;
+      int i;
+
+      for (i = 0; i < phnum; i++)
+	{
+	  if (phdr[i].p_paddr + phdr[i].p_memsz > cpu->endbrk)
+	    cpu->endbrk = phdr[i].p_paddr + phdr[i].p_memsz;
+	}
     }
 
   /* Standalone mode (i.e. `run`) will take care of the argv for us in
-- 
2.7.4

Re: [PATCH 20/24] RISC-V sim: Set brk to _end if possible.

[Mike Frysinger]

On 17 Apr 2021 10:58, Jim Wilson wrote:
> +static bfd_vma
> +riscv_get_symbol (SIM_DESC sd, const char *sym)
> +{
> +  long symcount = STATE_PROG_SYMS_COUNT (sd);
> +  asymbol **symtab = STATE_PROG_SYMS (sd);
> +  int i;
> +
> +  for (i = 0;i < symcount; ++i)
> +    {
> +      if (strcmp (sym, bfd_asymbol_name (symtab[i])) == 0)
> +	{
> +	  bfd_vma sa;
> +	  sa = bfd_asymbol_value (symtab[i]);
> +	  return sa;
> +	}
> +    }
> +
> +  /* Symbol not found.  */
> +  return 0;
> +}

this is trace_sym_value.  am i missing something ?

> +  /* Try to find _end symbol, and set it to the end of brk.  */
> +  trace_load_symbols (sd);

missing error checking
-mike

Re: [PATCH 20/24] RISC-V sim: Set brk to _end if possible.

[Jim Wilson]

On Sun, Apr 18, 2021 at 10:41 PM Mike Frysinger <vapier@gentoo.org> wrote:

> On 17 Apr 2021 10:58, Jim Wilson wrote:
> > +static bfd_vma
> > +riscv_get_symbol (SIM_DESC sd, const char *sym)
> ...
>
> this is trace_sym_value.  am i missing something ?
>

I think the patch author didn't realize trace_sym_value was there.  I will
fix to use it instead.

> +  /* Try to find _end symbol, and set it to the end of brk.  */
> > +  trace_load_symbols (sd);
>
> missing error checking
>

With the change to use trace_sym_value this line gets deleted.

Jim

[PATCH 21/24] RISC-V sim: Fix mingw builds.

[Jim Wilson]

Ifdef out TARGET_SYS_link support as mingw doesn't support that syscall.

	sim/riscv/
	* sim-main.c (execute_i): Ifdef out TARGET_sys_link for mingw32.
---
 sim/riscv/sim-main.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index ac0e910..82c8d4e 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -1784,6 +1784,7 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 
 	  switch (cpu->a7)
 	    {
+#ifndef __MINGW32__
 	    case TARGET_SYS_link:
 	      {
 		char oldpath[1024], newpath[1024];
@@ -1792,6 +1793,7 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 		cpu->a0 = link (oldpath, newpath);
 		break;
 	      }
+#endif
 	    case TARGET_SYS_brk:
 	      {
 		/* FIXME: Check the invalid access.  */
-- 
2.7.4

Re: [PATCH 21/24] RISC-V sim: Fix mingw builds.

[Mike Frysinger]

On 17 Apr 2021 10:58, Jim Wilson wrote:
>  	  switch (cpu->a7)
>  	    {
> +#ifndef __MINGW32__

we def don't want to do it this way.  test for the func at configure time via
AC_CHECK_FUNCS_ONCE and then make the logic conditional upon it existing.
-mike

[PATCH 22/24] RISC-V sim: Support compressed FP instructions.

[Jim Wilson]

Add functions to handle INSN_CLASS_F_AND_C and INSN_CLASS_D_AND_C.  Add
decode errors for insns that can decode to more than one class depending
on XLEN, if decoded in the wrong class.

	sim/riscv/
	* sim-main.c (execute_c): For F and D compressed instructions,
	call sim_engine_halt and report decode error.
	(execute_f_and_c, execute_d_and_c): New functions.
	(execute_one): Call the new functions.
---
 sim/riscv/sim-main.c | 376 +++++++++++++++++++++++++++++++++++++++++----------
 1 file changed, 306 insertions(+), 70 deletions(-)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 82c8d4e..67ad768 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -914,16 +914,10 @@ execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 	case MATCH_C_FLD:
 	  if (RISCV_XLEN (cpu) <= 64)
 	    {
-	      TRACE_INSN (cpu, "c.fld %s, %" PRIiTW "(%s);"
-			       " // %s = *(%s + %" PRIiTW ")",
-			  fcrs2s_name, EXTRACT_CLTYPE_LD_IMM (iw), fcrs1s_name,
-			  fcrs2s_name, fcrs1s_name, EXTRACT_CLTYPE_LD_IMM (iw));
-	      /* rv32/64, c.fld instruction.  */
-	      store_frd64 (cpu, crs2s,
-		sim_core_read_unaligned_8 (cpu, cpu->pc, read_map,
-					   cpu->regs[crs1s]
-					   + EXTRACT_CLTYPE_LD_IMM (iw)));
-	      return pc;
+	      /* rv32/64, c.fld instruction which is D and C.  */
+	      TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
+	      sim_engine_halt (sd, cpu, NULL, cpu->pc,
+			       sim_signalled, SIM_SIGILL);
 	    }
 	  else
 	    {
@@ -933,17 +927,12 @@ execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 			       sim_signalled, SIM_SIGILL);
 	    }
 	case MATCH_C_FLW:
-	  /* rv32: c.flw, rv64: c.ld.  */
+	  /* rv32: c.flw F and C, rv64: c.ld.  */
 	  if (RISCV_XLEN (cpu) == 32)
 	    {
-	      TRACE_INSN (cpu, "c.flw %s, %" PRIiTW "(%s);"
-			       " // *(%s + %" PRIiTW ") = %s",
-			  fcrs2s_name, EXTRACT_CLTYPE_LW_IMM (iw), crs1s_name,
-			  crs1s_name, EXTRACT_CLTYPE_LW_IMM (iw), fcrs2s_name);
-	      store_frd (cpu, crs2s, EXTEND32 (
-		sim_core_read_unaligned_4 (cpu, cpu->pc, read_map,
-					   cpu->regs[crs1s]
-					   + EXTRACT_CLTYPE_LW_IMM (iw))));
+	      TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
+	      sim_engine_halt (sd, cpu, NULL, cpu->pc,
+			       sim_signalled, SIM_SIGILL);
 	    }
 	  else
 	    {
@@ -960,16 +949,10 @@ execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 	case MATCH_C_FSD:
 	  if (RISCV_XLEN (cpu) <= 64)
 	    {
-	      /* rv32/64, c.fsd instruction.  */
-	      TRACE_INSN (cpu, "c.fsd %s, %" PRIiTW "(%s);"
-			       " // *(%s + %" PRIiTW ") = %s",
-			  fcrs2s_name, EXTRACT_CLTYPE_LD_IMM (iw), crs1s_name,
-			  crs1s_name, EXTRACT_CLTYPE_LD_IMM (iw), fcrs2s_name);
-	      sim_core_write_unaligned_8 (cpu, cpu->pc, write_map,
-					  cpu->regs[crs1s]
-					  + EXTRACT_CLTYPE_LD_IMM (iw),
-					  cpu->fpregs[crs2s].v[0]);
-	      return pc;
+	      /* rv32/64, c.fsd instruction which is D and C.  */
+	      TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
+	      sim_engine_halt (sd, cpu, NULL, cpu->pc,
+			       sim_signalled, SIM_SIGILL);
 	    }
 	  else
 	    {
@@ -979,17 +962,12 @@ execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 			       sim_signalled, SIM_SIGILL);
 	    }
 	case MATCH_C_FSW:
-	  /* rv32: c.fsw, rv64: c.sd.  */
+	  /* rv32: c.fsw F and C, rv64: c.sd.  */
 	  if (RISCV_XLEN (cpu) == 32)
 	    {
-	      TRACE_INSN (cpu, "c.fsw %s, %" PRIiTW "(%s);"
-			       " // *(%s + %" PRIiTW ") = %s",
-			  fcrs2s_name, EXTRACT_CLTYPE_LW_IMM (iw), crs1s_name,
-			  crs1s_name, EXTRACT_CLTYPE_LW_IMM (iw), fcrs2s_name);
-	      sim_core_write_unaligned_4 (cpu, cpu->pc, write_map,
-					  cpu->regs[crs1s]
-					  + EXTRACT_CLTYPE_LW_IMM (iw),
-					  cpu->fpregs[crs2s].w[0]);
+	      TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
+	      sim_engine_halt (sd, cpu, NULL, cpu->pc,
+			       sim_signalled, SIM_SIGILL);
 	    }
 	  else
 	    {
@@ -1173,18 +1151,13 @@ execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 	  store_rd (cpu, rd, cpu->regs[rd] + cpu->regs[crs2]);
 	  return pc;
 	case MATCH_C_FLDSP:
-	  /* rv32/64: c.fldsp, rv128: c.flqsp.  */
+	  /* rv32/64: c.fldsp D and C, rv128: c.flqsp.  */
 	  if (RISCV_XLEN (cpu) <= 64)
 	    {
-	      TRACE_INSN (cpu, "c.fldsp %s, %" PRIiTW "(sp);"
-			       " // %s = *(sp + %" PRIiTW ")",
-			  frd_name, EXTRACT_CITYPE_LDSP_IMM (iw),
-			  frd_name, EXTRACT_CITYPE_LDSP_IMM (iw));
-	      store_frd64 (cpu, rd,
-		sim_core_read_unaligned_8 (cpu, cpu->pc, read_map,
-					   cpu->sp
-					   + EXTRACT_CITYPE_LDSP_IMM (iw)));
-	      return pc;
+	      TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
+	      sim_engine_halt (sd, cpu, NULL, cpu->pc,
+			       sim_signalled, SIM_SIGILL);
+
 	    }
 	  else
 	    {
@@ -1193,17 +1166,13 @@ execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 			       sim_signalled, SIM_SIGILL);
 	    }
 	case MATCH_C_FLWSP:
-	  /* rv32: c.flwsp, rv64: c.ldsp.  */
+	  /* rv32: c.flwsp F and C, rv64: c.ldsp.  */
 	  if (RISCV_XLEN (cpu) == 32)
 	    {
-	      TRACE_INSN (cpu, "c.flwsp %s, %" PRIiTW "(sp);"
-			       " // %s = *(sp + %" PRIiTW ")",
-			  frd_name, EXTRACT_CITYPE_LWSP_IMM (iw),
-			  frd_name, EXTRACT_CITYPE_LWSP_IMM (iw));
-	      store_frd (cpu, rd, EXTEND32 (
-		sim_core_read_unaligned_4 (cpu, cpu->pc, read_map,
-					   cpu->sp
-					   + EXTRACT_CITYPE_LWSP_IMM (iw))));
+	      TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
+	      sim_engine_halt (sd, cpu, NULL, cpu->pc,
+			       sim_signalled, SIM_SIGILL);
+
 	    }
 	  else
 	    {
@@ -1218,26 +1187,157 @@ execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 	    }
 	  return pc;
 	case MATCH_C_FSDSP:
-	  /* rv32/64: c.fsdsp, rv128: c.fsqsp.  */
+	  /* rv32/64: c.fsdsp D and C, rv128: c.fsqsp.  */
 	  if (RISCV_XLEN (cpu) <= 64)
 	    {
-	      TRACE_INSN (cpu, "c.fsdsp %s, %" PRIiTW "(sp);"
+	      TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
+	      sim_engine_halt (sd, cpu, NULL, cpu->pc,
+			       sim_signalled, SIM_SIGILL);
+
+	    }
+	  else
+	    {
+	      TRACE_INSN (cpu, "UNHANDLED RV128 INSN: %s", op->name);
+	      sim_engine_halt (sd, cpu, NULL, cpu->pc,
+			       sim_signalled, SIM_SIGILL);
+	    }
+	case MATCH_C_FSWSP:
+	  /* rv32: c.fswsp F and C, rv64: c.sdsp.  */
+	  if (RISCV_XLEN (cpu) == 32)
+	    {
+	      TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
+	      sim_engine_halt (sd, cpu, NULL, cpu->pc,
+			       sim_signalled, SIM_SIGILL);
+	    }
+	  else
+	    {
+	      TRACE_INSN (cpu, "c.sdsp %s, %" PRIiTW "(sp);"
 			       " // *(sp + %" PRIiTW ") = %s",
-			  fcrs2_name, EXTRACT_CSSTYPE_SDSP_IMM (iw),
-			  EXTRACT_CSSTYPE_SDSP_IMM (iw), fcrs2_name);
+			  crs2_name, EXTRACT_CSSTYPE_SDSP_IMM (iw),
+			  EXTRACT_CSSTYPE_SDSP_IMM (iw), crs2_name);
 	      sim_core_write_unaligned_8 (cpu, cpu->pc, write_map,
 					  cpu->sp + EXTRACT_CSSTYPE_SDSP_IMM (iw),
-					  cpu->fpregs[crs2].v[0]);
-	      return pc;
+					  cpu->regs[crs2]);
+	    }
+	  return pc;
+	default:
+	  TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
+	  sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
+	}
+    default:
+      TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
+      sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
+    }
+
+  return pc;
+}
+
+static sim_cia
+execute_f_and_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
+{
+  SIM_DESC sd = CPU_STATE (cpu);
+  const int mask_group_op = 0x3;
+  const int mask_mv_jr = 0xf003;
+  const int match_mv_jr = 0x8002;
+  const int mask_ebk_jalr_add = 0xf003;
+  const int match_ebk_jalr_add = 0x9002;
+
+  int rd = (iw >> OP_SH_RD) & OP_MASK_RD;
+  int crs2 = (iw >> OP_SH_CRS2) & OP_MASK_CRS2;
+  int crs1s = ((iw >> OP_SH_CRS1S) & OP_MASK_CRS1S) | 0x8;
+  int crs2s = ((iw >> OP_SH_CRS2S) & OP_MASK_CRS2S) | 0x8;
+  int ciw_rd = crs2s;
+  unsigned_word rvc_imm = EXTRACT_CITYPE_IMM (iw);
+  unsigned_word tmp;
+  sim_cia pc = cpu->pc + 2;
+
+  const char *rd_name = riscv_gpr_names_abi[rd];
+  const char *crs2_name = riscv_gpr_names_abi[crs2];
+  const char *crs1s_name = riscv_gpr_names_abi[crs1s];
+  const char *crs2s_name = riscv_gpr_names_abi[crs2s];
+  const char *ciw_rd_name = crs2s_name;
+
+  const char *frd_name = riscv_fpr_names_abi[rd];
+  const char *fcrs2_name = riscv_fpr_names_abi[crs2];
+  const char *fcrs1s_name = riscv_fpr_names_abi[crs1s];
+  const char *fcrs2s_name = riscv_fpr_names_abi[crs2s];
+  const char *fciw_rd_name = fcrs2s_name;
+
+  switch (op->match & mask_group_op)
+    {
+    case 0:
+      switch (op->match)
+	{
+	case MATCH_C_FLW:
+	  /* rv32: c.flw F and C, rv64: c.ld.  */
+	  if (RISCV_XLEN (cpu) == 32)
+	    {
+	      TRACE_INSN (cpu, "c.flw %s, %" PRIiTW "(%s);"
+			       " // *(%s + %" PRIiTW ") = %s",
+			  fcrs2s_name, EXTRACT_CLTYPE_LW_IMM (iw), crs1s_name,
+			  crs1s_name, EXTRACT_CLTYPE_LW_IMM (iw), fcrs2s_name);
+	      store_frd (cpu, crs2s, EXTEND32 (
+		sim_core_read_unaligned_4 (cpu, cpu->pc, read_map,
+					   cpu->regs[crs1s]
+					   + EXTRACT_CLTYPE_LW_IMM (iw))));
 	    }
 	  else
 	    {
-	      TRACE_INSN (cpu, "UNHANDLED RV128 INSN: %s", op->name);
+	      TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
 	      sim_engine_halt (sd, cpu, NULL, cpu->pc,
 			       sim_signalled, SIM_SIGILL);
 	    }
+	  return pc;
+	case MATCH_C_FSW:
+	  /* rv32: c.fsw F and C, rv64: c.sd.  */
+	  if (RISCV_XLEN (cpu) == 32)
+	    {
+	      TRACE_INSN (cpu, "c.fsw %s, %" PRIiTW "(%s);"
+			       " // *(%s + %" PRIiTW ") = %s",
+			  fcrs2s_name, EXTRACT_CLTYPE_LW_IMM (iw), crs1s_name,
+			  crs1s_name, EXTRACT_CLTYPE_LW_IMM (iw), fcrs2s_name);
+	      sim_core_write_unaligned_4 (cpu, cpu->pc, write_map,
+					  cpu->regs[crs1s]
+					  + EXTRACT_CLTYPE_LW_IMM (iw),
+					  cpu->fpregs[crs2s].w[0]);
+	    }
+	  else
+	    {
+	      TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
+	      sim_engine_halt (sd, cpu, NULL, cpu->pc,
+			       sim_signalled, SIM_SIGILL);
+	    }
+	  return pc;
+	default:
+	  TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
+	  sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
+	}
+    case 2:
+      switch (op->match)
+	{
+	case MATCH_C_FLWSP:
+	  /* rv32: c.flwsp F and C, rv64: c.ldsp.  */
+	  if (RISCV_XLEN (cpu) == 32)
+	    {
+	      TRACE_INSN (cpu, "c.flwsp %s, %" PRIiTW "(sp);"
+			       " // %s = *(sp + %" PRIiTW ")",
+			  frd_name, EXTRACT_CITYPE_LWSP_IMM (iw),
+			  frd_name, EXTRACT_CITYPE_LWSP_IMM (iw));
+	      store_frd (cpu, rd, EXTEND32 (
+		sim_core_read_unaligned_4 (cpu, cpu->pc, read_map,
+					   cpu->sp
+					   + EXTRACT_CITYPE_LWSP_IMM (iw))));
+	    }
+	  else
+	    {
+	      TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
+	      sim_engine_halt (sd, cpu, NULL, cpu->pc,
+			       sim_signalled, SIM_SIGILL);
+
+	    }
+	  return pc;
 	case MATCH_C_FSWSP:
-	  /* rv32: c.fswsp, rv64: c.sdsp.  */
+	  /* rv32: c.fswsp F and C, rv64: c.sdsp.  */
 	  if (RISCV_XLEN (cpu) == 32)
 	    {
 	      TRACE_INSN (cpu, "c.fswsp %s, %" PRIiTW "(sp);"
@@ -1251,15 +1351,147 @@ execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 	    }
 	  else
 	    {
-	      TRACE_INSN (cpu, "c.sdsp %s, %" PRIiTW "(sp);"
+	      TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
+	      sim_engine_halt (sd, cpu, NULL, cpu->pc,
+			       sim_signalled, SIM_SIGILL);
+
+	    }
+	  return pc;
+	default:
+	  TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
+	  sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
+	}
+    default:
+      TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
+      sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
+    }
+
+  return pc;
+}
+
+static sim_cia
+execute_d_and_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
+{
+  SIM_DESC sd = CPU_STATE (cpu);
+  const int mask_group_op = 0x3;
+  const int mask_mv_jr = 0xf003;
+  const int match_mv_jr = 0x8002;
+  const int mask_ebk_jalr_add = 0xf003;
+  const int match_ebk_jalr_add = 0x9002;
+
+  int rd = (iw >> OP_SH_RD) & OP_MASK_RD;
+  int crs2 = (iw >> OP_SH_CRS2) & OP_MASK_CRS2;
+  int crs1s = ((iw >> OP_SH_CRS1S) & OP_MASK_CRS1S) | 0x8;
+  int crs2s = ((iw >> OP_SH_CRS2S) & OP_MASK_CRS2S) | 0x8;
+  int ciw_rd = crs2s;
+  unsigned_word rvc_imm = EXTRACT_CITYPE_IMM (iw);
+  unsigned_word tmp;
+  sim_cia pc = cpu->pc + 2;
+
+  const char *rd_name = riscv_gpr_names_abi[rd];
+  const char *crs2_name = riscv_gpr_names_abi[crs2];
+  const char *crs1s_name = riscv_gpr_names_abi[crs1s];
+  const char *crs2s_name = riscv_gpr_names_abi[crs2s];
+  const char *ciw_rd_name = crs2s_name;
+
+  const char *frd_name = riscv_fpr_names_abi[rd];
+  const char *fcrs2_name = riscv_fpr_names_abi[crs2];
+  const char *fcrs1s_name = riscv_fpr_names_abi[crs1s];
+  const char *fcrs2s_name = riscv_fpr_names_abi[crs2s];
+  const char *fciw_rd_name = fcrs2s_name;
+
+  switch (op->match & mask_group_op)
+    {
+    case 0:
+      switch (op->match)
+	{
+	case MATCH_C_FLD:
+	  if (RISCV_XLEN (cpu) <= 64)
+	    {
+	      TRACE_INSN (cpu, "c.fld %s, %" PRIiTW "(%s);"
+			       " // %s = *(%s + %" PRIiTW ")",
+			  fcrs2s_name, EXTRACT_CLTYPE_LD_IMM (iw), fcrs1s_name,
+			  fcrs2s_name, fcrs1s_name, EXTRACT_CLTYPE_LD_IMM (iw));
+	      /* rv32/64, c.fld D and C instruction.  */
+	      store_frd64 (cpu, crs2s,
+		sim_core_read_unaligned_8 (cpu, cpu->pc, read_map,
+					   cpu->regs[crs1s]
+					   + EXTRACT_CLTYPE_LD_IMM (iw)));
+	      return pc;
+	    }
+	  else
+	    {
+	      /* rv128, c.lq instruction, which is C.  */
+	      TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
+	      sim_engine_halt (sd, cpu, NULL, cpu->pc,
+			       sim_signalled, SIM_SIGILL);
+	    }
+	case MATCH_C_FSD:
+	  if (RISCV_XLEN (cpu) <= 64)
+	    {
+	      /* rv32/64, c.fsd D and C instruction.  */
+	      TRACE_INSN (cpu, "c.fsd %s, %" PRIiTW "(%s);"
+			       " // *(%s + %" PRIiTW ") = %s",
+			  fcrs2s_name, EXTRACT_CLTYPE_LD_IMM (iw), crs1s_name,
+			  crs1s_name, EXTRACT_CLTYPE_LD_IMM (iw), fcrs2s_name);
+	      sim_core_write_unaligned_8 (cpu, cpu->pc, write_map,
+					  cpu->regs[crs1s]
+					  + EXTRACT_CLTYPE_LD_IMM (iw),
+					  cpu->fpregs[crs2s].v[0]);
+	      return pc;
+	    }
+	  else
+	    {
+	      TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
+	      sim_engine_halt (sd, cpu, NULL, cpu->pc,
+			       sim_signalled, SIM_SIGILL);
+	    }
+	default:
+	  TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
+	  sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
+	}
+    case 2:
+      switch (op->match)
+	{
+	case MATCH_C_FLDSP:
+	  /* rv32/64: c.fldsp D and C, rv128: c.flqsp.  */
+	  if (RISCV_XLEN (cpu) <= 64)
+	    {
+	      TRACE_INSN (cpu, "c.fldsp %s, %" PRIiTW "(sp);"
+			       " // %s = *(sp + %" PRIiTW ")",
+			  frd_name, EXTRACT_CITYPE_LDSP_IMM (iw),
+			  frd_name, EXTRACT_CITYPE_LDSP_IMM (iw));
+	      store_frd64 (cpu, rd,
+		sim_core_read_unaligned_8 (cpu, cpu->pc, read_map,
+					   cpu->sp
+					   + EXTRACT_CITYPE_LDSP_IMM (iw)));
+	      return pc;
+	    }
+	  else
+	    {
+	      TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
+	      sim_engine_halt (sd, cpu, NULL, cpu->pc,
+			       sim_signalled, SIM_SIGILL);
+	    }
+	case MATCH_C_FSDSP:
+	  /* rv32/64: c.fsdsp D and C, rv128: c.fsqsp.  */
+	  if (RISCV_XLEN (cpu) <= 64)
+	    {
+	      TRACE_INSN (cpu, "c.fsdsp %s, %" PRIiTW "(sp);"
 			       " // *(sp + %" PRIiTW ") = %s",
-			  crs2_name, EXTRACT_CSSTYPE_SDSP_IMM (iw),
-			  EXTRACT_CSSTYPE_SDSP_IMM (iw), crs2_name);
+			  fcrs2_name, EXTRACT_CSSTYPE_SDSP_IMM (iw),
+			  EXTRACT_CSSTYPE_SDSP_IMM (iw), fcrs2_name);
 	      sim_core_write_unaligned_8 (cpu, cpu->pc, write_map,
 					  cpu->sp + EXTRACT_CSSTYPE_SDSP_IMM (iw),
-					  cpu->regs[crs2]);
+					  cpu->fpregs[crs2].v[0]);
+	      return pc;
+	    }
+	  else
+	    {
+	      TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
+	      sim_engine_halt (sd, cpu, NULL, cpu->pc,
+			       sim_signalled, SIM_SIGILL);
 	    }
-	  return pc;
 	default:
 	  TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
 	  sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
@@ -2220,6 +2452,10 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
       return execute_f (cpu, iw, op);
     case INSN_CLASS_C:
       return execute_c (cpu, iw, op);
+    case INSN_CLASS_F_AND_C:
+      return execute_f_and_c (cpu, iw, op);
+    case INSN_CLASS_D_AND_C:
+      return execute_d_and_c (cpu, iw, op);
     case INSN_CLASS_ZIFENCEI:
       return execute_zifencei (cpu, iw, op);
     default:
-- 
2.7.4

Re: [PATCH 22/24] RISC-V sim: Support compressed FP instructions.

[Mike Frysinger]

On 17 Apr 2021 10:58, Jim Wilson wrote:
> Add functions to handle INSN_CLASS_F_AND_C and INSN_CLASS_D_AND_C.  Add
> decode errors for insns that can decode to more than one class depending
> on XLEN, if decoded in the wrong class.

lgtm other than missing tests
-mike

[PATCH 23/24] RISC-V sim: Add zicsr support.

[Jim Wilson]

The CSR and f*csr, f*rm, and f*flags instructions are in INSN_CLASS_ZICSR.
Move to a new execute_zicsr function.

	sim/riscv/
	* sim-main.c (execute_f): Remove CSR instructions.
	(execute_i): Likewise.
	(execute_zicsr): New function.
	(execute_one): Call execute_zicsr.
---
 sim/riscv/sim-main.c | 256 ++++++++++++++++++++++++++++-----------------------
 1 file changed, 140 insertions(+), 116 deletions(-)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 67ad768..3974f61 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -761,39 +761,6 @@ execute_f (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 	  break;
 	}
       break;
-    case MATCH_FRCSR:
-      TRACE_INSN (cpu, "frcsr %s",
-		  rd_name);
-      store_rd (cpu, rd, fetch_csr (cpu, "fcsr", CSR_FCSR, &cpu->csr.fcsr));
-      break;
-    case MATCH_FSCSR:
-      TRACE_INSN (cpu, "fscsr %s, %sf",
-		  rd_name, rs1_name);
-      store_rd (cpu, rd, fetch_csr (cpu, "fcsr", CSR_FCSR, &cpu->csr.fcsr));
-      store_csr (cpu, "fcsr", CSR_FCSR, &cpu->csr.fcsr, cpu->regs[rs1]);
-      break;
-    case MATCH_FRRM:
-      TRACE_INSN (cpu, "frrm %s",
-		  rd_name);
-      store_rd (cpu, rd, fetch_csr (cpu, "frm", CSR_FRM, &cpu->csr.frm));
-      break;
-    case MATCH_FSRM:
-      TRACE_INSN (cpu, "fsrm %s, %s",
-		  rd_name, rs1_name);
-      store_rd (cpu, rd, fetch_csr (cpu, "frm", CSR_FCSR, &cpu->csr.frm));
-      store_csr (cpu, "frm", CSR_FCSR, &cpu->csr.frm, cpu->regs[rs1]);
-      break;
-    case MATCH_FRFLAGS:
-      TRACE_INSN (cpu, "frflags %s",
-		  rd_name);
-      store_rd (cpu, rd, fetch_csr (cpu, "fflags", CSR_FFLAGS, &cpu->csr.fflags));
-      break;
-    case MATCH_FSFLAGS:
-      TRACE_INSN (cpu, "fsflags %s, %s",
-		  rd_name, frs1_name);
-      store_rd (cpu, rd, fetch_csr (cpu, "fflags", CSR_FFLAGS, &cpu->csr.fflags));
-      store_csr (cpu, "fflags", CSR_FFLAGS, &cpu->csr.fflags, cpu->regs[rs1]);
-      break;
     default:
       TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
       sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
@@ -1872,89 +1839,6 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 				  cpu->regs[rs1] + s_imm, cpu->regs[rs2]);
       break;
 
-    case MATCH_CSRRC:
-      TRACE_INSN (cpu, "csrrc");
-      switch (csr)
-	{
-#define DECLARE_CSR(name, num, ...) \
-	case num: \
-	  store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
-	  store_csr (cpu, #name, num, &cpu->csr.name, \
-		     cpu->csr.name & !cpu->regs[rs1]); \
-	  break;
-#include "opcode/riscv-opc.h"
-#undef DECLARE_CSR
-	}
-      break;
-    case MATCH_CSRRCI:
-      TRACE_INSN (cpu, "csrrci");
-      switch (csr)
-	{
-#define DECLARE_CSR(name, num, ...) \
-	case num: \
-	  store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
-	  store_csr (cpu, #name, num, &cpu->csr.name, \
-		     cpu->csr.name & !rs1); \
-	  break;
-#include "opcode/riscv-opc.h"
-#undef DECLARE_CSR
-	}
-      break;
-    case MATCH_CSRRS:
-      TRACE_INSN (cpu, "csrrs");
-      switch (csr)
-	{
-#define DECLARE_CSR(name, num, ...) \
-	case num: \
-	  store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
-	  store_csr (cpu, #name, num, &cpu->csr.name, \
-		     cpu->csr.name | cpu->regs[rs1]); \
-	  break;
-#include "opcode/riscv-opc.h"
-#undef DECLARE_CSR
-	}
-      break;
-    case MATCH_CSRRSI:
-      TRACE_INSN (cpu, "csrrsi");
-      switch (csr)
-	{
-#define DECLARE_CSR(name, num, ...) \
-	case num: \
-	  store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
-	  store_csr (cpu, #name, num, &cpu->csr.name, \
-		     cpu->csr.name | rs1); \
-	  break;
-#include "opcode/riscv-opc.h"
-#undef DECLARE_CSR
-	}
-      break;
-    case MATCH_CSRRW:
-      TRACE_INSN (cpu, "csrrw");
-      switch (csr)
-	{
-#define DECLARE_CSR(name, num, ...) \
-	case num: \
-	  store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
-	  store_csr (cpu, #name, num, &cpu->csr.name, cpu->regs[rs1]); \
-	  break;
-#include "opcode/riscv-opc.h"
-#undef DECLARE_CSR
-	}
-      break;
-    case MATCH_CSRRWI:
-      TRACE_INSN (cpu, "csrrwi");
-      switch (csr)
-	{
-#define DECLARE_CSR(name, num, ...) \
-	case num: \
-	  store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
-	  store_csr (cpu, #name, num, &cpu->csr.name, rs1); \
-	  break;
-#include "opcode/riscv-opc.h"
-#undef DECLARE_CSR
-	}
-      break;
-
     case MATCH_RDCYCLE:
       TRACE_INSN (cpu, "rdcycle %s;", rd_name);
       store_rd (cpu, rd, fetch_csr (cpu, "cycle", CSR_CYCLE, &cpu->csr.cycle));
@@ -2409,6 +2293,144 @@ execute_a (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 }
 
 static sim_cia
+execute_zicsr (SIM_CPU *cpu, unsigned_word iw,
+	       const struct riscv_opcode *op)
+{
+  SIM_DESC sd = CPU_STATE (cpu);
+  sim_cia pc = cpu->pc + 4;
+  int rd = (iw >> OP_SH_RD) & OP_MASK_RD;
+  int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1;
+  const char *rd_name = riscv_gpr_names_abi[rd];
+  const char *rs1_name = riscv_gpr_names_abi[rs1];
+  const char *frs1_name = riscv_fpr_names_abi[rs1];
+  unsigned int csr = (iw >> OP_SH_CSR) & OP_MASK_CSR;
+
+  switch (op->match)
+    {
+    case MATCH_CSRRC:
+      TRACE_INSN (cpu, "csrrc");
+      switch (csr)
+	{
+#define DECLARE_CSR(name, num, ...) \
+	case num: \
+	  store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
+	  store_csr (cpu, #name, num, &cpu->csr.name, \
+		     cpu->csr.name & !cpu->regs[rs1]); \
+	  break;
+#include "opcode/riscv-opc.h"
+#undef DECLARE_CSR
+	}
+      break;
+    case MATCH_CSRRCI:
+      TRACE_INSN (cpu, "csrrci");
+      switch (csr)
+	{
+#define DECLARE_CSR(name, num, ...) \
+	case num: \
+	  store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
+	  store_csr (cpu, #name, num, &cpu->csr.name, \
+		     cpu->csr.name & !rs1); \
+	  break;
+#include "opcode/riscv-opc.h"
+#undef DECLARE_CSR
+	}
+      break;
+    case MATCH_CSRRS:
+      TRACE_INSN (cpu, "csrrs");
+      switch (csr)
+	{
+#define DECLARE_CSR(name, num, ...) \
+	case num: \
+	  store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
+	  store_csr (cpu, #name, num, &cpu->csr.name, \
+		     cpu->csr.name | cpu->regs[rs1]); \
+	  break;
+#include "opcode/riscv-opc.h"
+#undef DECLARE_CSR
+	}
+      break;
+    case MATCH_CSRRSI:
+      TRACE_INSN (cpu, "csrrsi");
+      switch (csr)
+	{
+#define DECLARE_CSR(name, num, ...) \
+	case num: \
+	  store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
+	  store_csr (cpu, #name, num, &cpu->csr.name, \
+		     cpu->csr.name | rs1); \
+	  break;
+#include "opcode/riscv-opc.h"
+#undef DECLARE_CSR
+	}
+      break;
+    case MATCH_CSRRW:
+      TRACE_INSN (cpu, "csrrw");
+      switch (csr)
+	{
+#define DECLARE_CSR(name, num, ...) \
+	case num: \
+	  store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
+	  store_csr (cpu, #name, num, &cpu->csr.name, cpu->regs[rs1]); \
+	  break;
+#include "opcode/riscv-opc.h"
+#undef DECLARE_CSR
+	}
+      break;
+    case MATCH_CSRRWI:
+      TRACE_INSN (cpu, "csrrwi");
+      switch (csr)
+	{
+#define DECLARE_CSR(name, num, ...) \
+	case num: \
+	  store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
+	  store_csr (cpu, #name, num, &cpu->csr.name, rs1); \
+	  break;
+#include "opcode/riscv-opc.h"
+#undef DECLARE_CSR
+	}
+      break;
+    case MATCH_FRCSR:
+      TRACE_INSN (cpu, "frcsr %s",
+		  rd_name);
+      store_rd (cpu, rd, fetch_csr (cpu, "fcsr", CSR_FCSR, &cpu->csr.fcsr));
+      break;
+    case MATCH_FSCSR:
+      TRACE_INSN (cpu, "fscsr %s, %sf",
+		  rd_name, rs1_name);
+      store_rd (cpu, rd, fetch_csr (cpu, "fcsr", CSR_FCSR, &cpu->csr.fcsr));
+      store_csr (cpu, "fcsr", CSR_FCSR, &cpu->csr.fcsr, cpu->regs[rs1]);
+      break;
+    case MATCH_FRRM:
+      TRACE_INSN (cpu, "frrm %s",
+		  rd_name);
+      store_rd (cpu, rd, fetch_csr (cpu, "frm", CSR_FRM, &cpu->csr.frm));
+      break;
+    case MATCH_FSRM:
+      TRACE_INSN (cpu, "fsrm %s, %s",
+		  rd_name, rs1_name);
+      store_rd (cpu, rd, fetch_csr (cpu, "frm", CSR_FCSR, &cpu->csr.frm));
+      store_csr (cpu, "frm", CSR_FCSR, &cpu->csr.frm, cpu->regs[rs1]);
+      break;
+    case MATCH_FRFLAGS:
+      TRACE_INSN (cpu, "frflags %s",
+		  rd_name);
+      store_rd (cpu, rd, fetch_csr (cpu, "fflags", CSR_FFLAGS, &cpu->csr.fflags));
+      break;
+    case MATCH_FSFLAGS:
+      TRACE_INSN (cpu, "fsflags %s, %s",
+		  rd_name, frs1_name);
+      store_rd (cpu, rd, fetch_csr (cpu, "fflags", CSR_FFLAGS, &cpu->csr.fflags));
+      store_csr (cpu, "fflags", CSR_FFLAGS, &cpu->csr.fflags, cpu->regs[rs1]);
+      break;
+    default:
+      TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
+      sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
+    }
+
+  return pc;
+}
+
+static sim_cia
 execute_zifencei (SIM_CPU *cpu, unsigned_word iw,
 		  const struct riscv_opcode *op)
 {
@@ -2456,6 +2478,8 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
       return execute_f_and_c (cpu, iw, op);
     case INSN_CLASS_D_AND_C:
       return execute_d_and_c (cpu, iw, op);
+    case INSN_CLASS_ZICSR:
+      return execute_zicsr (cpu, iw, op);
     case INSN_CLASS_ZIFENCEI:
       return execute_zifencei (cpu, iw, op);
     default:
-- 
2.7.4

Re: [PATCH 23/24] RISC-V sim: Add zicsr support.

[Mike Frysinger]

On 17 Apr 2021 10:58, Jim Wilson wrote:
> The CSR and f*csr, f*rm, and f*flags instructions are in INSN_CLASS_ZICSR.
> Move to a new execute_zicsr function.

lgtm
-mike

[PATCH 24/24] RISC-V sim: Fix divw and remw.

[Jim Wilson]

From: Kito Cheng <kito@andestech.com>

According to spec, result is -2^31 only when divisor is -1 AND dividend
is -2^31 for divw.
According to spec, result is 0 only when divisor is -1 AND dividend
is -2^31 for remw.

	sim/riscv/
	* sim-main.c (execute_m): New local dividend32_max.  Set it.  Use
	in cases MATCH_DIVW and MATCH_REMW.
---
 sim/riscv/sim-main.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 3974f61..d92f756 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -2020,9 +2020,11 @@ execute_m (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
   const char *rs1_name = riscv_gpr_names_abi[rs1];
   const char *rs2_name = riscv_gpr_names_abi[rs2];
   unsigned_word tmp, dividend_max;
+  signed_word dividend32_max;
   sim_cia pc = cpu->pc + 4;
 
   dividend_max = -((unsigned_word) 1 << (WITH_TARGET_WORD_BITSIZE - 1));
+  dividend32_max = INT32_MIN;
 
   switch (op->match)
     {
@@ -2041,7 +2043,8 @@ execute_m (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
       TRACE_INSN (cpu, "divw %s, %s, %s;  // %s = %s / %s",
 		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
       RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
-      if (EXTEND32 (cpu->regs[rs2]) == -1)
+      if (EXTEND32 (cpu->regs[rs1]) == dividend32_max
+	  && EXTEND32 (cpu->regs[rs2]) == -1)
 	tmp = 1 << 31;
       else if (EXTEND32 (cpu->regs[rs2]))
 	tmp = EXTEND32 (cpu->regs[rs1]) / EXTEND32 (cpu->regs[rs2]);
@@ -2122,7 +2125,8 @@ execute_m (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
       TRACE_INSN (cpu, "remw %s, %s, %s;  // %s = %s %% %s",
 		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
       RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
-      if (EXTEND32 (cpu->regs[rs2]) == -1)
+      if (EXTEND32 (cpu->regs[rs1]) == dividend32_max
+	  && EXTEND32 (cpu->regs[rs2]) == -1)
 	tmp = 0;
       else if (EXTEND32 (cpu->regs[rs2]))
 	tmp = EXTEND32 (cpu->regs[rs1]) % EXTEND32 (cpu->regs[rs2]);
-- 
2.7.4

Re: [PATCH 24/24] RISC-V sim: Fix divw and remw.

[Mike Frysinger]

On 17 Apr 2021 10:58, Jim Wilson wrote:
> According to spec, result is -2^31 only when divisor is -1 AND dividend
> is -2^31 for divw.
> According to spec, result is 0 only when divisor is -1 AND dividend
> is -2^31 for remw.

lgtm, but needs tests
-mike

Re: [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain.

[Mike Frysinger]

On 17 Apr 2021 10:58, Jim Wilson wrote:
> These are mostly patches extracted from riscv-gnu-toolchain with minor
> changes to apply to current FSF GDB sim.  I was careful to maintain the
> original author info, and the original commit logs when reasonable.
> There are also a few extra patches from me added in, as I noticed some
> problems when reviewing the patches, and debugging issues.  Note that
> Kito and Monk were at Andes when they wrote these patches, and are now
> at SiFive.  So this is mostly Andes work, and they should get credit
> for this work.  I kept their original email addresses even though they
> won't work anymore.  We will need permission from Andes to merge the
> patches into FSF GDB.  Hopefully Kuan-Lin can do that for us.  The patches
> from Palmer and myself were written at SiFive.

can you summarize author & company FSF assignments ?  we'd need those before
we could/should review anything from them.
-mike

Re: [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain.

[Jim Wilson]

On Sat, Apr 17, 2021 at 1:38 PM Mike Frysinger <vapier@gentoo.org> wrote:

> can you summarize author & company FSF assignments ?  we'd need those
> before
> we could/should review anything from them.
>

Everything was written by SiFive and Andes employees, and both have
corporate assignments that include gdb.

Jim

Re: [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain.

[Mike Frysinger]

On 18 Apr 2021 19:33, Jim Wilson wrote:
> On Sat, Apr 17, 2021 at 1:38 PM Mike Frysinger <vapier@gentoo.org> wrote:
> > can you summarize author & company FSF assignments ?  we'd need those
> > before
> > we could/should review anything from them.
> 
> Everything was written by SiFive and Andes employees, and both have
> corporate assignments that include gdb.

i don't follow this part then of your e-mail:
> We will need permission from Andes to merge the patches into FSF GDB.

if they have assignments in place, and the patches were released publicly,
then what is left ?
-mike

Re: [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain.

[Jim Wilson]

On Sun, Apr 18, 2021 at 8:23 PM Mike Frysinger <vapier@gentoo.org> wrote:

> i don't follow this part then of your e-mail:
> > We will need permission from Andes to merge the patches into FSF GDB.
>

Just because Andes has an assignment, doesn't mean that the code that they
write automatically becomes owned by the FSF.  They have to agree to the
copyright transfer.  This is implied when you submit a patch.  But this is
not implied if someone other than the author submits the patch.  So,
technically, I need permission from the original author (Andes) to submit
the code on their behalf.  Kuan-Lin has given that permission.  It is very
rare for this technicality to matter, but I'd rather be safe here.

I forgot one minor detail.  Palmer was at SiFive when he wrote the one
patch I included, but he is now at Google.  Since it is SiFive code I can
submit it.

Jim

Re: [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain.

[Mike Frysinger]

hmm, do you have push access ?  or do you need me to merge them ?
-mike

Re: [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain.

[Jim Wilson]

On Sun, Apr 18, 2021 at 8:42 PM Mike Frysinger <vapier@gentoo.org> wrote:

> hmm, do you have push access ?  or do you need me to merge them ?
>

I have write after approval access for gdb.  I'm also still listed as the
aarch64 sim maintainer, from back when I was at Linaro, which is why I
recently committed a patch for that.  But it is getting late here, so if
the patches have been approved I can commit them tomorrow.

Jim

Re: [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain.

[Andrew Burgess]

* Jim Wilson <jimw@sifive.com> [2021-04-17 10:58:07 -0700]:

> These are mostly patches extracted from riscv-gnu-toolchain with minor
> changes to apply to current FSF GDB sim.  I was careful to maintain the
> original author info, and the original commit logs when reasonable.

Maybe a silly question, but all of these authors do have an FSF
copyright assignment in place, right?  And they did all agree to pass
this code over to the FSF, right?

I don't think we can assume that just because an assignment is in
place they choose to give this code over to FSF, it would depend upon
the context in which they originally posted the code.

Thanks,
Andrew




> There are also a few extra patches from me added in, as I noticed some
> problems when reviewing the patches, and debugging issues.  Note that
> Kito and Monk were at Andes when they wrote these patches, and are now
> at SiFive.  So this is mostly Andes work, and they should get credit
> for this work.  I kept their original email addresses even though they
> won't work anymore.  We will need permission from Andes to merge the
> patches into FSF GDB.  Hopefully Kuan-Lin can do that for us.  The patches
> from Palmer and myself were written at SiFive.
> 
> I tested this with a gcc make check using riscv-gnu-toolchain and pulling
> in FSF GDB sim with my patches applied.  I get 13 gcc unexpected failures
> for rv32imac/ilp32 and 24 gcc unexpected failures for rv64gc/lp64d which
> matches the old simulator port in riscv-gnu-toolchain.  I did have one
> problem with the GNUC code in mulhu function producing the wrong result,
> but I think that is a bug in the Ubuntu 16.04 gcc-4.8 on my server.  If
> this is still broken with newer gcc versions I will take another look at
> that.
> 
> This code can probably use some cleanup.  I'd like to see the extensions
> in canonical arch order for instance.  But dealing with this many patches
> is unwieldy, and I wanted to retain the original authorship for the
> patches, so I'd rather do cleanup work as follow on patches.
> 
> Jim
> 
> Jim Wilson (6):
>   RISC-V sim: Fix fence.i.
>   RISC-V sim: More atomic fixes.
>   RISC-V sim: Fix ebreak, part 2.
>   RISC-V sim: Fix mingw builds.
>   RISC-V sim: Support compressed FP instructions.
>   RISC-V sim: Add zicsr support.
> 
> Kito Cheng (9):
>   RISC-V sim: Atomic fixes.
>   RISC-V sim: Fix syscall fallback.
>   RISC-V sim: Add csrr*i instructions.
>   RISC-V sim: Improve cycle and instret counts.
>   RISC-V sim: Check sbrk argument.
>   RISC-V sim: Improve branch tracing.
>   RISC-V sim: Improve tracing for slt* instructions.
>   RISC-V sim: Set brk to _end if possible.
>   RISC-V sim: Fix divw and remw.
> 
> Kuan-Lin Chen (5):
>   RISC-V sim: Fix stack pointer alignment.
>   RISC-V sim: Add link syscall support.
>   RISC-V sim: Add brk syscall.
>   RISC-V sim: Add gettimeofday.
>   RISC-V sim: Fix tracing typo.
> 
> Monk Chiang (3):
>   RISC-V: Add fp support.
>   RISC-V sim: Fix ebreak.
>   RISC-V sim: Add compressed support.
> 
> Palmer Dabbelt (1):
>   RISC-V sim: Fix for jalr.
> 
>  sim/riscv/interp.c   |   45 ++
>  sim/riscv/sim-main.c | 1790 ++++++++++++++++++++++++++++++++++++++++++++++----
>  sim/riscv/sim-main.h |   16 +-
>  3 files changed, 1733 insertions(+), 118 deletions(-)
> 
> -- 
> 2.7.4
> 

Re: [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain.

[Andrew Burgess]

* Andrew Burgess <andrew.burgess@embecosm.com> [2021-04-21 16:47:39 +0100]:

> * Jim Wilson <jimw@sifive.com> [2021-04-17 10:58:07 -0700]:
> 
> > These are mostly patches extracted from riscv-gnu-toolchain with minor
> > changes to apply to current FSF GDB sim.  I was careful to maintain the
> > original author info, and the original commit logs when reasonable.
> 
> Maybe a silly question, but all of these authors do have an FSF
> copyright assignment in place, right?  And they did all agree to pass
> this code over to the FSF, right?
> 
> I don't think we can assume that just because an assignment is in
> place they choose to give this code over to FSF, it would depend upon
> the context in which they originally posted the code.

OK, I realise you actually already addressed this point.  I don't know
how I didn't see this given it was on the very next line.

Apologies for the noise - it's been a long day :(

Thanks,
Andrew


> 
> Thanks,
> Andrew
> 
> 
> 
> 
> > There are also a few extra patches from me added in, as I noticed some
> > problems when reviewing the patches, and debugging issues.  Note that
> > Kito and Monk were at Andes when they wrote these patches, and are now
> > at SiFive.  So this is mostly Andes work, and they should get credit
> > for this work.  I kept their original email addresses even though they
> > won't work anymore.  We will need permission from Andes to merge the
> > patches into FSF GDB.  Hopefully Kuan-Lin can do that for us.  The patches
> > from Palmer and myself were written at SiFive.
> > 
> > I tested this with a gcc make check using riscv-gnu-toolchain and pulling
> > in FSF GDB sim with my patches applied.  I get 13 gcc unexpected failures
> > for rv32imac/ilp32 and 24 gcc unexpected failures for rv64gc/lp64d which
> > matches the old simulator port in riscv-gnu-toolchain.  I did have one
> > problem with the GNUC code in mulhu function producing the wrong result,
> > but I think that is a bug in the Ubuntu 16.04 gcc-4.8 on my server.  If
> > this is still broken with newer gcc versions I will take another look at
> > that.
> > 
> > This code can probably use some cleanup.  I'd like to see the extensions
> > in canonical arch order for instance.  But dealing with this many patches
> > is unwieldy, and I wanted to retain the original authorship for the
> > patches, so I'd rather do cleanup work as follow on patches.
> > 
> > Jim
> > 
> > Jim Wilson (6):
> >   RISC-V sim: Fix fence.i.
> >   RISC-V sim: More atomic fixes.
> >   RISC-V sim: Fix ebreak, part 2.
> >   RISC-V sim: Fix mingw builds.
> >   RISC-V sim: Support compressed FP instructions.
> >   RISC-V sim: Add zicsr support.
> > 
> > Kito Cheng (9):
> >   RISC-V sim: Atomic fixes.
> >   RISC-V sim: Fix syscall fallback.
> >   RISC-V sim: Add csrr*i instructions.
> >   RISC-V sim: Improve cycle and instret counts.
> >   RISC-V sim: Check sbrk argument.
> >   RISC-V sim: Improve branch tracing.
> >   RISC-V sim: Improve tracing for slt* instructions.
> >   RISC-V sim: Set brk to _end if possible.
> >   RISC-V sim: Fix divw and remw.
> > 
> > Kuan-Lin Chen (5):
> >   RISC-V sim: Fix stack pointer alignment.
> >   RISC-V sim: Add link syscall support.
> >   RISC-V sim: Add brk syscall.
> >   RISC-V sim: Add gettimeofday.
> >   RISC-V sim: Fix tracing typo.
> > 
> > Monk Chiang (3):
> >   RISC-V: Add fp support.
> >   RISC-V sim: Fix ebreak.
> >   RISC-V sim: Add compressed support.
> > 
> > Palmer Dabbelt (1):
> >   RISC-V sim: Fix for jalr.
> > 
> >  sim/riscv/interp.c   |   45 ++
> >  sim/riscv/sim-main.c | 1790 ++++++++++++++++++++++++++++++++++++++++++++++----
> >  sim/riscv/sim-main.h |   16 +-
> >  3 files changed, 1733 insertions(+), 118 deletions(-)
> > 
> > -- 
> > 2.7.4
> > 

RE: [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain.

[rufus]

On 19 Apr 2021 02:33, Jim Wilson wrote:
> Everything was written by SiFive and Andes employees, and both have
> corporate assignments that include gdb.

Behalf of Andes tech, I am OK with this patch set.
Thanks, Jim.
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