From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 54160 invoked by alias); 16 Jul 2018 22:01:46 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 54148 invoked by uid 89); 16 Jul 2018 22:01:45 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.0 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-wm0-f67.google.com Received: from mail-wm0-f67.google.com (HELO mail-wm0-f67.google.com) (74.125.82.67) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 16 Jul 2018 22:01:44 +0000 Received: by mail-wm0-f67.google.com with SMTP id s14-v6so17348211wmc.1 for ; Mon, 16 Jul 2018 15:01:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=od37lOYJ2lJdbV8QPX/zWGyup8ijqv7JxACgCFIX6+U=; b=czB29TKwcA7W5WR9+pP6ZNp9CvAAkyVlCn0CcgjYM8Et3JQ+qzKHnx4ZZwufdOZ04F C2N4c61rV7Dz750POosB1LYBpNWxrtG7BOUDNkVSVri4ZjOMqfwEmpG1W4SfBrZGNyMb P6H9JcBRXxSuxsEsqQuHnFdaxc+anArrcxgu900VKHyq84NrYGTN5vw1R0Aq9hy0v2ns mQ9sOcnX5Cd+LlA5amh2n8LIcPA7PJorc/0EtPEIqcGnkSF/rofQyDTrF7wIzsaA6VOx 2tbRnQmy2i5FABWv6HN5Oy6vgQe3dGEYLvlwYPYvOIDfPN9M638L+GgOKEKB7ItOyzct /2ug== MIME-Version: 1.0 Received: by 2002:adf:e44b:0:0:0:0:0 with HTTP; Mon, 16 Jul 2018 15:01:41 -0700 (PDT) In-Reply-To: <20180704083410.GD2675@embecosm.com> References: <20180704001334.27460-1-jimw@sifive.com> <20180704083410.GD2675@embecosm.com> From: Jim Wilson Date: Mon, 16 Jul 2018 22:01:00 -0000 Message-ID: Subject: Re: [PATCH] RISC-V: Correct legacy misa register number. To: Andrew Burgess Cc: gdb-patches@sourceware.org Content-Type: text/plain; charset="UTF-8" X-SW-Source: 2018-07/txt/msg00504.txt.bz2 On Wed, Jul 4, 2018 at 1:34 AM, Andrew Burgess wrote: > * Jim Wilson [2018-07-03 17:13:34 -0700]: > >> The main purpose of this patch is to fix the legacy misa register number, which >> is missing the +65 added to all of the other CSRs. >> >> This also changes DECLARE_CSR to use RISCV_FIRST_CSR_REGNUM instead of >> RISCV_LAST_FP_REGNUM+1 to be consistent with riscv-tdep.c. >> >> I don't have access to legacy hardware that I can test the misa number change >> with, but it has been tested on a riscv64-linux system using patched gdb and >> patched kernel, since it isn't usable otherwise. >> >> Jim >> >> gdb/ >> * riscv-tdep.h (DECLARE_CSR): Use RISCV_FIRST_CSR_REGNUM instead of >> RISCV_LAST_FP_REGNUM + 1. >> (RSICV_CSR_LEGACY_MISA_REGNUM): Add RISCV_FIRST_CSR_REGNUM. > > Regardless of the discussion about RISCV_CSR_LEGACY_MISA_REGNUM > could you push the change to DECLARE_CSR anyway please. I think this > is a good clean up and it's unrelated to the other change. Tim Newsome confirmed that there should be no special behavior in OpenOCD to handle the legacy misa register number. I'd like approval to commit the whole patch. It is a bug fix for live code, and a minor consistency cleanup. Jim