From: Nelson Chu <nelson.chu@sifive.com>
To: Binutils <binutils@sourceware.org>, gdb-patches@sourceware.org
Cc: Andrew Burgess <andrew.burgess@embecosm.com>,
Andrew Waterman <andrew@sifive.com>,
asb@lowrisc.org, Kito Cheng <kito.cheng@sifive.com>,
Maxim Blinov <maxim.blinov@embecosm.com>,
Jim Wilson <jimw@sifive.com>,
Palmer Dabbelt <palmerdabbelt@google.com>
Subject: Re: [PATCH 6/7] RISC-V: Disassembler dumps the CSR according to the chosen privilege spec.
Date: Sat, 18 Apr 2020 19:18:58 +0800 [thread overview]
Message-ID: <CAJYME4HExjEB4ohz7fu8+yS2qvGwiNz1_yR+1aTaSwG+pS7oZA@mail.gmail.com> (raw)
In-Reply-To: <1587208075-2462-7-git-send-email-nelson.chu@sifive.com>
CC Palmer.
Thanks
Nelson
On Sat, Apr 18, 2020 at 7:08 PM Nelson Chu <nelson.chu@sifive.com> wrote:
>
> Add new disassembler option -Mpriv-spec=[1p9|1p9p1|1p10|1p11] to dump the CSR
> correctly. Report error message if the chosen priv version isn't supported.
> Dump the CSR address direclty if it is invalid for the chosen spec.
>
> gas/
> * config/tc-riscv.c: Remove the static for default_priv_spec, and move
> it to opcodes/riscv-opc.c.
>
> * testsuite/gas/riscv/priv-reg.d: Removed.
> * testsuite/gas/riscv/priv-reg-version-1p9.d: New test case. Dump the
> CSR according to the priv spec 1p9.
> * testsuite/gas/riscv/priv-reg-version-1p9p1.d: New test case. Dump the
> CSR according to the priv spec 1p9p1.
> * testsuite/gas/riscv/priv-reg-version-1p10.d: New test case. Dump the
> CSR according to the priv spec 1p10.
> * testsuite/gas/riscv/priv-reg-version-1p11.d: New test case. Dump the
> CSR according to the priv spec 1p11.
>
> include/
> * opcode/riscv.h: Updated.
>
> opcodes/
> * riscv-opc.c: Updated.
> * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
> according to the chosen version. Build a hash table riscv_csr_hash to
> store the valid CSR for the chosen pirv verison. Dump the direct
> CSR address rather than it's name if it is invalid.
> (parse_riscv_dis_option_without_args): New function. Parse the options
> without arguments.
> (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
> parse the options without arguments first, and then handle the options
> with arguments. Add the new option -Mpriv-spec, which has argument.
> ---
> gas/config/tc-riscv.c | 1 -
> gas/testsuite/gas/riscv/priv-reg-version-1p10.d | 257 +++++++++++++++++++++++
> gas/testsuite/gas/riscv/priv-reg-version-1p11.d | 257 +++++++++++++++++++++++
> gas/testsuite/gas/riscv/priv-reg-version-1p9.d | 257 +++++++++++++++++++++++
> gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d | 257 +++++++++++++++++++++++
> gas/testsuite/gas/riscv/priv-reg.d | 256 ----------------------
> include/opcode/riscv.h | 2 +
> opcodes/riscv-dis.c | 67 +++++-
> opcodes/riscv-opc.c | 2 +
> 9 files changed, 1092 insertions(+), 264 deletions(-)
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p10.d
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p11.d
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p9.d
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
> delete mode 100644 gas/testsuite/gas/riscv/priv-reg.d
>
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index 9ce9046..81bdfa8 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -83,7 +83,6 @@ static const char default_arch[] = DEFAULT_ARCH;
> static const char *default_arch_with_ext = DEFAULT_ARCH_WITH_EXT;
> static const char *default_isa_spec = DEFAULT_ISA_SPEC;
> static const char *default_riscv_isa_version = DEFAULT_RISCV_ISA_VERSION;
> -static enum riscv_csr_vclass default_priv_spec = CSR_CLASS_VNONE;
>
> static unsigned xlen = 0; /* width of an x-register */
> static unsigned abi_xlen = 0; /* width of a pointer in the ABI */
> diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
> new file mode 100644
> index 0000000..3c369f4
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
> @@ -0,0 +1,257 @@
> +#as: -march=rv32if -mpriv-spec=1p10
> +#source: priv-reg.s
> +#objdump: -dr -Mpriv-spec=1p10
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <.text>:
> +[ ]+[0-9a-f]+:[ ]+00002573[ ]+csrr[ ]+a0,ustatus
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> diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
> new file mode 100644
> index 0000000..1196c80
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
> @@ -0,0 +1,257 @@
> +#as: -march=rv32if -mpriv-spec=1p11
> +#source: priv-reg.s
> +#objdump: -dr -Mpriv-spec=1p11
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <.text>:
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> diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p9.d b/gas/testsuite/gas/riscv/priv-reg-version-1p9.d
> new file mode 100644
> index 0000000..1b5a5a7
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-version-1p9.d
> @@ -0,0 +1,257 @@
> +#as: -march=rv32if -mpriv-spec=1p9
> +#source: priv-reg.s
> +#objdump: -dr -Mpriv-spec=1p9
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <.text>:
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> diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
> new file mode 100644
> index 0000000..5affc54
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
> @@ -0,0 +1,257 @@
> +#as: -march=rv32if -mpriv-spec=1p9p1
> +#source: priv-reg.s
> +#objdump: -dr -Mpriv-spec=1p9p1
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <.text>:
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> diff --git a/gas/testsuite/gas/riscv/priv-reg.d b/gas/testsuite/gas/riscv/priv-reg.d
> deleted file mode 100644
> index 8fc41d2..0000000
> --- a/gas/testsuite/gas/riscv/priv-reg.d
> +++ /dev/null
> @@ -1,256 +0,0 @@
> -#as: -march=rv32if
> -#objdump: -dr
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <.text>:
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> -[ ]+[0-9a-f]+:[ ]+b0702573[ ]+csrr[ ]+a0,mhpmcounter7
> -[ ]+[0-9a-f]+:[ ]+b0802573[ ]+csrr[ ]+a0,mhpmcounter8
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> -[ ]+[0-9a-f]+:[ ]+b1002573[ ]+csrr[ ]+a0,mhpmcounter16
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> -[ ]+[0-9a-f]+:[ ]+b1902573[ ]+csrr[ ]+a0,mhpmcounter25
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> -[ ]+[0-9a-f]+:[ ]+b1f02573[ ]+csrr[ ]+a0,mhpmcounter31
> -[ ]+[0-9a-f]+:[ ]+b8002573[ ]+csrr[ ]+a0,mcycleh
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> -[ ]+[0-9a-f]+:[ ]+b8402573[ ]+csrr[ ]+a0,mhpmcounter4h
> -[ ]+[0-9a-f]+:[ ]+b8502573[ ]+csrr[ ]+a0,mhpmcounter5h
> -[ ]+[0-9a-f]+:[ ]+b8602573[ ]+csrr[ ]+a0,mhpmcounter6h
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> -[ ]+[0-9a-f]+:[ ]+b9902573[ ]+csrr[ ]+a0,mhpmcounter25h
> -[ ]+[0-9a-f]+:[ ]+b9a02573[ ]+csrr[ ]+a0,mhpmcounter26h
> -[ ]+[0-9a-f]+:[ ]+b9b02573[ ]+csrr[ ]+a0,mhpmcounter27h
> -[ ]+[0-9a-f]+:[ ]+b9c02573[ ]+csrr[ ]+a0,mhpmcounter28h
> -[ ]+[0-9a-f]+:[ ]+b9d02573[ ]+csrr[ ]+a0,mhpmcounter29h
> -[ ]+[0-9a-f]+:[ ]+b9e02573[ ]+csrr[ ]+a0,mhpmcounter30h
> -[ ]+[0-9a-f]+:[ ]+b9f02573[ ]+csrr[ ]+a0,mhpmcounter31h
> -[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mcountinhibit
> -[ ]+[0-9a-f]+:[ ]+32302573[ ]+csrr[ ]+a0,mhpmevent3
> -[ ]+[0-9a-f]+:[ ]+32402573[ ]+csrr[ ]+a0,mhpmevent4
> -[ ]+[0-9a-f]+:[ ]+32502573[ ]+csrr[ ]+a0,mhpmevent5
> -[ ]+[0-9a-f]+:[ ]+32602573[ ]+csrr[ ]+a0,mhpmevent6
> -[ ]+[0-9a-f]+:[ ]+32702573[ ]+csrr[ ]+a0,mhpmevent7
> -[ ]+[0-9a-f]+:[ ]+32802573[ ]+csrr[ ]+a0,mhpmevent8
> -[ ]+[0-9a-f]+:[ ]+32902573[ ]+csrr[ ]+a0,mhpmevent9
> -[ ]+[0-9a-f]+:[ ]+32a02573[ ]+csrr[ ]+a0,mhpmevent10
> -[ ]+[0-9a-f]+:[ ]+32b02573[ ]+csrr[ ]+a0,mhpmevent11
> -[ ]+[0-9a-f]+:[ ]+32c02573[ ]+csrr[ ]+a0,mhpmevent12
> -[ ]+[0-9a-f]+:[ ]+32d02573[ ]+csrr[ ]+a0,mhpmevent13
> -[ ]+[0-9a-f]+:[ ]+32e02573[ ]+csrr[ ]+a0,mhpmevent14
> -[ ]+[0-9a-f]+:[ ]+32f02573[ ]+csrr[ ]+a0,mhpmevent15
> -[ ]+[0-9a-f]+:[ ]+33002573[ ]+csrr[ ]+a0,mhpmevent16
> -[ ]+[0-9a-f]+:[ ]+33102573[ ]+csrr[ ]+a0,mhpmevent17
> -[ ]+[0-9a-f]+:[ ]+33202573[ ]+csrr[ ]+a0,mhpmevent18
> -[ ]+[0-9a-f]+:[ ]+33302573[ ]+csrr[ ]+a0,mhpmevent19
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> -[ ]+[0-9a-f]+:[ ]+33502573[ ]+csrr[ ]+a0,mhpmevent21
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> -[ ]+[0-9a-f]+:[ ]+33b02573[ ]+csrr[ ]+a0,mhpmevent27
> -[ ]+[0-9a-f]+:[ ]+33c02573[ ]+csrr[ ]+a0,mhpmevent28
> -[ ]+[0-9a-f]+:[ ]+33d02573[ ]+csrr[ ]+a0,mhpmevent29
> -[ ]+[0-9a-f]+:[ ]+33e02573[ ]+csrr[ ]+a0,mhpmevent30
> -[ ]+[0-9a-f]+:[ ]+33f02573[ ]+csrr[ ]+a0,mhpmevent31
> -[ ]+[0-9a-f]+:[ ]+7a002573[ ]+csrr[ ]+a0,tselect
> -[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
> -[ ]+[0-9a-f]+:[ ]+7a202573[ ]+csrr[ ]+a0,tdata2
> -[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
> -[ ]+[0-9a-f]+:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
> -[ ]+[0-9a-f]+:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
> -[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
> -[ ]+[0-9a-f]+:[ ]+7b302573[ ]+csrr[ ]+a0,dscratch1
> -[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,utval
> -[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,stval
> -[ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,satp
> -[ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mtval
> -[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mcountinhibit
> -[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
> -[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,hstatus
> -[ ]+[0-9a-f]+:[ ]+20202573[ ]+csrr[ ]+a0,hedeleg
> -[ ]+[0-9a-f]+:[ ]+20302573[ ]+csrr[ ]+a0,hideleg
> -[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,hie
> -[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,htvec
> -[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,hscratch
> -[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,hepc
> -[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,hcause
> -[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,hbadaddr
> -[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,hip
> -[ ]+[0-9a-f]+:[ ]+38002573[ ]+csrr[ ]+a0,mbase
> -[ ]+[0-9a-f]+:[ ]+38102573[ ]+csrr[ ]+a0,mbound
> -[ ]+[0-9a-f]+:[ ]+38202573[ ]+csrr[ ]+a0,mibase
> -[ ]+[0-9a-f]+:[ ]+38302573[ ]+csrr[ ]+a0,mibound
> -[ ]+[0-9a-f]+:[ ]+38402573[ ]+csrr[ ]+a0,mdbase
> -[ ]+[0-9a-f]+:[ ]+38502573[ ]+csrr[ ]+a0,mdbound
> -[ ]+[0-9a-f]+:[ ]+32102573[ ]+csrr[ ]+a0,mscounteren
> -[ ]+[0-9a-f]+:[ ]+32202573[ ]+csrr[ ]+a0,mhcounteren
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index c36bf69..0f263ab 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -446,6 +446,8 @@ extern const struct riscv_opcode riscv_opcodes[];
> extern const struct riscv_opcode riscv_insn_types[];
> extern const struct riscv_ext_version riscv_ext_version_table[];
>
> +extern enum riscv_csr_vclass default_priv_spec;
> +
> extern bfd_boolean
> riscv_get_priv_version_class (const char *, enum riscv_csr_vclass *);
> extern const char *
> diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
> index 98302ff..38ae8ac 100644
> --- a/opcodes/riscv-dis.c
> +++ b/opcodes/riscv-dis.c
> @@ -52,8 +52,8 @@ set_default_riscv_dis_options (void)
> no_aliases = 0;
> }
>
> -static void
> -parse_riscv_dis_option (const char *option)
> +static bfd_boolean
> +parse_riscv_dis_option_without_args (const char *option)
> {
> if (strcmp (option, "no-aliases") == 0)
> no_aliases = 1;
> @@ -63,6 +63,44 @@ parse_riscv_dis_option (const char *option)
> riscv_fpr_names = riscv_fpr_names_numeric;
> }
> else
> + return FALSE;
> + return TRUE;
> +}
> +
> +static void
> +parse_riscv_dis_option (const char *option)
> +{
> + char *equal, *value;
> +
> + if (parse_riscv_dis_option_without_args (option))
> + return;
> +
> + equal = strchr (option, '=');
> + if (equal == NULL)
> + {
> + /* The option without '=' should be defined above. */
> + opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
> + return;
> + }
> + if (equal == option
> + || *(equal + 1) == '\0')
> + {
> + /* Invalid options with '=', no option name before '=',
> + and no value after '='. */
> + opcodes_error_handler (_("unrecognized disassembler option with '=': %s"),
> + option);
> + return;
> + }
> +
> + *equal = '\0';
> + value = equal + 1;
> + if (strcmp (option, "priv-spec") == 0)
> + {
> + if (!riscv_get_priv_version_class (value, &default_priv_spec))
> + opcodes_error_handler (_("unsupported privilege version set by %s=%s"),
> + option, value);
> + }
> + else
> {
> /* xgettext:c-format */
> opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
> @@ -322,17 +360,32 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
>
> case 'E':
> {
> - const char* csr_name = NULL;
> + static const char *riscv_csr_hash[4096]; /* Total 2^12 CSR */
> + static bfd_boolean init_csr = FALSE;
> unsigned int csr = EXTRACT_OPERAND (CSR, l);
> - switch (csr)
> +
> + if (!init_csr)
> {
> + unsigned int i;
> + for (i = 0; i < 4096; i++)
> + riscv_csr_hash[i] = NULL;
> +
> + /* Set to the newest privilege version. */
> + if (default_priv_spec == CSR_CLASS_VNONE)
> + default_priv_spec = CSR_CLASS_VDRAFT - 1;
> +
> #define DECLARE_CSR(name, num, class, define_version, abort_version) \
> - case num: csr_name = #name; break;
> + if (default_priv_spec >= define_version \
> + && default_priv_spec < abort_version) \
> + riscv_csr_hash[num] = #name;
> +#define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
> + DECLARE_CSR(name, num, class, define_version, abort_version)
> #include "opcode/riscv-opc.h"
> #undef DECLARE_CSR
> }
> - if (csr_name)
> - print (info->stream, "%s", csr_name);
> +
> + if (riscv_csr_hash[csr] != NULL)
> + print (info->stream, "%s", riscv_csr_hash[csr]);
> else
> print (info->stream, "0x%x", csr);
> break;
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index cfefd8e..ad568bb 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -938,6 +938,8 @@ const struct riscv_ext_version riscv_ext_version_table[] =
> {NULL, NULL, 0, 0}
> };
>
> +enum riscv_csr_vclass default_priv_spec = CSR_CLASS_VNONE;
> +
> struct priv_version_t
> {
> const char *name;
> --
> 2.7.4
>
next prev parent reply other threads:[~2020-04-18 11:19 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-18 11:07 [PATCH 0/7] RISC-V: Support version controling for ISA standard extensions and CSR Nelson Chu
2020-04-18 11:07 ` [PATCH 1/7] RISC-V: Remove the redundant gas test file Nelson Chu
2020-04-18 11:17 ` Nelson Chu
2020-04-18 11:20 ` Nelson Chu
2020-04-18 11:07 ` [PATCH 2/7] RISC-V: Forgot to update the priv-reg-fail-read-only-01 test case Nelson Chu
2020-04-18 11:17 ` Nelson Chu
2020-04-18 11:07 ` [PATCH 3/7] RISC-V: Support new GAS options and configure options to set ISA versions Nelson Chu
2020-04-18 11:18 ` Nelson Chu
2020-04-23 22:58 ` Palmer Dabbelt
2020-04-24 2:37 ` Nelson Chu
2020-04-24 6:43 ` Nelson Chu
2020-04-18 11:07 ` [PATCH 4/7] RISC-V: Support version checking for CSR according to privilege version Nelson Chu
2020-04-18 11:18 ` Nelson Chu
2020-04-24 10:21 ` Andrew Burgess
2020-04-27 1:35 ` Nelson Chu
2020-04-18 11:07 ` [PATCH 5/7] RISC-V: Make privilege spec attributes work Nelson Chu
2020-04-18 11:18 ` Nelson Chu
2020-04-18 11:07 ` [PATCH 6/7] RISC-V: Disassembler dumps the CSR according to the chosen privilege spec Nelson Chu
2020-04-18 11:18 ` Nelson Chu [this message]
2020-04-18 11:07 ` [PATCH 7/7] RISC-V: Add documents and --help for the new GAS and OBJDUMP options Nelson Chu
2020-04-18 11:19 ` Nelson Chu
2020-04-18 11:17 ` [PATCH 0/7] RISC-V: Support version controling for ISA standard extensions and CSR Nelson Chu
2020-04-23 20:59 ` Palmer Dabbelt
2020-04-30 16:10 ` Kito Cheng
2020-05-01 9:29 ` Nelson Chu
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