From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yb1-xb35.google.com (mail-yb1-xb35.google.com [IPv6:2607:f8b0:4864:20::b35]) by sourceware.org (Postfix) with ESMTPS id 732DF3858D1E for ; Wed, 20 Mar 2024 11:13:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 732DF3858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 732DF3858D1E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::b35 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1710933206; cv=none; b=I126QUmC2LH9YYqOnxNUFhdABgm9ld8tUxK7lbwS7BGNMzIS0hwFvY8eeZZB7BdX9YT5IGP6bgSKfSzNSQsZ+oQItex9M4ThyoEYrFMIIBIR9mymLm9olMCa2iXD6DTVoHf257F0DWQzfozdQB0/jWwBuMmX2riYc7Zl5Sa/Ojg= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1710933206; c=relaxed/simple; bh=rs866O8PspYZ9Yoi8PGMdZxXCZbNko9BpTsS+3IR40k=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=dw+u0/+DApTk9SzX1EbMJbZ1LWA1tqvdNh8s3MepK+UkdvxQUboO21mEfJdtJ5S64Lupf0wS6AmTabq9VwyDiV1HUZIFkruxRlj4nWlllxHbb2foQn/jx+qned9cahVgnTeO2SJMZdvaSp2vQ+gQAtrBt6fwJDrUbj53S7TZ7hw= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-yb1-xb35.google.com with SMTP id 3f1490d57ef6-dc236729a2bso6286155276.0 for ; Wed, 20 Mar 2024 04:13:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1710933201; x=1711538001; darn=sourceware.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=FIsccuTcWuaxrXCoxe8URzxnwbDfzNxZlyI9V+Ghb7g=; b=F/8rDRWCyKkbQyun6ngO3B6TQj7csBG6tt2pUNBFq6ryDJAxPIZpJJKn+jaOZ3vti+ kH3Jkp0hkGEBoIMyzfMGRq11rUFauyqSUOebKg5sLrd+b0s8yIHT6Jfovzatqye1DFbn bfhsrVezP+68d7qeizVMtji9D6FlVLiN6UKGGsgE3kuiys74ZbqBJQZz3Slg31k4CUsf ZaJEA/9OBKwj+M3jiSzBQo1+tdqaEdH8Q6fuO7euXfMCaUvrT+/o8ZtsZOut6XNZy5QD oqfafsMMjx4FZ1vt6FmyCLi49sQs1UEBe0Nf+XjtHcS6QTmzetdBvRAFcvehJnv0JxCo Ir9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710933201; x=1711538001; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FIsccuTcWuaxrXCoxe8URzxnwbDfzNxZlyI9V+Ghb7g=; b=vXsT0RT/MZZUx43Kgs5NdCRUD9g6S9D8mgVdlqChzJGThkOTm9NWmIRZ5DXDeHDyWB 4D/K96W6DVD3jFMpgIYeRmDtUkg1xZ7EwoCDFiLUmtvmajdQkdGwGiQMQc/4Ingk5k2Y O0JUdlTYRcqQVH2kHAob5mA5q70nx9EkVshJaUDQ19SAhKolrXoAVb4DawK6DvWmn2Oi tMlXafodjeaDGm9PtIzF0pDz9C89XLoiB8S65zKmM/ca/ALyGUMQKIHTuHtl7PUindS5 E6IwpBToq6mzhATKSj0VUT3+G70VS9DtrNqu8c4CcE0DdNZTjCtH1KDkIq+qtKcY3zfF a6Eg== X-Gm-Message-State: AOJu0YzlXndFyvc/d/Xvtyq2kqxnBrTSOIuZ20T+IqAC/JkJsImr1mCR uOwIcQUMSHgVeKfMwqeg6ujOE0E/GHxhglR9y/+ebpCkHJK9Arn+ifzeQesQWQ7kX0hb+5wpqNp EdkrXi7vHTWDkFWky6/9WUpO5KsEXDIVG X-Google-Smtp-Source: AGHT+IGrqx40Y7+sntVGMNApFm6Qi1nsEk3WmUBFBpgTT7Z3eHNi9JpVzBVWjNHmiYBawbaLSrsjRicyA5zpEJrDhzo= X-Received: by 2002:a25:c509:0:b0:dc7:32e5:a707 with SMTP id v9-20020a25c509000000b00dc732e5a707mr15035761ybe.61.1710933201085; Wed, 20 Mar 2024 04:13:21 -0700 (PDT) MIME-Version: 1.0 References: <20240320104703.117257-1-hjl.tools@gmail.com> In-Reply-To: <20240320104703.117257-1-hjl.tools@gmail.com> From: "H.J. Lu" Date: Wed, 20 Mar 2024 04:12:45 -0700 Message-ID: Subject: Re: [PATCH v2] Fix GDB: Initial r16-r31 support for Intel APX To: gdb-patches@sourceware.org Cc: felix.willgerodt@intel.com, jhb@freebsd.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-3019.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, Mar 20, 2024 at 3:47=E2=80=AFAM H.J. Lu wrote= : > > --- > gdb/amd64-tdep.c | 58 ++++++++++++++++++++++++++++++------------------ > gdb/i386-tdep.h | 6 ++++- > 2 files changed, 41 insertions(+), 23 deletions(-) > > diff --git a/gdb/amd64-tdep.c b/gdb/amd64-tdep.c > index 9b641ea3ab6..786c9dd1db4 100644 > --- a/gdb/amd64-tdep.c > +++ b/gdb/amd64-tdep.c > @@ -467,15 +467,27 @@ amd64_pseudo_register_name (struct gdbarch *gdbarch= , int regnum) > return i386_pseudo_register_name (gdbarch, regnum); > } > > -/* Convert the raw APX register number to the register number relative > - to r16. NUM_BASE_REGS is the number of registers without APX. */ > +/* Convert the APX byte and word register number to the register number > + relative to r16. */ > > static int > -amd64_apx_raw_register (i386_gdbarch_tdep *tdep, int gpnum, > - int num_base_regs) > +amd64_apx_byte_word_register (i386_gdbarch_tdep *tdep, int gpnum) > { > - if (gpnum >=3D num_base_regs) > - gpnum +=3D tdep->r16_regnum - num_base_regs; > + if (gpnum >=3D 16) > + gpnum +=3D tdep->r16_regnum - 16; > + return gpnum; > +} > + > +/* Convert the APX dword register number to the register number relative > + to r16. For x32, the last dword register is EIP. */ > + > +static int > +amd64_apx_dword_register (i386_gdbarch_tdep *tdep, int gpnum) > +{ > + if (tdep->eip_regnum =3D=3D gpnum) > + return AMD64_RIP_REGNUM; > + if (gpnum >=3D 16) > + gpnum +=3D tdep->r16_regnum - 16; > return gpnum; > } > > @@ -499,21 +511,20 @@ amd64_pseudo_register_read_value (gdbarch *gdbarch,= const frame_info_ptr &next_f > } > else > { > - gpnum =3D amd64_apx_raw_register (tdep, gpnum, > - tdep->num_byte_regs); > + gpnum =3D amd64_apx_byte_word_register (tdep, gpnum); > return pseudo_from_raw_part (next_frame, regnum, gpnum, 0); > } > } > else if (i386_word_regnum_p (gdbarch, regnum)) > { > int gpnum =3D regnum - tdep->ax_regnum; > - gpnum =3D amd64_apx_raw_register (tdep, gpnum, tdep->num_word_regs= ); > + gpnum =3D amd64_apx_byte_word_register (tdep, gpnum); > return pseudo_from_raw_part (next_frame, regnum, gpnum, 0); > } > else if (i386_dword_regnum_p (gdbarch, regnum)) > { > int gpnum =3D regnum - tdep->eax_regnum; > - gpnum =3D amd64_apx_raw_register (tdep, gpnum, tdep->num_dword_reg= s); > + gpnum =3D amd64_apx_dword_register (tdep, gpnum); > return pseudo_from_raw_part (next_frame, regnum, gpnum, 0); > } > else > @@ -537,21 +548,20 @@ amd64_pseudo_register_write (gdbarch *gdbarch, cons= t frame_info_ptr &next_frame, > } > else > { > - gpnum =3D amd64_apx_raw_register (tdep, gpnum, > - tdep->num_byte_regs); > + gpnum =3D amd64_apx_byte_word_register (tdep, gpnum); > pseudo_to_raw_part (next_frame, buf, gpnum, 0); > } > } > else if (i386_word_regnum_p (gdbarch, regnum)) > { > int gpnum =3D regnum - tdep->ax_regnum; > - gpnum =3D amd64_apx_raw_register (tdep, gpnum, tdep->num_word_regs= ); > + gpnum =3D amd64_apx_byte_word_register (tdep, gpnum); > pseudo_to_raw_part (next_frame, buf, gpnum, 0); > } > else if (i386_dword_regnum_p (gdbarch, regnum)) > { > int gpnum =3D regnum - tdep->eax_regnum; > - gpnum =3D amd64_apx_raw_register (tdep, gpnum, tdep->num_dword_reg= s); > + gpnum =3D amd64_apx_dword_register (tdep, gpnum); > pseudo_to_raw_part (next_frame, buf, gpnum, 0); > } > else > @@ -574,8 +584,7 @@ amd64_ax_pseudo_register_collect (struct gdbarch *gdb= arch, > ax_reg_mask (ax, gpnum - tdep->num_lower_byte_regs); > else > { > - gpnum =3D amd64_apx_raw_register (tdep, gpnum, > - tdep->num_byte_regs); > + gpnum =3D amd64_apx_byte_word_register (tdep, gpnum); > ax_reg_mask (ax, gpnum); > } > return 0; > @@ -583,14 +592,14 @@ amd64_ax_pseudo_register_collect (struct gdbarch *g= dbarch, > else if (i386_word_regnum_p (gdbarch, regnum)) > { > int gpnum =3D regnum - tdep->ax_regnum; > - gpnum =3D amd64_apx_raw_register (tdep, gpnum, tdep->num_word_regs= ); > + gpnum =3D amd64_apx_byte_word_register (tdep, gpnum); > ax_reg_mask (ax, gpnum); > return 0; > } > else if (i386_dword_regnum_p (gdbarch, regnum)) > { > int gpnum =3D regnum - tdep->eax_regnum; > - gpnum =3D amd64_apx_raw_register (tdep, gpnum, tdep->num_dword_reg= s); > + gpnum =3D amd64_apx_dword_register (tdep, gpnum); > ax_reg_mask (ax, gpnum); > return 0; > } > @@ -3498,14 +3507,17 @@ static struct type * > amd64_x32_pseudo_register_type (struct gdbarch *gdbarch, int regnum) > { > i386_gdbarch_tdep *tdep =3D gdbarch_tdep (gdbarch); > + int gpnum =3D regnum - tdep->eax_regnum; > + > + /* %eip */ > + if (gpnum =3D=3D tdep->eip_regnum) > + return builtin_type (gdbarch)->builtin_func_ptr; > > - switch (regnum - tdep->eax_regnum) > + switch (gpnum) > { > case AMD64_RBP_REGNUM: /* %ebp */ > case AMD64_RSP_REGNUM: /* %esp */ > return builtin_type (gdbarch)->builtin_data_ptr; > - case AMD64_RIP_REGNUM: /* %eip */ > - return builtin_type (gdbarch)->builtin_func_ptr; > } > > return i386_pseudo_register_type (gdbarch, regnum); > @@ -3519,7 +3531,9 @@ amd64_x32_init_abi (struct gdbarch_info info, struc= t gdbarch *gdbarch, > > amd64_init_abi (info, gdbarch, default_tdesc); > > - /* Increment 1 for EIP. */ > + /* Set %eip to the last dword register. */ > + tdep->eip_regnum =3D tdep->num_dword_regs; > + /* Increment 1 for %eip. */ > tdep->num_dword_regs +=3D 1; > set_tdesc_pseudo_register_type (gdbarch, amd64_x32_pseudo_register_typ= e); > > diff --git a/gdb/i386-tdep.h b/gdb/i386-tdep.h > index b750800c7c4..08906e7ad53 100644 > --- a/gdb/i386-tdep.h > +++ b/gdb/i386-tdep.h > @@ -104,7 +104,7 @@ struct i386_gdbarch_tdep : gdbarch_tdep_base > /* Number of byte registers. */ > int num_byte_regs =3D 0; > > -/* Number of lower byte registers. Only used for AMD64. */ > + /* Number of pseudo lower byte registers. Only used for AMD64. */ > int num_lower_byte_regs =3D 0; > > /* Register pseudo number for %al. */ > @@ -123,6 +123,10 @@ struct i386_gdbarch_tdep : gdbarch_tdep_base > of pseudo dword register support. */ > int eax_regnum =3D 0; > > + /* Register number for %eip. Set this to -1 to indicate the absence > + of %eip support. Only used for AMD64. */ > + int eip_regnum =3D -1; > + > /* Number of core registers. */ > int num_core_regs =3D 0; > > -- > 2.44.0 > Ignore this. The wrong patch. --=20 H.J.