From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oa1-x34.google.com (mail-oa1-x34.google.com [IPv6:2001:4860:4864:20::34]) by sourceware.org (Postfix) with ESMTPS id AF90E3857C72 for ; Tue, 30 Aug 2022 09:55:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org AF90E3857C72 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-oa1-x34.google.com with SMTP id 586e51a60fabf-11e7e0a63e2so14625782fac.4 for ; Tue, 30 Aug 2022 02:55:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc; bh=cuhFZgYUElGbQWw6LSfHPWuHIISw7swq1dAla70kGiQ=; b=afhqqpqGkQNovR6I7+0D39yX8fDqQeYU7dTFjJ1dR/AqSk//GnG3XmDDo6lKuy5PzJ gVD4ed2/wPaeegpIKtbn1WsvVjazA9bQgg25N4d4LqN+O3h4NNQwgSuYAT8TWL5vFG2N 16QsPkTPuT2YdMdcT19jg5Lcdf2V+hosESaE8Gb8/OsIVppi+qvPvWwPSqWPV3KBKk+N 8QTzgTAZ0q5+jZ7h2QPYp/FwwdNtWuI1IpWLJhcLm6W/6yGdK1NSZKi4Nj4nHPH1SLEX uiEgdELfqetqatMMAOB3vDUwejOZirxCLPHJ5r+uiKuo9GuYdpHOOpUDVYHrLvhFEog2 moWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc; bh=cuhFZgYUElGbQWw6LSfHPWuHIISw7swq1dAla70kGiQ=; b=EnEkExyNZSt83XKxTzxummiDDOxKUG5mn5do7TXxNKB1X09Fsh4jyhugMcfwcpCa/H OlXr0vOEErHVJP8pTsCO3GR2FpbWp/WzIq2snXb9PetnChaiOTaHk/gxRUvsFX5U8KUZ 03WAM1VI6TAVNPVghPiCK00PzOq+GdNNGZ/d12p4ETSyY9eeLM1EuZWYROpSCd9frTRC kmmiaPDAW5OFOf9UgZs5IXLSyE1VeVPCvAcThg06tHzvS8pCrVzom5ZG4UW8wMVe+udt yuSvtdA0cYirHgyM+RB2m89aRbmdf9Yfj/3prBrlJ2oaw4E0tQPVYRruZ1SJ49GV1ALe UvjA== X-Gm-Message-State: ACgBeo2CObf8ANLiRbX1KhVRYImyO0fkY/yvIe42TN+G3gh+17B7XaYH b6Cnk48I9wXST925E4S5lCcvobez8Vv2/2kWq+YcRg== X-Google-Smtp-Source: AA6agR6PAqSNZsmuq8OH049Ef3lRY7Z+vg9+7d8cMxM+L02226D81tUDkcS2EgufCfE7BYKTOXSz5iNukqBTnNAap9s= X-Received: by 2002:a05:6870:831f:b0:11c:dfe3:ef6d with SMTP id p31-20020a056870831f00b0011cdfe3ef6dmr9402923oae.107.1661853331446; Tue, 30 Aug 2022 02:55:31 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Nelson Chu Date: Tue, 30 Aug 2022 17:55:18 +0800 Message-ID: Subject: Re: [PATCH v5 0/3] RISC-V: Add 'Zmmul' extension To: Tsukasa OI Cc: Nelson Chu , Kito Cheng , Palmer Dabbelt , Liao Shihua , binutils@sourceware.org, gdb-patches@sourceware.org Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 30 Aug 2022 09:55:37 -0000 Thanks, committed except the gdb-sim part, since I'm not the maintainer of gdb and sim, so I cannot approve the related stuff. Besides that, some minor failures of ld testcases which caused by m adding implicit zmmul. However, I also fix that since it's minor. Nelson On Mon, Aug 29, 2022 at 9:59 AM Tsukasa OI via Binutils wrote: > > Hi RISC-V folks, > > 'Zmmul' is a RISC-V extension consisting of only multiply instructions (a > subset of 'M'; multiply and divide instructions). > > This patch is PATCH v5 of the Zmmul support patchset primarily for Binutils > but also contains some GDB changes (a simulator fix and a new testcase). > > I completed the copyright assignment for my GDB contribution so minor > simulator changes are now safe enough to merge. > > Changed Project(s): > PATCH 1/3: Binutils > PATCH 2/3: Binutils and GDB (not to make "temporally broken" revision) > PATCH 3/3: Binutils > > > Note: > To confirm that the simulator is fixed, it requires another patch. > > Without the patch above, 'Zmmul' extension will still work perfectly > (even the simulator). Still, testing whether the simulator works with this > extension (with `make check-sim') requires it. > > > Tracker on GitHub: > > PATCH v1: > > PATCH v2: > > PATCH v3: > > PATCH v4: > > > > This is based on the ISA Manual, draft-20220707-f518c25: > > > > This patchset also contains generic 'M' extension testcases as PATCH 1/3 (it > also tests for existence of the symbol `zmmul' so that it can also be a > base of 'Zmmul' testcases). > > > [Changes: v4 -> v5] > > - Clarify that PATCH 1/3 (new 'M' extension testcases) contains > preparation for the 'Zmmul' extension. > > > [BUG in PATCH v2 (fixed in v3): Simulator stopped working] > > The cause was simple. The RISC-V simulator supports I, M and A extensions > and the instruction is identified by those instruction classes: > > - INSN_CLASS_I (for 'I') > - INSN_CLASS_M (for 'M') > - INSN_CLASS_A (for 'A') > > I forgot to add INSN_CLASS_ZMMUL (also for 'M') to that list and that caused > multiply instructions to cause failure. > > PATCH v3 fixed that and I added a testcase (checks whether all RV32M > instructions run without any fault). > > > Thanks, > Tsukasa > > > > > Tsukasa OI (3): > RISC-V: Add 'M' extension testcases > RISC-V: Add 'Zmmul' extension > RISC-V: Add 'Zmmul' failure testcases > > bfd/elfxx-riscv.c | 6 +++++ > gas/testsuite/gas/riscv/attribute-09.d | 2 +- > gas/testsuite/gas/riscv/m-ext-32.d | 18 +++++++++++++ > gas/testsuite/gas/riscv/m-ext-64.d | 23 ++++++++++++++++ > .../gas/riscv/m-ext-fail-noarch-64.d | 4 +++ > .../gas/riscv/m-ext-fail-noarch-64.l | 14 ++++++++++ > gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d | 4 +++ > gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l | 6 +++++ > gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d | 4 +++ > gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l | 5 ++++ > gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d | 4 +++ > gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l | 9 +++++++ > gas/testsuite/gas/riscv/m-ext.s | 21 +++++++++++++++ > gas/testsuite/gas/riscv/option-arch-02.d | 2 +- > gas/testsuite/gas/riscv/zmmul-32.d | 14 ++++++++++ > gas/testsuite/gas/riscv/zmmul-64.d | 15 +++++++++++ > include/opcode/riscv.h | 1 + > opcodes/riscv-opc.c | 26 +++++++++---------- > sim/riscv/sim-main.c | 1 + > sim/testsuite/riscv/m-ext.s | 18 +++++++++++++ > 20 files changed, 182 insertions(+), 15 deletions(-) > create mode 100644 gas/testsuite/gas/riscv/m-ext-32.d > create mode 100644 gas/testsuite/gas/riscv/m-ext-64.d > create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d > create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l > create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d > create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l > create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d > create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l > create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d > create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l > create mode 100644 gas/testsuite/gas/riscv/m-ext.s > create mode 100644 gas/testsuite/gas/riscv/zmmul-32.d > create mode 100644 gas/testsuite/gas/riscv/zmmul-64.d > create mode 100644 sim/testsuite/riscv/m-ext.s > > > base-commit: 27d582267a1d06e94661979f8893799ac235a768 > -- > 2.34.1 >