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From: Jaydeep Patil <Jaydeep.Patil@imgtec.com>
To: Mike Frysinger <vapier@gentoo.org>
Cc: "gdb-patches@sourceware.org" <gdb-patches@sourceware.org>,
	"aburgess@redhat.com" <aburgess@redhat.com>,
	Joseph Faulls <Joseph.Faulls@imgtec.com>,
	Bhushan Attarde <Bhushan.Attarde@imgtec.com>
Subject: RE: [EXTERNAL] Re: [PATCH v3 2/3] [sim/riscv] Add support for compressed integer instruction set simulation
Date: Tue, 19 Dec 2023 06:15:41 +0000	[thread overview]
Message-ID: <CWXP265MB5321453CDB994D37FD6CE3E68C97A@CWXP265MB5321.GBRP265.PROD.OUTLOOK.COM> (raw)
In-Reply-To: <ZYBzcgsO1NJrL6Y-@vapier>

Mike Frysinger <vapier@gentoo.org> writes:

>you haven't responded to feedback in previous patches.  please do that before posting new ones, or clearly document in the patch the feedback you've addressed as is standard git behavior.

I have replied to your questions.

>we already have SIM_RISCV_xxx_REGNUM.  don't invent new ones

Will address this in next revision

Regards,
Jaydeep

  reply	other threads:[~2023-12-19  6:15 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-17  6:52 [PATCH v3 0/3] sim: riscv: Compressed instruction simulation and semi-hosting support jaydeep.patil
2023-12-17  6:52 ` [PATCH v3 1/3] [sim/riscv] Fix crash during instruction decoding jaydeep.patil
2023-12-18 16:26   ` Mike Frysinger
2023-12-19  6:14     ` [EXTERNAL] " Jaydeep Patil
2023-12-17  6:52 ` [PATCH v3 2/3] [sim/riscv] Add support for compressed integer instruction set simulation jaydeep.patil
2023-12-18 16:29   ` Mike Frysinger
2023-12-19  6:15     ` Jaydeep Patil [this message]
2023-12-17  6:52 ` [PATCH v3 3/3] [sim/riscv] Add semi-hosting support jaydeep.patil
2023-12-18 16:30   ` Mike Frysinger
2023-12-19  6:16     ` [EXTERNAL] " Jaydeep Patil

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