[PATCH 0/4] sim: riscv: Compressed instruction simulation and semi-hosting support

[Jaydeep Patil <Jaydeep.Patil@imgtec.com>]

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Hi,

This is a collection of patches that add simulation of compressed integer
instruction set ("c") and semi-hosting support to the RISC-V simulator. It also
fixes 32bit JALR instruction simulation when RD is same as RS1. Two tests are
added in gdb.arch to test basic semi-hosting and then the simulation of
compressed integer instructions.

Patch #1 adds basic semi-hosting support (OPEN, EXIT and GET_CMDLINE) and
         gdb.arch/riscv-exit-getcmd.c test
Patch #2 fixes JALR instruction simulation when RD is same as RS1
Patch #3 adds support for compressed integer instruction set ("c") and
         gdb.arch/riscv-insn-simulation.c test
Patch #4 adds support for remaining semi-hosting calls

Contributions from:
  Joseph Faulls (Joseph.Faulls@imgtec.com<mailto:Joseph.Faulls@imgtec.com>)
  Jaydeep Patil (Jaydeep.Patil@imgtec.com<mailto:Jaydeep.Patil@imgtec.com>)
  Bhushan Attarde (Bhushan.Attarde@imgtec.com<mailto:Bhushan.Attarde@imgtec.com>)

Jaydeep Patil (4):
  [sim/riscv] Add basic semi-hosting support
  [sim/riscv] Fix JALR instruction simulation
  [sim/riscv] Add support for compressed integer instruction set
  [sim/riscv] Add semi-hosting support

gdb/testsuite/gdb.arch/riscv-exit-getcmd.c    |    6 +
gdb/testsuite/gdb.arch/riscv-exit-getcmd.exp  |   31 +
.../gdb.arch/riscv-insn-simulation.c          | 1590 +++++++++++++++++
.../gdb.arch/riscv-insn-simulation.exp        |   35 +
sim/riscv/riscv-sim.h                         |   54 +
sim/riscv/sim-main.c                          |  952 +++++++++-
6 files changed, 2652 insertions(+), 16 deletions(-)
create mode 100644 gdb/testsuite/gdb.arch/riscv-exit-getcmd.c
create mode 100644 gdb/testsuite/gdb.arch/riscv-exit-getcmd.exp
create mode 100644 gdb/testsuite/gdb.arch/riscv-insn-simulation.c
create mode 100644 gdb/testsuite/gdb.arch/riscv-insn-simulation.exp

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2.25.1