From: Jaydeep Patil <Jaydeep.Patil@imgtec.com>
To: "gdb-patches@sourceware.org" <gdb-patches@sourceware.org>
Cc: "aburgess@redhat.com" <aburgess@redhat.com>,
"vapier@gentoo.org" <vapier@gentoo.org>,
Joseph Faulls <Joseph.Faulls@imgtec.com>,
"Bhushan Attarde" <Bhushan.Attarde@imgtec.com>
Subject: [PATCH 2/4] [sim/riscv] Fix JALR instruction simulation
Date: Tue, 17 Oct 2023 05:53:07 +0000 [thread overview]
Message-ID: <CWXP265MB532192568CE81921F58C1F048CD6A@CWXP265MB5321.GBRP265.PROD.OUTLOOK.COM> (raw)
[-- Attachment #1: Type: text/plain, Size: 777 bytes --]
Fixed 32bit JALR ra,ra,imm integer instruction, where RD was written before
using it to calculate target PC.
---
sim/riscv/sim-main.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 2b184aea554..3cf6e3fc4b0 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -598,8 +598,8 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
break;
case MATCH_JALR:
TRACE_INSN (cpu, "jalr %s, %s, %" PRIiTW ";", rd_name, rs1_name, i_imm);
- store_rd (cpu, rd, riscv_cpu->pc + 4);
pc = riscv_cpu->regs[rs1] + i_imm;
+ store_rd (cpu, rd, riscv_cpu->pc + 4);
TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
break;
--
2.25.1
next reply other threads:[~2023-10-17 5:53 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-17 5:53 Jaydeep Patil [this message]
2023-10-18 16:58 ` Andrew Burgess
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