From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp.polymtl.ca (smtp.polymtl.ca [132.207.4.11]) by sourceware.org (Postfix) with ESMTPS id B337C3858D35 for ; Wed, 26 Jul 2023 22:51:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B337C3858D35 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=polymtl.ca Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=polymtl.ca Received: from simark.ca (simark.ca [158.69.221.121]) (authenticated bits=0) by smtp.polymtl.ca (8.14.7/8.14.7) with ESMTP id 36QMpns1032309 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 26 Jul 2023 18:51:53 -0400 DKIM-Filter: OpenDKIM Filter v2.11.0 smtp.polymtl.ca 36QMpns1032309 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=polymtl.ca; s=default; t=1690411914; bh=D4rF0Vo4qczy01Xjm0NdJBUC1oV1AZXDc1F14RttXGM=; h=Date:From:To:CC:Subject:In-Reply-To:References:From; b=DXKdC3qYCMundoE5jcZ2NkvabUdJWSpf/74jP53b5JfZvOyubMxo6rPQOTGS5dTRd TEkvo/JDBSWcmV8s9YAwDHYeJC0hj67nqOte8Lzret+IcT3RMW6bdObXFVbvfAo0ZQ Biox4P1olucLk93gAX3A2lUVrTwMa3+lEpHTA2XY= Received: from [127.0.0.1] (unknown [204.48.78.241]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPSA id CC3A61E00F; Wed, 26 Jul 2023 18:51:48 -0400 (EDT) Date: Wed, 26 Jul 2023 18:51:48 -0400 From: Simon Marchi To: John Baldwin , gdb-patches@sourceware.org CC: Aleksandar Paunovic Subject: =?US-ASCII?Q?Re=3A_=5BPATCH_v6_01/15=5D_x86=3A_Add_an_x86=5Fxsave=5Flay?= =?US-ASCII?Q?out_structure_to_handle_variable_XSAVE_layouts=2E?= User-Agent: K-9 Mail for Android In-Reply-To: References: <20230714155151.21723-1-jhb@FreeBSD.org> <20230714155151.21723-2-jhb@FreeBSD.org> <00492b34-3d4d-6584-cce7-1624326908f0@polymtl.ca> Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Poly-FromMTA: (simark.ca [158.69.221.121]) at Wed, 26 Jul 2023 22:51:49 +0000 X-Spam-Status: No, score=-3038.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_LOW,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On July 26, 2023 5:27:41 p=2Em=2E EDT, John Baldwin wr= ote: >On 7/26/23 12:22 PM, Simon Marchi wrote: >> On 7/14/23 11:51, John Baldwin wrote: >>> The standard layout of the XSAVE extended state area consists of three >>> regions=2E The first 512 bytes (legacy region) match the layout of th= e >>> FXSAVE instruction including floating point registers, MMX registers, >>> and SSE registers=2E The next 64 bytes (XSAVE header) contains a head= er >>> with a fixed layout=2E The final region (extended region) contains ze= ro >>> or more optional state components=2E Examples of these include the >>> upper 128 bits of YMM registers for AVX=2E >>>=20 >>> These optional state components generally have an >>> architecturally-fixed size, but they are not assigned architectural >>> offsets in the extended region=2E Instead, processors provide >>> additional CPUID leafs describing the size and offset of each >>> component in the "standard" layout for a given CPU=2E (There is also = a >>> "compact" format which uses an alternate layout, but existing OS's >>> currently export the "standard" layout when exporting XSAVE data via >>> ptrace() and core dumps=2E) >>>=20 >>> To date, GDB has assumed the layout used on current Intel processors >>> for state components in the extended region and hardcoded those >>> offsets in the tables in i387-tdep=2Ec and i387-fp=2Ecc=2E However, t= his >>> fails on recent AMD processors which use a different layout=2E >>> Specifically, AMD Zen3 and later processors do not leave space for the >>> MPX register set in between the AVX and AVX512 register sets=2E >>>=20 >>> To rectify this, add an x86_xsave_layout structure which contains the >>> total size of the XSAVE extended state area as well as the offset of >>> each known optional state component=2E >>>=20 >>> Subsequent commits will modify XSAVE parsing in both gdb and gdbserver >>> to use x86_xsave_layout=2E >>>=20 >>> Co-authored-by: Aleksandar Paunovic >>> --- >>> gdbsupport/x86-xstate=2Eh | 65 +++++++++++++++++++++++++++++++++++--= ---- >>> 1 file changed, 56 insertions(+), 9 deletions(-) >>>=20 >>> diff --git a/gdbsupport/x86-xstate=2Eh b/gdbsupport/x86-xstate=2Eh >>> index b8740fd8701=2E=2E27fc0bd12f2 100644 >>> --- a/gdbsupport/x86-xstate=2Eh >>> +++ b/gdbsupport/x86-xstate=2Eh >>> @@ -20,22 +20,69 @@ >>> #ifndef COMMON_X86_XSTATE_H >>> #define COMMON_X86_XSTATE_H >>> +/* The extended state feature IDs in the state component bitmap=2E = */ >>> +#define X86_XSTATE_X87_ID 0 >>> +#define X86_XSTATE_SSE_ID 1 >>> +#define X86_XSTATE_AVX_ID 2 >>> +#define X86_XSTATE_BNDREGS_ID 3 >>> +#define X86_XSTATE_BNDCFG_ID 4 >>> +#define X86_XSTATE_K_ID 5 >>> +#define X86_XSTATE_ZMM_H_ID 6 >>> +#define X86_XSTATE_ZMM_ID 7 >>> +#define X86_XSTATE_PKRU_ID 9 >>> + >>> /* The extended state feature bits=2E */ >>> -#define X86_XSTATE_X87 (1ULL << 0) >>> -#define X86_XSTATE_SSE (1ULL << 1) >>> -#define X86_XSTATE_AVX (1ULL << 2) >>> -#define X86_XSTATE_BNDREGS (1ULL << 3) >>> -#define X86_XSTATE_BNDCFG (1ULL << 4) >>> +#define X86_XSTATE_X87 (1ULL << X86_XSTATE_X87_ID) >>> +#define X86_XSTATE_SSE (1ULL << X86_XSTATE_SSE_ID) >>> +#define X86_XSTATE_AVX (1ULL << X86_XSTATE_AVX_ID) >>> +#define X86_XSTATE_BNDREGS (1ULL << X86_XSTATE_BNDREGS_ID) >>> +#define X86_XSTATE_BNDCFG (1ULL << X86_XSTATE_BNDCFG_ID) >>> #define X86_XSTATE_MPX (X86_XSTATE_BNDREGS | X86_XSTATE_BNDCFG) >>> /* AVX 512 adds three feature bits=2E All three must be enabled= =2E */ >>> -#define X86_XSTATE_K (1ULL << 5) >>> -#define X86_XSTATE_ZMM_H (1ULL << 6) >>> -#define X86_XSTATE_ZMM (1ULL << 7) >>> +#define X86_XSTATE_K (1ULL << X86_XSTATE_K_ID) >>> +#define X86_XSTATE_ZMM_H (1ULL << X86_XSTATE_ZMM_H_ID) >>> +#define X86_XSTATE_ZMM (1ULL << X86_XSTATE_ZMM_ID) >>> #define X86_XSTATE_AVX512 (X86_XSTATE_K | X86_XSTATE_ZMM_H \ >>> | X86_XSTATE_ZMM) >>> -#define X86_XSTATE_PKRU (1ULL << 9) >>> +#define X86_XSTATE_PKRU (1ULL << X86_XSTATE_PKRU_ID) >>> + >>> +/* Size and offsets of register states in the XSAVE area extended >>> + region=2E Offsets are set to 0 to indicate the absence of the >>> + associated registers=2E */ >>=20 >> Extreme comment nitpick=2E In "Size and offsets", one is singular and = the >> other is plural=2E Should it be "Sizes and offsets", or "Size and >> offset"? > >Ah, there's a single size and multiple offsets=2E Is this version cleare= r: > >/* Total size of the XSAVE area extended region and offsets of > register states within the region=2E Offsets are set to 0 to > indicate the absence of the associated registers=2E */ > Ah, sorry=2E The new comment is clearer, thanks=2E=20 Simon=20