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Sun, 13 Dec 2020 10:13:05 +0000 From: Fredrik Hederstierna To: Paul Mathieu , Luis Machado CC: Andrew Burgess , "binutils@sourceware.org" , "gdb-patches@sourceware.org" Subject: Re: [PATCH 5/8] gdb/riscv: introduce bare metal core dump support Thread-Topic: [PATCH 5/8] gdb/riscv: introduce bare metal core dump support Thread-Index: AQHWyNa1rTkZzTRf6k+oISEsTT9an6nrxlkAgAALiYCAABDYAIAAB0CAgAANJQCAAA2NAIAABqyAgAAEdQCAAAMbgIAIyGZ4 Date: Sun, 13 Dec 2020 10:13:05 +0000 Message-ID: References: <5ba628c1042f3000947a1f2a6f9e24cf46573fa3.1606930261.git.andrew.burgess@embecosm.com> <20201207151702.GK2729@embecosm.com> <36bed17a-6012-a5d9-a29c-64e9cbbef640@linaro.org> <20201207165836.GM2729@embecosm.com> <615830c3-4ccb-cfd6-3721-0123d6c4b56a@linaro.org> <20201207181136.GN2729@embecosm.com> <3595d9b8-e26c-5ed4-8906-4ee3519a120e@linaro.org> <20201207192359.GO2729@embecosm.com> <601f2195-db95-3864-c54d-8c6998cff00a@linaro.org>, In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [81.236.17.7] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 06432735-bf95-4ad4-7c4f-08d89f4fae8e x-ms-traffictypediagnostic: HE1PR10MB1723: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:10000; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: verisure.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: HE1PR10MB1723.EURPRD10.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-Network-Message-Id: 06432735-bf95-4ad4-7c4f-08d89f4fae8e X-MS-Exchange-CrossTenant-originalarrivaltime: 13 Dec 2020 10:13:05.1901 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3055fa7f-a944-4927-801e-a62b63119e43 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: DgVKO1P3oMAVRApVQHNIkoD+4HaGTTZRBZCYF922+tBvdBc9ajDtCK1r7/XmU4IfojdJtJ+1AOLXX9gfy1moUox7BR8DcuR/JLEyfIxYY3KfsM+2bU200VrbixIZcsvE X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR10MB1723 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737 definitions=2020-12-13_04:2020-12-11, 2020-12-13 signatures=0 X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 13 Dec 2020 10:13:24 -0000 > From: Paul Mathieu =0A= > Sent: Monday, December 7, 2020 8:51 PM=0A= > To: Luis Machado =0A= > Cc: Andrew Burgess ; binutils@sourceware.org= ; gdb-patches@sourceware.org ; Fredrik Hederstierna =0A= > Subject: Re: [PATCH 5/8] gdb/riscv: introduce bare metal core dump suppor= t =0A= > =0A= > Thanks Luis for getting the ball rolling again!=0A= > =0A= > As far as I'm concerned, I haven't deployed much infrastructure to=0A= > generate or otherwise deal with bare metal cores at the moment, so I'm=0A= > happy to work with anything. The one thing that is a big deal to me is=0A= > support for RTOS threads.=0A= > =0A= > ELF + NOTES seems like the obvious choice to me, as it matches what=0A= > I'm used to. Most online resources about core dumps seem to be=0A= > specifically about Linux core dumps, so it would be less surprising=0A= > and more helpful to share as much as possible with it, IMO.=0A= > =0A= > What I'm expecting from a bare metal core dump:=0A= > - memory dump sections=0A= > - CPU registers=0A= > - when available (RTOS support from the dumping side): inactive=0A= > threads' CPU registers=0A= =0A= Thanks all, good to see that bare metal corefile support involves even more= people, and increased interest to get gdb support this feature.=0A= I'm sorry I haven't had much time this fall to put more time into it. The v= 4-patch as discussed here is my latest proposal, and as I understood it was= some 'leftovers' yet regarding specification/documentation, but I had not = good idea how to start this work, so I think I would need to some help wher= e to start off.=0A= =0A= Hopefully the more generic parts of the v4-patch like the 'none-tdep.c' par= ts could be reused by riscv, the it can open paths to make the future ARM-s= upport less work and easier to get it done. Then hopefully the riscv docume= ntation parts could be very similar and also could be possibly reused for t= he ARM corefile format.=0A= =0A= Anything that could help the arm-none-corefile support is great, nice if th= ese patches for arm and riscv do not diverge, better if the patches could '= help each other' to get a good solution as generic as possible, also openin= g paths for future corefiles for even other CPU architectures.=0A= Can I do anything right now to help proceeding this process, I'm sorry I do= not really know what I can do currently to 'make it happen' :-)=0A= =0A= Thanks all, Best Regards,=0A= Fredrik=