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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: syrmia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: VI1PR03MB4208.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 96ea699b-0f6b-40a3-b95b-08daac7be3dc X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Oct 2022 18:02:12.9569 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 19214a73-c1ab-4e19-8f59-14bdcb09a66e X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: nTyDFrAo4ALg1GIfKrUJ0goehupbtiPjNkt5c2OpDGK4JGpJeYX8a9WozbfLt8tc1GujQlCU/pPyebYwOZVSaIgnMu/OaYJeIMj7Q5Uj+mA= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR03MB7586 X-Spam-Status: No, score=-13.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 12 Oct 2022 18:02:19 -0000 =0A= Introduce new instruction encodings from Release 6 of the MIPS=0A= architecture [1]. Support breakpoints and single stepping with=0A= compact branches, forbidden slots, new branch instruction and=0A= new atomic load-store instruction encodings.=0A= =0A= [1] "MIPS64 Architecture for Programmers Volume II-A: The MIPS64=0A= Instruction Set Reference Manual", Document Number: MD00087,=0A= Revision 6.06, December 15, 2016, Section 3 "The MIPS64=0A= Instruction Set", pp. 42-530=0A= https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00087-2B-MIPS= 64BIS-AFP-6.06.pdf=0A= =0A= 2022-10-12 Andrew Bennett =0A= Matthew Fortune =0A= Faraz Shahbazker =0A= =0A= gdb/ChangeLog:=0A= * mips-tdep.c (is_mipsr6_isa): New.=0A= (b0s21_imm): New define.=0A= (mips32_relative_offset21, mips32_relative_offset26): New.=0A= (is_add32bit_overflow, is_add64bit_overflow): New.=0A= (mips32_next_pc): Handle r6 compact and fpu coprocessor branches.= =0A= Move handling of BLEZ, BGTZ opcode into ...=0A= (mips32_blez_pc): New.=0A= (mips32_instruction_is_compact_branch): New.=0A= (mips32_insn_at_pc_has_forbidden_slot): New.=0A= (mips32_scan_prologue): Ignore pre-r6 addi encoding on r6.=0A= Stop at compact branch also.=0A= (LLSC_R6_OPCODE,LL_R6_FUNCT,LLE_FUNCT,=0A= LLD_R6_FUNCT,SC_R6_FUNCT,SCE_FUNCT,=0A= SCD_R6_FUNCT: New defines.=0A= (is_ll_insn, is_sc_insn): New.=0A= (mips_deal_with_atomic_sequence): Use is_ll_insn/is_sc_insn.=0A= Handle compact branches.=0A= (mips_about_to_return): Handle jrc and macro jr.=0A= (mips32_stack_frame_destroyed_p): Likewise.=0A= (mips32_instruction_has_delay_slot): Don't handle JALX on r6.=0A= Handle compact branches and coprocessor branches.=0A= (mips_adjust_breakpoint_address): Skip forbidden slot for=0A= compact branches.=0A= ---=0A= gdb/mips-tdep.c | 498 ++++++++++++++++++++++++++++++++++++++++++++----=0A= 1 file changed, 457 insertions(+), 41 deletions(-)=0A= =0A= diff --git a/gdb/mips-tdep.c b/gdb/mips-tdep.c=0A= index a5c39ce224f..556eb141f86 100644=0A= --- a/gdb/mips-tdep.c=0A= +++ b/gdb/mips-tdep.c=0A= @@ -76,6 +76,9 @@ static int mips16_insn_at_pc_has_delay_slot (struct gdbar= ch *gdbarch,=0A= static void mips_print_float_info (struct gdbarch *, struct ui_file *,=0A= frame_info_ptr , const char *);=0A= =0A= +static void mips_read_fp_register_single (frame_info_ptr, int,=0A= + gdb_byte *);=0A= +=0A= /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */=0A= /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */= =0A= #define ST0_FR (1 << 26)=0A= @@ -1497,6 +1500,17 @@ mips_fetch_instruction (struct gdbarch *gdbarch,=0A= return extract_unsigned_integer (buf, instlen, byte_order);=0A= }=0A= =0A= +/* Return true if the gdbarch is based on MIPS Release 6. */=0A= +=0A= +static bool=0A= +is_mipsr6_isa (struct gdbarch *gdbarch)=0A= +{=0A= + const struct bfd_arch_info *info =3D gdbarch_bfd_arch_info (gdbarch);=0A= +=0A= + return (info->mach =3D=3D bfd_mach_mipsisa32r6=0A= + || info->mach =3D=3D bfd_mach_mipsisa64r6);=0A= +}=0A= +=0A= /* These are the fields of 32 bit mips instructions. */=0A= #define mips32_op(x) (x >> 26)=0A= #define itype_op(x) (x >> 26)=0A= @@ -1539,6 +1553,7 @@ mips_fetch_instruction (struct gdbarch *gdbarch,=0A= #define b0s11_op(x) ((x) & 0x7ff)=0A= #define b0s12_imm(x) ((x) & 0xfff)=0A= #define b0s16_imm(x) ((x) & 0xffff)=0A= +#define b0s21_imm(x) ((x) & 0x1fffff)=0A= #define b0s26_imm(x) ((x) & 0x3ffffff)=0A= #define b6s10_ext(x) (((x) >> 6) & 0x3ff)=0A= #define b11s5_reg(x) (((x) >> 11) & 0x1f)=0A= @@ -1575,6 +1590,18 @@ mips32_relative_offset (ULONGEST inst)=0A= return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2;=0A= }=0A= =0A= +static LONGEST=0A= +mips32_relative_offset21 (ULONGEST insn)=0A= +{=0A= + return ((b0s21_imm (insn) ^ 0x100000) - 0x100000) << 2;=0A= +}=0A= +=0A= +static LONGEST=0A= +mips32_relative_offset26 (ULONGEST insn)=0A= +{=0A= + return ((b0s26_imm (insn) ^ 0x2000000) - 0x2000000) << 2;=0A= +}=0A= +=0A= /* Determine the address of the next instruction executed after the INST= =0A= floating condition branch instruction at PC. COUNT specifies the=0A= number of the floating condition bits tested by the branch. */=0A= @@ -1633,6 +1660,70 @@ is_octeon_bbit_op (int op, struct gdbarch *gdbarch)= =0A= return 0;=0A= }=0A= =0A= +/* Return true if addition produces 32-bit overflow. */=0A= +=0A= +static bool=0A= +is_add32bit_overflow (int32_t a, int32_t b)=0A= +{=0A= + int32_t r =3D (uint32_t) a + (uint32_t) b;=0A= + return (a < 0 && b < 0 && r >=3D 0) || (a >=3D 0 && b >=3D 0 && r < 0);= =0A= +}=0A= +=0A= +/* Return true if addition produces 32-bit overflow or=0A= + one of the inputs is not sign-extended 32-bit value. */=0A= +=0A= +static bool=0A= +is_add64bit_overflow (int64_t a, int64_t b)=0A= +{=0A= + if (a !=3D (int32_t) a)=0A= + return 1;=0A= + if (b !=3D (int32_t) b)=0A= + return 1;=0A= + return is_add32bit_overflow ((int32_t) a, (int32_t) b);=0A= +}=0A= +=0A= +/* Calculate address of next instruction after BLEZ-like or=0A= + BGTZ-like (invert =3D=3D true) instruction at pc. */=0A= +=0A= +static CORE_ADDR=0A= +mips32_blez_pc (struct gdbarch *gdbarch, struct regcache *regcache,=0A= + ULONGEST inst, CORE_ADDR pc, bool invert)=0A= +{=0A= + int rs =3D itype_rs (inst);=0A= + int rt =3D itype_rt (inst);=0A= + LONGEST val_rs =3D regcache_raw_get_signed (regcache, rs);=0A= + LONGEST val_rt =3D regcache_raw_get_signed (regcache, rt);=0A= + ULONGEST uval_rs =3D regcache_raw_get_unsigned (regcache, rs);=0A= + ULONGEST uval_rt =3D regcache_raw_get_unsigned (regcache, rt);=0A= + bool taken =3D false;=0A= +=0A= + /* BLEZ, BLEZL, BGTZ, BGTZL */=0A= + if (rt =3D=3D 0)=0A= + taken =3D (val_rs <=3D 0);=0A= + else if (is_mipsr6_isa (gdbarch))=0A= + {=0A= + /* BLEZALC, BGTZALC */=0A= + if (rs =3D=3D 0 && rt !=3D 0)=0A= + taken =3D (val_rt <=3D 0);=0A= + /* BGEZALC, BLTZALC */=0A= + else if (rs =3D=3D rt && rt !=3D 0)=0A= + taken =3D (val_rt >=3D 0);=0A= + /* BGEUC, BLTUC */=0A= + else if (rs !=3D rt && rs !=3D 0 && rt !=3D 0)=0A= + taken =3D (uval_rs >=3D uval_rt);=0A= + }=0A= +=0A= + if (invert)=0A= + taken =3D !taken;=0A= +=0A= + /* Calculate branch target. */=0A= + if (taken)=0A= + pc +=3D mips32_relative_offset (inst) + 4;=0A= + else=0A= + pc +=3D 8;=0A= +=0A= + return pc;=0A= +}=0A= =0A= /* Determine where to set a single step breakpoint while considering=0A= branch prediction. */=0A= @@ -1643,13 +1734,15 @@ mips32_next_pc (struct regcache *regcache, CORE_ADD= R pc)=0A= struct gdbarch *gdbarch =3D regcache->arch ();=0A= unsigned long inst;=0A= int op;=0A= + bool mips64bitreg =3D mips_isa_regsize (gdbarch) =3D=3D 8;=0A= +=0A= inst =3D mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);=0A= op =3D itype_op (inst);=0A= if ((inst & 0xe0000000) !=3D 0) /* Not a special, jump or branch=0A= instruction. */=0A= {=0A= - if (op >> 2 =3D=3D 5)=0A= - /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */=0A= + /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */=0A= + if (op >> 2 =3D=3D 5 && ((op & 0x02) =3D=3D 0 || itype_rt (inst) =3D= =3D 0))=0A= {=0A= switch (op & 0x03)=0A= {=0A= @@ -1658,7 +1751,7 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR = pc)=0A= case 1: /* BNEL */=0A= goto neq_branch;=0A= case 2: /* BLEZL */=0A= - goto less_branch;=0A= + goto lez_branch;=0A= case 3: /* BGTZL */=0A= goto greater_branch;=0A= default:=0A= @@ -1668,15 +1761,19 @@ mips32_next_pc (struct regcache *regcache, CORE_ADD= R pc)=0A= else if (op =3D=3D 17 && itype_rs (inst) =3D=3D 8)=0A= /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */=0A= pc =3D mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 1);=0A= - else if (op =3D=3D 17 && itype_rs (inst) =3D=3D 9=0A= + else if (!is_mipsr6_isa (gdbarch)=0A= + && op =3D=3D 17=0A= + && itype_rs (inst) =3D=3D 9=0A= && (itype_rt (inst) & 2) =3D=3D 0)=0A= /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */=0A= pc =3D mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 2);=0A= - else if (op =3D=3D 17 && itype_rs (inst) =3D=3D 10=0A= + else if (!is_mipsr6_isa (gdbarch)=0A= + && op =3D=3D 17=0A= + && itype_rs (inst) =3D=3D 10=0A= && (itype_rt (inst) & 2) =3D=3D 0)=0A= /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */=0A= pc =3D mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 4);=0A= - else if (op =3D=3D 29)=0A= + else if (!is_mipsr6_isa (gdbarch) && op =3D=3D 29)=0A= /* JALX: 011101 */=0A= /* The new PC will be alternate mode. */=0A= {=0A= @@ -1704,7 +1801,119 @@ mips32_next_pc (struct regcache *regcache, CORE_ADD= R pc)=0A= else=0A= pc +=3D 8; /* After the delay slot. */=0A= }=0A= + else if (is_mipsr6_isa (gdbarch))=0A= + {=0A= + /* BOVC, BEQZALC, BEQC and BNVC, BNEZALC, BNEC */=0A= + if (op =3D=3D 8 || op =3D=3D 24)=0A= + {=0A= + int rs =3D rtype_rs (inst);=0A= + int rt =3D rtype_rt (inst);=0A= + LONGEST val_rs =3D regcache_raw_get_signed (regcache, rs);=0A= + LONGEST val_rt =3D regcache_raw_get_signed (regcache, rt);=0A= + bool taken =3D false;=0A= + /* BOVC (BNVC) */=0A= + if (rs >=3D rt)=0A= + {=0A= + if (mips64bitreg)=0A= + taken =3D is_add64bit_overflow (val_rs, val_rt);=0A= + else=0A= + taken =3D is_add32bit_overflow (val_rs, val_rt);=0A= + }=0A= + else if (rs < rt && rs =3D=3D 0)=0A= + /* BEQZALC (BNEZALC) */=0A= + taken =3D (val_rt =3D=3D 0);=0A= + else=0A= + /* BEQC (BNEC) */=0A= + taken =3D (val_rs =3D=3D val_rt);=0A= +=0A= + /* BNVC, BNEZALC, BNEC */=0A= + if (op =3D=3D 24)=0A= + taken =3D !taken;=0A= =0A= + if (taken)=0A= + pc +=3D mips32_relative_offset (inst) + 4;=0A= + else=0A= + /* Step through the forbidden slot. */=0A= + pc +=3D 8;=0A= + }=0A= + else if (op =3D=3D 17 && (itype_rs (inst) =3D=3D 9 || itype_rs (inst) = =3D=3D 13))=0A= + /* BC1EQZ, BC1NEZ */=0A= + {=0A= + gdb_byte status;=0A= + gdb_byte true_val =3D 0;=0A= + unsigned int fp =3D (gdbarch_num_regs (gdbarch)=0A= + + mips_regnum (gdbarch)->fp0=0A= + + itype_rt (inst));=0A= + frame_info_ptr frame =3D get_current_frame ();=0A= + gdb_byte raw_buffer[4];=0A= + mips_read_fp_register_single (frame, fp, raw_buffer);=0A= +=0A= + if (gdbarch_byte_order (gdbarch) =3D=3D BFD_ENDIAN_BIG)=0A= + status =3D *(raw_buffer + 3);=0A= + else=0A= + status =3D *(raw_buffer);=0A= +=0A= + if (itype_rs (inst) =3D=3D 13)=0A= + true_val =3D 1;=0A= +=0A= + if ((status & 0x1) =3D=3D true_val)=0A= + pc +=3D mips32_relative_offset (inst) + 4;=0A= + else=0A= + pc +=3D 8;=0A= + }=0A= + else if (op =3D=3D 22 || op =3D=3D 23)=0A= + /* BLEZC, BGEZC, BGEC, BGTZC, BLTZC, BLTC */=0A= + {=0A= + int rs =3D rtype_rs (inst);=0A= + int rt =3D rtype_rt (inst);=0A= + LONGEST val_rs =3D regcache_raw_get_signed (regcache, rs);=0A= + LONGEST val_rt =3D regcache_raw_get_signed (regcache, rt);=0A= + bool taken =3D false;=0A= + /* The R5 rt =3D=3D 0 case is handled above so we treat it as=0A= + an unknown instruction here for future ISA usage. */=0A= + if (rs =3D=3D 0 && rt !=3D 0)=0A= + taken =3D (val_rt <=3D 0);=0A= + else if (rs =3D=3D rt && rt !=3D 0)=0A= + taken =3D (val_rt >=3D 0);=0A= + else if (rs !=3D rt && rs !=3D 0 && rt !=3D 0)=0A= + taken =3D (val_rs >=3D val_rt);=0A= +=0A= + if (op =3D=3D 23)=0A= + taken =3D !taken;=0A= +=0A= + if (taken)=0A= + pc +=3D mips32_relative_offset (inst) + 4;=0A= + else=0A= + /* Step through the forbidden slot. */=0A= + pc +=3D 8;=0A= + }=0A= + else if (op =3D=3D 50 || op =3D=3D 58)=0A= + /* BC, BALC */=0A= + pc +=3D mips32_relative_offset26 (inst) + 4;=0A= + else if ((op =3D=3D 54 || op =3D=3D 62)=0A= + && rtype_rs (inst) =3D=3D 0)=0A= + /* JIC, JIALC */=0A= + {=0A= + pc =3D regcache_raw_get_signed (regcache, itype_rt (inst));=0A= + pc +=3D (itype_immediate (inst) ^ 0x8000) - 0x8000;=0A= + }=0A= + else if (op =3D=3D 54 || op =3D=3D 62)=0A= + /* BEQZC, BNEZC */=0A= + {=0A= + int rs =3D itype_rs (inst);=0A= + LONGEST rs_val =3D regcache_raw_get_signed (regcache, rs);=0A= + bool taken =3D (rs_val =3D=3D 0);=0A= + if (op =3D=3D 62)=0A= + taken =3D !taken;=0A= + if (taken)=0A= + pc +=3D mips32_relative_offset21 (inst) + 4;=0A= + else=0A= + /* Step through the forbidden slot. */=0A= + pc +=3D 8;=0A= + }=0A= + else=0A= + pc +=3D 4; /* Not a branch, next instruction is easy. */=0A= + }=0A= else=0A= pc +=3D 4; /* Not a branch, next instruction is easy. */=0A= }=0A= @@ -1748,7 +1957,6 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR = pc)=0A= case 2: /* BLTZL */=0A= case 16: /* BLTZAL */=0A= case 18: /* BLTZALL */=0A= - less_branch:=0A= if (regcache_raw_get_signed (regcache, itype_rs (inst)) < 0)=0A= pc +=3D mips32_relative_offset (inst) + 4;=0A= else=0A= @@ -1764,6 +1972,7 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR = pc)=0A= pc +=3D 8; /* after the delay slot */=0A= break;=0A= case 0x1c: /* BPOSGE32 */=0A= + case 0x1d: /* BPOSGE32C */=0A= case 0x1e: /* BPOSGE64 */=0A= pc +=3D 4;=0A= if (itype_rs (inst) =3D=3D 0)=0A= @@ -1775,6 +1984,13 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR= pc)=0A= /* No way to handle; it'll most likely trap anyway. */=0A= break;=0A= =0A= + /* BPOSGE32C */=0A= + if (op =3D=3D 0x1d)=0A= + {=0A= + if (!is_mipsr6_isa (gdbarch))=0A= + break;=0A= + }=0A= +=0A= if ((regcache_raw_get_unsigned (regcache,=0A= dspctl) & 0x7f) >=3D pos)=0A= pc +=3D mips32_relative_offset (inst);=0A= @@ -1813,19 +2029,14 @@ mips32_next_pc (struct regcache *regcache, CORE_ADD= R pc)=0A= else=0A= pc +=3D 8;=0A= break;=0A= - case 6: /* BLEZ, BLEZL */=0A= - if (regcache_raw_get_signed (regcache, itype_rs (inst)) <=3D 0)=0A= - pc +=3D mips32_relative_offset (inst) + 4;=0A= - else=0A= - pc +=3D 8;=0A= + case 6: /* BLEZ, BLEZL, BLEZALC, BGEZALC, BGEUC */=0A= + lez_branch:=0A= + pc =3D mips32_blez_pc (gdbarch, regcache, inst, pc, /*invert*/ false);= =0A= break;=0A= case 7:=0A= default:=0A= - greater_branch: /* BGTZ, BGTZL */=0A= - if (regcache_raw_get_signed (regcache, itype_rs (inst)) > 0)=0A= - pc +=3D mips32_relative_offset (inst) + 4;=0A= - else=0A= - pc +=3D 8;=0A= + greater_branch: /* BGTZ, BGTZL, BGTZALC, BLTZALC, BLTUC */=0A= + pc =3D mips32_blez_pc (gdbarch, regcache, inst, pc, /*invert*/ true);= =0A= break;=0A= } /* switch */=0A= } /* else */=0A= @@ -2448,6 +2659,72 @@ micromips_instruction_is_compact_branch (unsigned sh= ort insn)=0A= }=0A= }=0A= =0A= +/* Return non-zero if the MIPS instruction INSN is a compact branch=0A= + or jump. A value of 1 indicates an unconditional compact branch=0A= + and a value of 2 indicates a conditional compact branch. */=0A= +=0A= +static int=0A= +mips32_instruction_is_compact_branch (struct gdbarch *gdbarch, ULONGEST in= sn)=0A= +{=0A= + switch (itype_op (insn))=0A= + {=0A= + /* BC */=0A= + case 50:=0A= + /* BALC */=0A= + case 58:=0A= + if (is_mipsr6_isa (gdbarch))=0A= + return 1;=0A= + break;=0A= + /* BOVC, BEQZALC, BEQC */=0A= + case 8:=0A= + /* BNVC, BNEZALC, BNEC */=0A= + case 24:=0A= + if (is_mipsr6_isa (gdbarch))=0A= + return 2;=0A= + break;=0A= + /* BEQZC, JIC */=0A= + case 54:=0A= + /* BNEZC, JIALC */=0A= + case 62:=0A= + if (is_mipsr6_isa (gdbarch))=0A= + /* JIC, JIALC are unconditional */=0A= + return (itype_rs (insn) =3D=3D 0) ? 1 : 2;=0A= + break;=0A= + /* BLEZC, BGEZC, BGEC */=0A= + case 22:=0A= + /* BGTZC, BLTZC, BLTC */=0A= + case 23:=0A= + /* BLEZALC, BGEZALC, BGEUC */=0A= + case 6:=0A= + /* BGTZALC, BLTZALC, BLTUC */=0A= + case 7:=0A= + if (is_mipsr6_isa (gdbarch)=0A= + && itype_rt (insn) !=3D 0)=0A= + return 2;=0A= + break;=0A= + /* BPOSGE32C */=0A= + case 1:=0A= + if (is_mipsr6_isa (gdbarch)=0A= + && itype_rt (insn) =3D=3D 0x1d && itype_rs (insn) =3D=3D 0)=0A= + return 2;=0A= + }=0A= + return 0;=0A= +}=0A= +=0A= +/* Return true if a standard MIPS instruction at ADDR has a branch=0A= + forbidden slot (i.e. it is a conditional compact branch instruction). = */=0A= +=0A= +static bool=0A= +mips32_insn_at_pc_has_forbidden_slot (struct gdbarch *gdbarch, CORE_ADDR a= ddr)=0A= +{=0A= + int status;=0A= + ULONGEST insn =3D mips_fetch_instruction (gdbarch, ISA_MIPS, addr, &stat= us);=0A= + if (status)=0A= + return false;=0A= +=0A= + return mips32_instruction_is_compact_branch (gdbarch, insn) =3D=3D 2;=0A= +}=0A= +=0A= struct mips_frame_cache=0A= {=0A= CORE_ADDR base;=0A= @@ -3491,7 +3768,8 @@ mips32_scan_prologue (struct gdbarch *gdbarch,=0A= reg =3D high_word & 0x1f;=0A= =0A= if (high_word =3D=3D 0x27bd /* addiu $sp,$sp,-i */=0A= - || high_word =3D=3D 0x23bd /* addi $sp,$sp,-i */=0A= + || (high_word =3D=3D 0x23bd /* addi $sp,$sp,-i */=0A= + && !is_mipsr6_isa (gdbarch))=0A= || high_word =3D=3D 0x67bd) /* daddiu $sp,$sp,-i */=0A= {=0A= if (offset < 0) /* Negative stack adjustment? */=0A= @@ -3629,7 +3907,9 @@ mips32_scan_prologue (struct gdbarch *gdbarch,=0A= =0A= /* A jump or branch, or enough non-prologue insns seen? If so,=0A= then we must have reached the end of the prologue by now. */=0A= - if (prev_delay_slot || non_prologue_insns > 1)=0A= + if (prev_delay_slot=0A= + || non_prologue_insns > 1=0A= + || mips32_instruction_is_compact_branch (gdbarch, inst))=0A= break;=0A= =0A= prev_non_prologue_insn =3D this_non_prologue_insn;=0A= @@ -3935,6 +4215,59 @@ mips_addr_bits_remove (struct gdbarch *gdbarch, CORE= _ADDR addr)=0A= #define LLD_OPCODE 0x34=0A= #define SC_OPCODE 0x38=0A= #define SCD_OPCODE 0x3c=0A= +#define LLSC_R6_OPCODE 0x1f=0A= +#define LL_R6_FUNCT 0x36=0A= +#define LLE_FUNCT 0x2e=0A= +#define LLD_R6_FUNCT 0x37=0A= +#define SC_R6_FUNCT 0x26=0A= +#define SCE_FUNCT 0x1e=0A= +#define SCD_R6_FUNCT 0x27=0A= +=0A= +static bool=0A= +is_ll_insn (struct gdbarch *gdbarch, ULONGEST insn)=0A= +{=0A= + if (itype_op (insn) =3D=3D LL_OPCODE=0A= + || itype_op (insn) =3D=3D LLD_OPCODE)=0A= + return true;=0A= +=0A= + if (rtype_op (insn) =3D=3D LLSC_R6_OPCODE=0A= + && rtype_funct (insn) =3D=3D LLE_FUNCT=0A= + && (insn & 0x40) =3D=3D 0)=0A= + return true;=0A= +=0A= + /* Handle LL and LLP varieties. */=0A= + if (is_mipsr6_isa (gdbarch)=0A= + && rtype_op (insn) =3D=3D LLSC_R6_OPCODE=0A= + && (rtype_funct (insn) =3D=3D LL_R6_FUNCT=0A= + || rtype_funct (insn) =3D=3D LLD_R6_FUNCT=0A= + || rtype_funct (insn) =3D=3D LLE_FUNCT))=0A= + return true;=0A= +=0A= + return false;=0A= +}=0A= +=0A= +static bool=0A= +is_sc_insn (struct gdbarch *gdbarch, ULONGEST insn)=0A= +{=0A= + if (itype_op (insn) =3D=3D SC_OPCODE=0A= + || itype_op (insn) =3D=3D SCD_OPCODE)=0A= + return true;=0A= +=0A= + if (rtype_op (insn) =3D=3D LLSC_R6_OPCODE=0A= + && rtype_funct (insn) =3D=3D SCE_FUNCT=0A= + && (insn & 0x40) =3D=3D 0)=0A= + return true;=0A= +=0A= + /* Handle SC and SCP varieties. */=0A= + if (is_mipsr6_isa (gdbarch)=0A= + && rtype_op (insn) =3D=3D LLSC_R6_OPCODE=0A= + && (rtype_funct (insn) =3D=3D SC_R6_FUNCT=0A= + || rtype_funct (insn) =3D=3D SCD_R6_FUNCT=0A= + || rtype_funct (insn) =3D=3D SCE_FUNCT))=0A= + return true;=0A= +=0A= + return false;=0A= +}=0A= =0A= static std::vector=0A= mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)=0A= @@ -3947,10 +4280,11 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdb= arch, CORE_ADDR pc)=0A= int index;=0A= int last_breakpoint =3D 0; /* Defaults to 0 (no breakpoints placed). */= =0A= const int atomic_sequence_length =3D 16; /* Instruction sequence length.= */=0A= + bool is_mipsr6 =3D is_mipsr6_isa (gdbarch);=0A= =0A= insn =3D mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL);=0A= /* Assume all atomic sequences start with a ll/lld instruction. */=0A= - if (itype_op (insn) !=3D LL_OPCODE && itype_op (insn) !=3D LLD_OPCODE)= =0A= + if (!is_ll_insn (gdbarch, insn))=0A= return {};=0A= =0A= /* Assume that no atomic sequence is longer than "atomic_sequence_length= " =0A= @@ -3980,28 +4314,72 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdb= arch, CORE_ADDR pc)=0A= return {}; /* fallback to the standard single-step code. */=0A= case 4: /* BEQ */=0A= case 5: /* BNE */=0A= - case 6: /* BLEZ */=0A= - case 7: /* BGTZ */=0A= case 20: /* BEQL */=0A= case 21: /* BNEL */=0A= - case 22: /* BLEZL */=0A= - case 23: /* BGTTL */=0A= + case 22: /* BLEZL (BLEZC, BGEZC, BGEC) */=0A= + case 23: /* BGTZL (BGTZC, BLTZC, BLTC) */=0A= is_branch =3D 1;=0A= break;=0A= + case 6: /* BLEZ (BLEZALC, BGEZALC, BGEUC) */=0A= + case 7: /* BGTZ (BGTZALC, BLTZALC, BLTUC) */=0A= + if (is_mipsr6)=0A= + {=0A= + /* BLEZALC, BGTZALC */=0A= + if (itype_rs (insn) =3D=3D 0 && itype_rt (insn) !=3D 0)=0A= + return {}; /* fallback to the standard single-step code. */=0A= + /* BGEZALC, BLTZALC */=0A= + else if (itype_rs (insn) =3D=3D itype_rt (insn)=0A= + && itype_rt (insn) !=3D 0)=0A= + return {}; /* fallback to the standard single-step code. */=0A= + }=0A= + is_branch =3D 1;=0A= + break;=0A= + case 8: /* BOVC, BEQZALC, BEQC */=0A= + case 24: /* BNVC, BNEZALC, BNEC */=0A= + if (is_mipsr6)=0A= + is_branch =3D 1;=0A= + break;=0A= + case 50: /* BC */=0A= + case 58: /* BALC */=0A= + if (is_mipsr6)=0A= + return {}; /* fallback to the standard single-step code. */=0A= + break;=0A= + case 54: /* BEQZC, JIC */=0A= + case 62: /* BNEZC, JIALC */=0A= + if (is_mipsr6)=0A= + {=0A= + if (itype_rs (insn) =3D=3D 0) /* JIC, JIALC */=0A= + return {}; /* fallback to the standard single-step code. */=0A= + else=0A= + is_branch =3D 2; /* Marker for branches with a 21-bit offset. */=0A= + }=0A= + break;=0A= case 17: /* COP1 */=0A= - is_branch =3D ((itype_rs (insn) =3D=3D 9 || itype_rs (insn) =3D=3D 10)= =0A= - && (itype_rt (insn) & 0x2) =3D=3D 0);=0A= - if (is_branch) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */=0A= + is_branch =3D ((!is_mipsr6=0A= + /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */=0A= + && (itype_rs (insn) =3D=3D 9 || itype_rs (insn) =3D=3D 10)=0A= + && (itype_rt (insn) & 0x2) =3D=3D 0)=0A= + /* BZ.df: 010001 110xx */=0A= + || (itype_rs (insn) & 0x18) =3D=3D 0x18);=0A= + if (is_branch)=0A= break;=0A= /* Fall through. */=0A= case 18: /* COP2 */=0A= case 19: /* COP3 */=0A= - is_branch =3D (itype_rs (insn) =3D=3D 8); /* BCzF, BCzFL, BCzT, BCzTL *= /=0A= + /* BCzF, BCzFL, BCzT, BCzTL, BC*EQZ, BC*NEZ */=0A= + is_branch =3D ((itype_rs (insn) =3D=3D 8)=0A= + || (is_mipsr6=0A= + && (itype_rs (insn) =3D=3D 9=0A= + || itype_rs (insn) =3D=3D 13)));=0A= break;=0A= }=0A= if (is_branch)=0A= {=0A= - branch_bp =3D loc + mips32_relative_offset (insn) + 4;=0A= + /* Is this a special PC21_S2 branch? */=0A= + if (is_branch =3D=3D 2)=0A= + branch_bp =3D loc + mips32_relative_offset21 (insn) + 4;=0A= + else=0A= + branch_bp =3D loc + mips32_relative_offset (insn) + 4;=0A= if (last_breakpoint >=3D 1)=0A= return {}; /* More than one branch found, fallback to the=0A= standard single-step code. */=0A= @@ -4009,12 +4387,12 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdb= arch, CORE_ADDR pc)=0A= last_breakpoint++;=0A= }=0A= =0A= - if (itype_op (insn) =3D=3D SC_OPCODE || itype_op (insn) =3D=3D SCD_O= PCODE)=0A= + if (is_sc_insn (gdbarch, insn))=0A= break;=0A= }=0A= =0A= /* Assume that the atomic sequence ends with a sc/scd instruction. */= =0A= - if (itype_op (insn) !=3D SC_OPCODE && itype_op (insn) !=3D SCD_OPCODE)= =0A= + if (!is_sc_insn (gdbarch, insn))=0A= return {};=0A= =0A= loc +=3D MIPS_INSN32_SIZE;=0A= @@ -4239,8 +4617,14 @@ mips_about_to_return (struct gdbarch *gdbarch, CORE_= ADDR pc)=0A= gdb_assert (mips_pc_is_mips (pc));=0A= =0A= insn =3D mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);=0A= - hint =3D 0x7c0;=0A= - return (insn & ~hint) =3D=3D 0x3e00008; /* jr(.hb) $ra */=0A= + /* Mask the hint and the jalr/jr bit. */=0A= + hint =3D 0x7c1;=0A= +=0A= + if (is_mipsr6_isa (gdbarch) && insn =3D=3D 0xd81f0000) /* jrc $31 */=0A= + return 1;=0A= +=0A= + /* jr(.hb) $ra and "jalr(.hb) $ra" */=0A= + return ((insn & ~hint) =3D=3D 0x3e00008);=0A= }=0A= =0A= =0A= @@ -6758,7 +7142,9 @@ mips32_stack_frame_destroyed_p (struct gdbarch *gdbar= ch, CORE_ADDR pc)=0A= =0A= if (high_word !=3D 0x27bd /* addiu $sp,$sp,offset */=0A= && high_word !=3D 0x67bd /* daddiu $sp,$sp,offset */=0A= - && inst !=3D 0x03e00008 /* jr $ra */=0A= + && (inst & ~0x1) !=3D 0x03e00008 /* jr $31 or jalr $0, $31 */=0A= + && (!is_mipsr6_isa (gdbarch)=0A= + || inst !=3D 0xd81f0000) /* jrc $31 */=0A= && inst !=3D 0x00000000) /* nop */=0A= return 0;=0A= }=0A= @@ -7136,22 +7522,31 @@ mips32_instruction_has_delay_slot (struct gdbarch *= gdbarch, ULONGEST inst)=0A= int op;=0A= int rs;=0A= int rt;=0A= + bool is_mipsr6 =3D is_mipsr6_isa (gdbarch);=0A= =0A= op =3D itype_op (inst);=0A= if ((inst & 0xe0000000) !=3D 0)=0A= {=0A= rs =3D itype_rs (inst);=0A= rt =3D itype_rt (inst);=0A= - return (is_octeon_bbit_op (op, gdbarch) =0A= - || op >> 2 =3D=3D 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */=0A= - || op =3D=3D 29 /* JALX: bits 011101 */=0A= + return (is_octeon_bbit_op (op, gdbarch)=0A= + || (op >> 1 =3D=3D 10) /* BEQL, BNEL: bits 01010x */=0A= + || (op >> 1 =3D=3D 11 && rt =3D=3D 0) /* BLEZL, BGTZL: bits 01011x = */=0A= + || (!is_mipsr6 && op =3D=3D 29) /* JALX: bits 011101 */=0A= || (op =3D=3D 17=0A= && (rs =3D=3D 8=0A= /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */=0A= - || (rs =3D=3D 9 && (rt & 0x2) =3D=3D 0)=0A= + || (!is_mipsr6 && rs =3D=3D 9 && (rt & 0x2) =3D=3D 0)=0A= /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */=0A= - || (rs =3D=3D 10 && (rt & 0x2) =3D=3D 0))));=0A= + || (!is_mipsr6 && rs =3D=3D 10 && (rt & 0x2) =3D=3D 0)))=0A= /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */=0A= + || (is_mipsr6=0A= + && ((op =3D=3D 17=0A= + && (rs =3D=3D 9 /* BC1EQZ: 010001 01001 */=0A= + || rs =3D=3D 13)) /* BC1NEZ: 010001 01101 */=0A= + || (op =3D=3D 18=0A= + && (rs =3D=3D 9 /* BC2EQZ: 010010 01001 */=0A= + || rs =3D=3D 13))))); /* BC2NEZ: 010010 01101 */=0A= }=0A= else=0A= switch (op & 0x07) /* extract bits 28,27,26 */=0A= @@ -7170,7 +7565,11 @@ mips32_instruction_has_delay_slot (struct gdbarch *g= dbarch, ULONGEST inst)=0A= || ((rt & 0x1e) =3D=3D 0x1c && rs =3D=3D 0));=0A= /* BPOSGE32, BPOSGE64: bits 1110x */=0A= break; /* end REGIMM */=0A= - default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */=0A= + case 6: /* BLEZ */=0A= + case 7: /* BGTZ */=0A= + return (itype_rt (inst) =3D=3D 0);=0A= + break;=0A= + default: /* J, JAL, BEQ, BNE */=0A= return 1;=0A= break;=0A= }=0A= @@ -7382,7 +7781,18 @@ mips_adjust_breakpoint_address (struct gdbarch *gdba= rch, CORE_ADDR bpaddr)=0A= =0A= So, we'll use the second solution. To do this we need to know if=0A= the instruction we're trying to set the breakpoint on is in the=0A= - branch delay slot. */=0A= + branch delay slot.=0A= +=0A= + A similar problem occurs for breakpoints on forbidden slots where=0A= + the trap will be reported for the branch with the BD bit set.=0A= + In this case it would be ideal to recover using solution 1 from=0A= + above as there is no problem with the branch being skipped=0A= + (since the forbidden slot only exists on not-taken branches).=0A= + However, the BD bit is not available in all scenarios currently=0A= + so instead we move the breakpoint on to the next instruction.=0A= + This means that it is not possible to stop on an instruction=0A= + that can be in a forbidden slot even if that instruction is=0A= + jumped to directly. */=0A= =0A= boundary =3D mips_segment_boundary (bpaddr);=0A= =0A= @@ -7404,6 +7814,12 @@ mips_adjust_breakpoint_address (struct gdbarch *gdba= rch, CORE_ADDR bpaddr)=0A= prev_addr =3D bpaddr - 4;=0A= if (mips32_insn_at_pc_has_delay_slot (gdbarch, prev_addr))=0A= bpaddr =3D prev_addr;=0A= + /* If the previous instruction has a forbidden slot, we have to=0A= + move the breakpoint to the following instruction to prevent=0A= + breakpoints in forbidden slots being reported as unknown=0A= + traps. */=0A= + else if (mips32_insn_at_pc_has_forbidden_slot (gdbarch, prev_addr))= =0A= + bpaddr +=3D 4;=0A= }=0A= else=0A= {=0A= -- =0A= 2.34.1=0A= =0A=