From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR02-AM5-obe.outbound.protection.outlook.com (mail-eopbgr00084.outbound.protection.outlook.com [40.107.0.84]) by sourceware.org (Postfix) with ESMTPS id 46141385C318 for ; Mon, 27 Jun 2022 08:38:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 46141385C318 ARC-Seal: i=2; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=pass; b=oedMwAmT+s48sYg+NUgTTyc27Hb1PNBOXlwHqSH/0/hOioJYutg+5hQhETg2bEg4rVnwOsVz+7dZcs91Kh/A635k9MrARFnzHoXzU79EfzAxscaQkmUU/8QCtsWkY0UDzKTINSuOLleF8ZzntgQxnsdCECN4pHZVzns5H3S91yRqlhIJ6m/72MjV6NjMKKKmjrrOh448vFr9MHHFk3ForG7uIKVX4F6Do0u3Gpe6cKEKouyxwiwbN0TCggwcWn/vRkX3J8vGdPbeb+7HFcyhQaIBhQnOfNbJcEFSkSiD7NobxdTcAfz+nGmAE8z+hii4/aSkTlTK6+VAOJJIOChDxQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=rz1nctCRQgraqjVJ/XgCIoPt/Ze+4pRhvjfL7IDUW/4=; b=bMZ7CjT3119Zbaigs5AHvySAQ/ZsiiSYSWEo9dKugH9NlULEZ4NJkXNYtKb8+odOALgbgUCs9S/mCNJuoW3CHC1fd0cxQpSJ0iHliwrszMD6DT9SvpvY9+MSLl6hn6KcGa6fq/WiWd5LPvL1bQoy737MLeqU+gKl/i6/T2LXYB/YDn3LyNav0fBpt+XNmCRr3SHq2ALUjqGImzHS5BKGo3Bf6lZGLGmEDFmVG4uuMTfCX94CQxLAWfLrEY9vRcS5G5Q9cewhWgecjrsVP2HLcRkuZgSZcY4OWiRI8oHCwLKSG+BSVkOv6Ygtz644ToNtoZbdW0dmjEx+MbdJw+GjwA== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 63.35.35.123) smtp.rcpttodomain=sourceware.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dkim=[1,1,header.d=arm.com] dmarc=[1,1,header.from=arm.com]) Received: from DB7PR05CA0043.eurprd05.prod.outlook.com (2603:10a6:10:2e::20) by AS8PR08MB6632.eurprd08.prod.outlook.com (2603:10a6:20b:31c::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5373.16; Mon, 27 Jun 2022 08:38:50 +0000 Received: from DBAEUR03FT019.eop-EUR03.prod.protection.outlook.com (2603:10a6:10:2e:cafe::47) by DB7PR05CA0043.outlook.office365.com (2603:10a6:10:2e::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5273.22 via Frontend Transport; Mon, 27 Jun 2022 08:38:50 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DBAEUR03FT019.mail.protection.outlook.com (100.127.142.129) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5373.15 via Frontend Transport; Mon, 27 Jun 2022 08:38:50 +0000 Received: ("Tessian outbound e40990bc24d7:v120"); Mon, 27 Jun 2022 08:38:45 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 82710b8b8f450a5a X-CR-MTA-TID: 64aa7808 Received: from ca9cde333181.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 7BFC1B6A-EA52-4652-A58B-DC5336673EA6.1; Mon, 27 Jun 2022 08:38:39 +0000 Received: from EUR02-VE1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id ca9cde333181.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Mon, 27 Jun 2022 08:38:39 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=UjYSGG/1m3pMsXX05JnJmQVzGJDKwGKdMV+IgxLqT/BYtd/ZGppO3n16xc/EaAcNBu31I1GJAQmIcxIPU5S6aVEa5kO7Afjr2HmCf062xUT7kO61dF6bOkXUJ1evbZMF8bQntwFCgqFnRBAttKKfQGG2WVIsFEQoJM+CJtrRBFjoQbWw65PIczgQnD4lq03QuxNWrTba/5wNqy+zfvJTGpaR9BxGCPUJiz5OFKgHzOM+pRvbBm20GeR4Y9syu1I2hi03S1dBBUjWj8NhMxsiJS859tsTnusXl5q1mnhbvMPdKly+4dkrgHGm3XxslbXzTwXDubqpusmriajIHQN+2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=rz1nctCRQgraqjVJ/XgCIoPt/Ze+4pRhvjfL7IDUW/4=; b=CPmuhDoEQHfAxnTguVx/Ry941bS8QF/3o66zvN6hNczf9KUNGhoywbEKsTsWIfO9L4ePtZbRQuW5tH91KKX0kUkpw+oAAZ7+sbkxH418qJjgAhVq0uK8ULq9NZTBE7fwfYZToBQF03/shnDPekrhYHj3iFqQGUN6VIhuYaImN5eX5ZYkGqkJBPRKFrVGh+DSy4qgvPbi6VL3ENxW16fbwtMfMeRV57QT9fLVnlv9J1W7/m++mdcfE7FKyBJqCf9mSx/feaiVK2h3mBWLo14Sv8/uet3EJ45NXHyuHfyYaI2wu9DwRUkm2l/USdxeg+DGB6Uu/Db7ZrUueogKuzhdyQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Received: from VI1PR08MB3919.eurprd08.prod.outlook.com (2603:10a6:803:c4::31) by DU0PR08MB7488.eurprd08.prod.outlook.com (2603:10a6:10:358::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5373.17; Mon, 27 Jun 2022 08:38:36 +0000 Received: from VI1PR08MB3919.eurprd08.prod.outlook.com ([fe80::1cda:8ca1:6353:572c]) by VI1PR08MB3919.eurprd08.prod.outlook.com ([fe80::1cda:8ca1:6353:572c%4]) with mapi id 15.20.5373.018; Mon, 27 Jun 2022 08:38:36 +0000 Message-ID: Date: Mon, 27 Jun 2022 09:38:34 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [PATCH] gdb/arm: Unwind Non-Secure callbacks from Secure Content-Language: en-US To: Yvan Roux , gdb-patches@sourceware.org Cc: Torbjorn SVENSSON References: <20220617125000.GA5800@gnbcxd0114.gnb.st.com> <16e5e509-7094-df0d-285e-f8a676ed251b@arm.com> <20220624160525.GA30742@gnbcxd0114.gnb.st.com> From: Luis Machado In-Reply-To: <20220624160525.GA30742@gnbcxd0114.gnb.st.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: LO4P123CA0201.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:1a5::8) To VI1PR08MB3919.eurprd08.prod.outlook.com (2603:10a6:803:c4::31) MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: 29e5ebb7-1fac-422e-f159-08da5818759c X-MS-TrafficTypeDiagnostic: DU0PR08MB7488:EE_|DBAEUR03FT019:EE_|AS8PR08MB6632:EE_ x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: aOMiJa3rW5d5e2lBSRondDn4+AI9qPXTb3n7rgJQZzr/y2+mrXmRcvgm0GhZM0rNLbKg3KFCjz9Oi4O6i6Eq8hJSvlVLmSv6VGbVzoWo1dXeh+91Pygyv4AwULbHk+lMh7XZStbkWGjih/4bUUl0pCBcjPoTNLc2nwsbiWILCvT7j9qaA4FPxYDfIOX5Nh4ub55cJyeQPF1nm0XsvNo7rpAgx3AGq970cU9PlAmGTFmVGaoG7wrVUnB6cYo6fiiQMYtKvY9IvrG0J4cvTHt8YPDu29QFLUI53EQhz+iBTDIDvkq+7Nwrew6vmZ1DQ7RZpDTjZG6w0+oDa3qLa3+JZxWxvx4lL/zdDtDeAsPVWT1Oe4mJAlOlPGRpRDk7SDCP3sw13OYRUw/7MwrRTrogZqJV9940Eho6QcVAqxBdgODSdwGmOVG9EWYbjR+8POR7BAHO7Z9AojHr0z6udMDImnbvoCr/dBNzdxNQ43dxQHPAsOKHqpDdU42At4D0t9snohEjnLKs83e1qoiAEfK6KXTSEU25joAYs0NzghbfY5CiUcp5PJbhj91ZVFFrn1Xd4xTabrUHswixqDjaOdvhRqyLy49nYeYt75FaUfQfgygRblAdPf1mWF+tO4/m1qa3zNvDBjcaMXSKJRp0W0WPnglBUdlQ+M5tp9MpReA+Maz/0Q8Y5utjv0/01rrLhKTESnbN+LpP+voqWSD9lSkuD/DnGMslAh4pfs2R04hRikBHJieuHNBhEjP0XmDUMV5X8sokb1oj+9utT09lq3MhnNCKe/ECBARvvN3FsSmn9I8f3s75KtkRNmuxec0w5bJY X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:VI1PR08MB3919.eurprd08.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230016)(4636009)(136003)(396003)(346002)(39860400002)(376002)(366004)(38100700002)(2906002)(8936002)(66556008)(316002)(66946007)(66476007)(8676002)(30864003)(44832011)(4326008)(5660300002)(83380400001)(6512007)(6506007)(26005)(53546011)(186003)(6486002)(478600001)(66574015)(31686004)(41300700001)(2616005)(36756003)(86362001)(31696002)(43740500002)(45980500001); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB7488 Original-Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DBAEUR03FT019.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 62072007-fba1-4352-aa5d-08da58186d0b X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ud2yKGDz4CiUSB4d6psU6dKRaLgHQXZOQRhhrvnTJo+YNbX4YHRLT+RqOdEzfskHP9Q3Q9nRAmO3rSwJJ1gho1g6Oqan/r0ZnH5FliL06+r55QH0OnJvXH3k+nGUZyIrIjVa7tzT65Yt2ozsYkYicwPIWX1QXetEelrDH0dQvj9QEZgiz4UMjiL8oF6vQ2PTnryG90nU1k9YrK2eUAIVMyJx3IJ25r6cOXvN9+yPkc6W6BWFDo5nNAO2v1G3EeB9PONgiPjXHqj4KY6IUC6yKntI8DZwIhaYZ/iU6y3LxgTlg69mo0tqtRCjo/57OXA1ZXDx8g/xmn0vHWXX2C3+/ir/VXYCLdNfTxn0fvos35SrieocOSdrZ9xz0WC9p2E3+O3kKyXtw7Y8kiQwV5uIr4CUiEq3MUqXvpt1ki5xb/7xtpiLQop0vGBv9gGKHtNICro06pzjOYtPavXlYpwSulrjlDKSCNxep8XtiPf6lulWBkZPhfOuhW46PubntA9vVlEfU39a1davigzGr8BxGBiY4x1lo8LqaE8S6sDJ59LkDDO4EPlx35HwsWfm014VfjdzLf4pfNfkxXbw7Dim68rreUM6o8ChYcfSvs3ccvOwUJMPVsZbSpdrUPg/PeGCwotWcUmaEsHPVrC8Ohy0PTH5Gt49aqYSfWrsw06IhtWWq5G1VQj70+LnfGLwP6f48kcZ2OA8UxGbhYRPH7nJvV8BgiM8+JY/h3ABLUDPQZ+6eTUY7W/au0GUvvlTi0BVDq6fEhR99wHEFFKdJFgMViKeJgoUmodz7iwiXckZZJ+0BBtsFrG+Cp0tnugulOQc2J8RFAVhkcTaqF5YbNUclQ== X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230016)(4636009)(396003)(346002)(376002)(136003)(39860400002)(46966006)(40470700004)(36840700001)(6506007)(70586007)(82740400003)(2616005)(44832011)(70206006)(66574015)(41300700001)(6486002)(336012)(83380400001)(186003)(53546011)(82310400005)(31686004)(86362001)(26005)(478600001)(36756003)(47076005)(31696002)(8676002)(316002)(356005)(36860700001)(4326008)(5660300002)(40460700003)(30864003)(2906002)(40480700001)(6512007)(8936002)(81166007)(43740500002); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jun 2022 08:38:50.1869 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 29e5ebb7-1fac-422e-f159-08da5818759c X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT019.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB6632 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, NICE_REPLY_A, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 27 Jun 2022 08:38:58 -0000 On 6/24/22 17:05, Yvan Roux wrote: > Hi, > > Thanks for the review Luis, here is a new version of the patch. > > On Tue, Jun 21, 2022 at 12:28:07PM +0100, Luis Machado wrote: >> Hi, >> >> On 6/17/22 13:50, Yvan Roux wrote: >>> Hi, >>> >>> Without this changeset, the unwinding doesn't take into account >>> Non-Secure to Secure stack unwinding enablement status and >>> doesn't choose on the proper SP to do the unwinding. >> >> choose on -> choose? >> >>> >>> This patch only unwind the stack when Non-Secure to Secure >> >> unwind -> unwinds >>> unwinding is enabled, previous SP is set w/r to the current mode >>> (Handler -> msp_s, Thread -> psp_s) and then the Secure stack is >>> unwound. Ensure thumb bit is set in PSR when needed. Also, drop >>> thumb bit from PC if set. >> >> Also, two spaces after `.` according to the GNU Coding Standards. >> >>> >>> Signed-off-by: Torbjörn SVENSSON >>> Signed-off-by: Yvan ROUX >>> --- >>> gdb/arm-tdep.c | 121 +++++++++++++++++++++++++++++++++++++------------ >>> 1 file changed, 91 insertions(+), 30 deletions(-) >>> >>> diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c >>> index 0c907482036..8a84754cfa6 100644 >>> --- a/gdb/arm-tdep.c >>> +++ b/gdb/arm-tdep.c >>> @@ -309,6 +309,21 @@ struct arm_prologue_cache >>> arm_prologue_cache() = default; >>> }; >>> + >>> +/* Reconstruct T bit in program status register from LR value. */ >>> + >>> +static inline ULONGEST >>> +reconstruct_t_bit(struct gdbarch *gdbarch, CORE_ADDR lr, ULONGEST psr) >>> +{ >>> + ULONGEST t_bit = arm_psr_thumb_bit (gdbarch); >>> + if (IS_THUMB_ADDR (lr)) >>> + psr |= t_bit; >>> + else >>> + psr &= ~t_bit; >>> + >>> + return psr; >>> +} >>> + >>> /* Initialize stack pointers, and flag the active one. */ >>> static inline void >>> @@ -2342,15 +2357,10 @@ arm_prologue_prev_register (struct frame_info *this_frame, >>> but the processor status is likely valid. */ >>> if (prev_regnum == ARM_PS_REGNUM) >>> { >>> - CORE_ADDR lr, cpsr; >>> - ULONGEST t_bit = arm_psr_thumb_bit (gdbarch); >>> + ULONGEST cpsr = get_frame_register_unsigned (this_frame, prev_regnum); >>> + CORE_ADDR lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); >>> - cpsr = get_frame_register_unsigned (this_frame, prev_regnum); >>> - lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); >>> - if (IS_THUMB_ADDR (lr)) >>> - cpsr |= t_bit; >>> - else >>> - cpsr &= ~t_bit; >>> + cpsr = reconstruct_t_bit (gdbarch, lr, cpsr); >>> return frame_unwind_got_constant (this_frame, prev_regnum, cpsr); >>> } >>> @@ -3363,24 +3373,46 @@ arm_m_exception_cache (struct frame_info *this_frame) >>> return cache; >>> } >>> - fnc_return = ((lr & 0xfffffffe) == 0xfefffffe); >>> + fnc_return = (((lr >> 24) & 0xff) == 0xfe); >> >> Is the above throwing away the comparison with the lower byte 0xfe? > > Yes, it only checks the FNC_RETURN prefix for coherency with how EXC_RETURN is > handled and how it is also done in arm_m_addr_is_magic function (line 777), but > according to the reference manual bits [23:1] are all 1, so we can keep the > current comparison if you prefer. > Thanks for the explanation. No need to keep it if it doesn't make sense. I just wanted to make sure we're not dropping something that may be used by other targets. >>> if (tdep->have_sec_ext && fnc_return) >>> { >>> - int actual_sp; >>> + if (!arm_unwind_secure_frames) >>> + { >>> + warning (_("Non-secure to secure stack unwinding disabled.")); >>> - arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_msp_ns_regnum); >>> - arm_cache_set_active_sp_value (cache, tdep, sp); >>> - if (lr & 1) >>> - actual_sp = tdep->m_profile_msp_s_regnum; >>> + /* Terminate any further stack unwinding by referring to self. */ >>> + arm_cache_set_active_sp_value (cache, tdep, sp); >>> + return cache; >>> + } >>> + >>> + xpsr = get_frame_register_unsigned (this_frame, ARM_PS_REGNUM); >>> + if ((xpsr & 0xff) != 0) >>> + /* Handler mode */ >> >> What is the handler mode? Can we expand on that to make it clear? > > This is the mode in which exceptions are handled and Threadmode is the normal > or main mode where a program runs in, the comment are more explicits in this > new version of the patch. > Thanks. >>> + arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_msp_s_regnum); >>> else >>> - actual_sp = tdep->m_profile_msp_ns_regnum; >>> + /* Thread mode */ >> >> Similarly, what is the thread mode? >> >>> + arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_psp_s_regnum); >>> + >>> + unwound_sp = arm_cache_get_prev_sp_value (cache, tdep); >>> - arm_cache_switch_prev_sp (cache, tdep, actual_sp); >>> - sp = get_frame_register_unsigned (this_frame, actual_sp); >>> + /* Stack layout for a function call from Secure to Non-Secure state >>> + (ARMv8-M section B3.16): >>> - cache->saved_regs[ARM_LR_REGNUM].set_addr (sp); >>> + SP Offset >>> - arm_cache_set_active_sp_value (cache, tdep, sp + 8); >>> + +-------------------+ >>> + 0x08 | | >>> + +-------------------+ <-- Original SP >>> + 0x04 | Partial xPSR | >>> + +-------------------+ >>> + 0x00 | Return Address | >>> + +===================+ <-- New SP */ >>> + >>> + cache->saved_regs[ARM_PC_REGNUM].set_addr (unwound_sp + 0x00); >>> + cache->saved_regs[ARM_LR_REGNUM].set_addr (unwound_sp + 0x00); >>> + cache->saved_regs[ARM_PS_REGNUM].set_addr (unwound_sp + 0x04); >>> + >>> + arm_cache_set_active_sp_value (cache, tdep, unwound_sp + 0x08); >>> return cache; >>> } >>> @@ -3441,11 +3473,6 @@ arm_m_exception_cache (struct frame_info *this_frame) >>> arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_msp_regnum); >>> } >>> } >>> - else >>> - { >>> - /* Main stack used, use MSP as SP. */ >>> - arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_msp_regnum); >>> - } >>> /* Fetch the SP to use for this frame. */ >>> unwound_sp = arm_cache_get_prev_sp_value (cache, tdep); >>> @@ -3641,6 +3668,20 @@ arm_m_exception_prev_register (struct frame_info *this_frame, >>> return frame_unwind_got_constant (this_frame, prev_regnum, >>> arm_cache_get_prev_sp_value (cache, tdep)); >>> + /* If we are asked to unwind the PC, strip the saved T bit. */ >>> + if (prev_regnum == ARM_PC_REGNUM) >>> + { >>> + CORE_ADDR pc; >>> + struct value *value; >>> + >>> + value = trad_frame_get_prev_register (this_frame, cache->saved_regs, >>> + prev_regnum); >>> + >>> + pc = value_as_address (value); >>> + return frame_unwind_got_constant (this_frame, prev_regnum, >>> + UNMAKE_THUMB_ADDR (pc)); >>> + } >>> + >>> /* The value might be one of the alternative SP, if so, use the >>> value already constructed. */ >>> if (arm_cache_is_sp_register (cache, tdep, prev_regnum)) >>> @@ -3649,6 +3690,29 @@ arm_m_exception_prev_register (struct frame_info *this_frame, >>> return frame_unwind_got_constant (this_frame, prev_regnum, sp_value); >>> } >>> + /* If we are asked to unwind the xPSR, set T bit if PC is in thumb mode. >>> + * LR register is unreliable as it contains FNC_RETURN or EXC_RETURN pattern. >>> + */ >> >> I think this style of comments doesn't match GDB's coding standards. >> >>> + if (prev_regnum == ARM_PS_REGNUM) >>> + { >>> + CORE_ADDR pc; >>> + ULONGEST xpsr; >> >> >> You could declare both pc and xpsr at their assignment locations. >> >>> + struct value *value; >> >> Same thing as above. Declare it in its assignment. >> >>> + struct gdbarch *gdbarch = get_frame_arch (this_frame); >>> + >>> + value = trad_frame_get_prev_register (this_frame, cache->saved_regs, >>> + ARM_PC_REGNUM); >> >> here... >> >>> + pc = value_as_address (value); >> >> here... >>> + >>> + value = trad_frame_get_prev_register (this_frame, cache->saved_regs, >>> + ARM_PS_REGNUM); >>> + xpsr = value_as_long (value); >> >> and here. >>> + >>> + /* Reconstruct the T bit; see arm_prologue_prev_register for details. */ >> >> /* Reconstruct the T bit. See arm_prologue_prev_register for details. */ >> >>> + xpsr = reconstruct_t_bit (gdbarch, pc, xpsr); >>> + return frame_unwind_got_constant (this_frame, ARM_PS_REGNUM, xpsr); >>> + } >>> + >>> return trad_frame_get_prev_register (this_frame, cache->saved_regs, >>> prev_regnum); >>> } >>> @@ -3711,8 +3775,8 @@ arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache, >>> { >>> struct gdbarch * gdbarch = get_frame_arch (this_frame); >>> arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); >>> - CORE_ADDR lr, cpsr; >>> - ULONGEST t_bit = arm_psr_thumb_bit (gdbarch); >>> + CORE_ADDR lr; >>> + ULONGEST cpsr; >>> switch (regnum) >>> { >>> @@ -3741,10 +3805,7 @@ arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache, >>> /* Reconstruct the T bit; see arm_prologue_prev_register for details. */ >>> cpsr = get_frame_register_unsigned (this_frame, regnum); >>> lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); >>> - if (IS_THUMB_ADDR (lr)) >>> - cpsr |= t_bit; >>> - else >>> - cpsr &= ~t_bit; >>> + cpsr = reconstruct_t_bit (gdbarch, lr, cpsr); >>> return frame_unwind_got_constant (this_frame, regnum, cpsr); >>> default > > Updated version: > > gdb/arm: Unwind Non-Secure callbacks from Secure > > Without this changeset, the unwinding doesn't take into account > Non-Secure to Secure stack unwinding enablement status and > doesn't choose the proper SP to do the unwinding. > > This patch only unwinds the stack when Non-Secure to Secure > unwinding is enabled, previous SP is set w/r to the current mode > (Handler -> msp_s, Thread -> psp_s) and then the Secure stack is > unwound. Ensure thumb bit is set in PSR when needed. Also, drop > thumb bit from PC if set. > > Signed-off-by: Torbjörn SVENSSON > Signed-off-by: Yvan ROUX > --- > gdb/arm-tdep.c | 117 ++++++++++++++++++++++++++++++++++++------------- > 1 file changed, 87 insertions(+), 30 deletions(-) > > diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c > index 96d70d40b28..8ae0c9fecd7 100644 > --- a/gdb/arm-tdep.c > +++ b/gdb/arm-tdep.c > @@ -309,6 +309,21 @@ struct arm_prologue_cache > arm_prologue_cache() = default; > }; > > + > +/* Reconstruct T bit in program status register from LR value. */ > + > +static inline ULONGEST > +reconstruct_t_bit(struct gdbarch *gdbarch, CORE_ADDR lr, ULONGEST psr) > +{ > + ULONGEST t_bit = arm_psr_thumb_bit (gdbarch); > + if (IS_THUMB_ADDR (lr)) > + psr |= t_bit; > + else > + psr &= ~t_bit; > + > + return psr; > +} > + > /* Initialize stack pointers, and flag the active one. */ > > static inline void > @@ -2348,15 +2363,10 @@ arm_prologue_prev_register (struct frame_info *this_frame, > but the processor status is likely valid. */ > if (prev_regnum == ARM_PS_REGNUM) > { > - CORE_ADDR lr, cpsr; > - ULONGEST t_bit = arm_psr_thumb_bit (gdbarch); > + ULONGEST cpsr = get_frame_register_unsigned (this_frame, prev_regnum); > + CORE_ADDR lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); > > - cpsr = get_frame_register_unsigned (this_frame, prev_regnum); > - lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); > - if (IS_THUMB_ADDR (lr)) > - cpsr |= t_bit; > - else > - cpsr &= ~t_bit; > + cpsr = reconstruct_t_bit (gdbarch, lr, cpsr); > return frame_unwind_got_constant (this_frame, prev_regnum, cpsr); > } > > @@ -3369,24 +3379,46 @@ arm_m_exception_cache (struct frame_info *this_frame) > return cache; > } > > - fnc_return = ((lr & 0xfffffffe) == 0xfefffffe); > + fnc_return = (((lr >> 24) & 0xff) == 0xfe); > if (tdep->have_sec_ext && fnc_return) > { > - int actual_sp; > + if (!arm_unwind_secure_frames) > + { > + warning (_("Non-secure to secure stack unwinding disabled.")); > > - arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_msp_ns_regnum); > - arm_cache_set_active_sp_value (cache, tdep, sp); > - if (lr & 1) > - actual_sp = tdep->m_profile_msp_s_regnum; > + /* Terminate any further stack unwinding by referring to self. */ > + arm_cache_set_active_sp_value (cache, tdep, sp); > + return cache; > + } > + > + xpsr = get_frame_register_unsigned (this_frame, ARM_PS_REGNUM); > + if ((xpsr & 0xff) != 0) > + /* Handler mode: This is mode that exceptions are handled in. */ This is mode -> This is the mode. Otherwise LGTM. Thanks!