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From: will schmidt <will_schmidt@vnet.ibm.com>
To: gdb-patches@sourceware.org
Cc: Ulrich Weigand <Ulrich.Weigand@de.ibm.com>,
	rogerio <rogealve@br.ibm.com>,
	Andrew Burgess <andrew.burgess@embecosm.com>
Subject: Re: [PATCH,rs6000, v2]  GDB testcases for exercising breakpoints over PC-Relative instructions
Date: Mon, 29 Mar 2021 17:43:58 -0500	[thread overview]
Message-ID: <a4f7181bb5bb22369eb56fb160c2b96efee2a5fd.camel@vnet.ibm.com> (raw)
In-Reply-To: <f75ec92bc04539d097869b57b1f919a038b51eb8.camel@vnet.ibm.com>


Hi,
  This is V2 of this patch.  Multiple updates per feedback received.
Thanks,
-Will

[v1]
  A few testcases to exercise powerpc PC-Relative instructions.
These exercise single-stepping over prefixed instructions and
verifying the loaded values are correct when we have single-stepped
over an instruction that was executed from a displaced
location.

This is meant to assure that
- single stepping over a prefixed instruction succeeds, in particular to
confirm that an 8-byte instruction is properly handled.
- An instruction that references the PC/NIA is properly fixed-up upon
completion.

[v2]
  Updated tests to use standard_testfile ; updated to use prepare_for_testing.
Multiple whitespace/indentation updates.
Updated -regex checks to use -wrap.   Copyright notices added.  Comments
updated and corrected in tests.


YYYY-MM-DD  Will Schmidt  <will_schmidt@vnet.ibm.com>

	gdb/testsuite/ChangeLog:
	* gdb.arch/powerpc-breakpoint-on-prefix-insn.s:  Testcase with
	pnop and pcrelative plxv instructions.
	* gdb.arch/powerpc-breakpoint-on-prefix-insn.exp: Testcase harness.
	* gdb.arch/powerpc-plxv.s:  Testcase with plxv and nop instructions.
	* gdb.arch/powerpc-plxv.exp:  Testcase harness.


diff --git a/gdb/testsuite/gdb.arch/powerpc-breakpoint-on-prefix-insn.exp b/gdb/testsuite/gdb.arch/powerpc-breakpoint-on-prefix-insn.exp
new file mode 100644
index 00000000000..2f83695f19d
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/powerpc-breakpoint-on-prefix-insn.exp
@@ -0,0 +1,132 @@
+# Copyright 2021 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+# Test to see if gdb is properly single stepping over the
+# displaced plxv instruction.   Depending on the Relocation flag
+# which is part of the instruction encoding, the plxv instruction
+# indicates that data is loaded from either an offset(address) or
+# from a location at an offset from the current instruction address.
+#
+
+if { ![istarget powerpc*-*] } {
+    verbose "Skipping powerpc plxv test."
+    return
+}
+
+set retval 0
+
+standard_testfile .s
+
+if { [prepare_for_testing "failed to prepare" $testfile "$srcfile" \
+      {debug quiet}] } {
+    return -1
+}
+
+if ![runto_main] then {
+      return
+}
+
+gdb_test "set radix 0b10000"
+gdb_test "set debug displaced"
+
+# Proc to extract the uint128 hex value from the output of
+# a print vs##.uint128 output.
+proc get_vector_hexadecimal_valueof { exp default {test ""} } {
+    global gdb_prompt
+    set val 0xeeee
+    if {$test == ""} {
+	set test "get_vector_hexadecimal_valueof \"${exp}\""
+    }
+    gdb_test_multiple "print $${exp}.uint128" $test {
+	-re -wrap  "\\$\[0-9\]* = (0x\[0-9a-zA-Z\]+).*" {
+	    set val $expect_out(1,string)
+	    pass "$test"
+	}
+    }
+    return ${val}
+}
+
+# Proc to do a single-step, and ensure we gently handle
+# an illegal instruction situation.
+proc stepi_over_instruction { xyz } {
+    global gdb_prompt
+    gdb_test_multiple "stepi" "${xyz} " {
+         -re ".*Illegal instruction.*${gdb_prompt}" {
+	    fail "Illegal instruction on single step."
+	    return
+	 }
+	 -re ".*${gdb_prompt}" {
+	     pass "stepi ${xyz}"
+         }
+    }
+}
+
+set check_pc [get_hexadecimal_valueof "\$pc" "default0"]
+
+# Set some breakpoints on the instructions below main().
+gdb_test "info reg pc"
+gdb_test "disas /r main"
+set bp1 *$check_pc+8
+set bp2 *$check_pc+0d16
+set bp3 *$check_pc+0d24
+set bp4 *$check_pc+0d32
+set bp5 *$check_pc+0d40
+set bp6 *$check_pc+0
+gdb_breakpoint $bp1
+gdb_breakpoint $bp2
+gdb_breakpoint $bp3
+gdb_breakpoint $bp4
+gdb_breakpoint $bp5
+gdb_breakpoint $bp6
+gdb_test "info break"
+
+# Single-step through the plxv instructions, and see what happens.
+# If the breakpoints are improperly set, these will fail with
+# illegal instruction errors.
+stepi_over_instruction "stepi over pnop 1"
+stepi_over_instruction "stepi over vs4 assignment"
+stepi_over_instruction "stepi over pnop 2"
+stepi_over_instruction "stepi over vs5 assignment"
+stepi_over_instruction "stepi over pnop 3"
+stepi_over_instruction "stepi over vs6 assignment"
+stepi_over_instruction "stepi over pnop 4"
+stepi_over_instruction "stepi over vs7 assignment"
+stepi_over_instruction "stepi over pnop"
+
+set check_vs4 [get_vector_hexadecimal_valueof "vs4" "default0"]
+set check_vs5 [get_vector_hexadecimal_valueof "vs5" "default0"]
+set check_vs6 [get_vector_hexadecimal_valueof "vs6" "default0"]
+set check_vs7 [get_vector_hexadecimal_valueof "vs7" "default0"]
+
+set vs4_expected 0xa5b5c5d5a4b4c4d4a3b3c3d3a2b2c2d2
+set vs5_expected 0xa7b7c7d7a6b6c6d6a5b5c5d5a4b4c4d4
+set vs6_expected 0xa9b9c9d9a8b8c8d8a7b7c7d7a6b6c6d6
+set vs7_expected 0xabbbcbdbaabacadaa9b9c9d9a8b8c8d8
+
+if [expr  $check_vs4 != $vs4_expected] {
+    fail "unexpected value vs4;  actual:$check_vs4 expected:$vs4_expected"
+}
+if [expr $check_vs5 != $vs5_expected ] {
+    fail "unexpected value vs5;   actual:$check_vs5 expected:$vs5_expected"
+}
+if [expr $check_vs6 != $vs6_expected ] {
+    fail "unexpected value vs6;   actual:$check_vs6 expected:$vs6_expected"
+}
+if [expr $check_vs7 != $vs7_expected ] {
+    fail "unexpected value vs7;   actual:$check_vs7 expected:$vs7_expected"
+}
+
+gdb_test "info register vs4 vs5 vs6 vs7 "
+
diff --git a/gdb/testsuite/gdb.arch/powerpc-breakpoint-on-prefix-insn.s b/gdb/testsuite/gdb.arch/powerpc-breakpoint-on-prefix-insn.s
new file mode 100644
index 00000000000..b04364be85b
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/powerpc-breakpoint-on-prefix-insn.s
@@ -0,0 +1,44 @@
+/* This testcase is part of GDB, the GNU debugger.
+
+   Copyright 2021 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>. */
+
+.global main
+.type main,function
+main:
+	pnop
+	plxv 4,0x48(0),1
+	pnop
+	plxv 5,0x40(0),1
+	pnop
+	plxv 6,0x38(0),1
+	pnop
+	plxv 7,0x30(0),1
+	pnop
+	blr
+mydata:
+	.long 0xa1b1c1d1	# <<-
+	.long 0xa2b2c2d2	# <<- loaded into vs4
+	.long 0xa3b3c3d3	# <<- loaded into vs4
+	.long 0xa4b4c4d4	# <<- loaded into vs4, vs5
+	.long 0xa5b5c5d5	# <<- loaded into vs4, vs5
+	.long 0xa6b6c6d6	# <<- loaded into      vs5, vs6
+	.long 0xa7b7c7d7	# <<- loaded into      vs5, vs6
+	.long 0xa8b8c8d8	# <<- loaded into           vs6, vs7
+	.long 0xa9b9c9d9	# <<- loaded into           vs6, vs7
+	.long 0xaabacada	# <<- loaded into                vs7
+	.long 0xabbbcbdb	# <<- loaded into                vs7
+	.long 0xacbcccdc	# <<-
+
diff --git a/gdb/testsuite/gdb.arch/powerpc-plxv.exp b/gdb/testsuite/gdb.arch/powerpc-plxv.exp
new file mode 100644
index 00000000000..69e4f328bc8
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/powerpc-plxv.exp
@@ -0,0 +1,137 @@
+# Copyright 2021 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+# Test to see if gdb is properly single stepping over the
+# displaced plxv instruction.
+# plxv is an extended mnemonic for the addpcis instruction, which
+# stores the $NIA plus an immediate value into a register.
+#
+#		plxv Rx == addpcis Rx,0 == plxv Rx
+#		subcis Rx,value == addpcis Rx,-value
+
+if { ![istarget powerpc*-*] } {
+    verbose "Skipping powerpc plxv test."
+    return
+}
+
+set retval 0
+
+set testfile "powerpc-plxv"
+set srcfile ${testfile}.s
+set binfile [standard_output_file ${testfile}]
+
+if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {}] != "" } {
+    untested "PowerPC plxv test"
+    return -1
+}
+
+gdb_exit
+gdb_start
+gdb_load ${binfile}
+gdb_test "set radix 0b10000"
+gdb_test "set debug displaced"
+
+if ![runto_main] then {
+      return
+}
+
+# Proc to extract the uint128 hex value from the output of
+# a print vs##.uint128 output.
+proc get_vector_hexadecimal_valueof { exp default {test ""} } {
+	set val "0x0000"
+	global gdb_prompt
+	if {$test == ""} {
+		set test "get vector_hexadecimal valueof \"${exp}\""
+	}
+	gdb_test_multiple "print $${exp}.uint128" $test {
+		-re "\\$\[0-9\]* = (0x\[0-9a-zA-Z\]+).*$gdb_prompt $" {
+			set val $expect_out(1,string)
+				pass "$test"
+		}
+		-re ".*Illegal instruction.*${gdb_prompt} $" {
+			fail "Illegal instruction on print."
+			set val 0xffff
+		}
+	}
+	return ${val}
+}
+
+# Proc to do a single-step, and ensure we gently handle
+# an illegal instruction situation.
+proc stepi_over_instruction { xyz } {
+	global gdb_prompt
+	gdb_test_multiple "stepi" "${xyz} " {
+		-re ".*Illegal instruction.*${gdb_prompt}" {
+		    fail "Illegal instruction on single step."
+		return
+		}
+		-re ".*${gdb_prompt}" {
+		 pass "stepi ${xyz}"
+		}
+	}
+}
+
+set check_pc [get_hexadecimal_valueof "\$pc" "default0"]
+
+# Set some breakpoints on the instructions below main().
+gdb_test "disas /r main"
+set bp1 *$check_pc+4
+set bp2 *$check_pc+0d12
+set bp3 *$check_pc+0d20
+set bp4 *$check_pc+0d28
+gdb_breakpoint $bp1
+gdb_breakpoint $bp2
+gdb_breakpoint $bp3
+gdb_breakpoint $bp4
+
+# Single-step through the plxv instructions, and retrieve the
+# register values as we proceed.
+
+stepi_over_instruction  "stepi over NOP"
+
+stepi_over_instruction  "stepi over vs4 assignment"
+set check_vs4 [get_vector_hexadecimal_valueof "vs4" "default0"]
+
+stepi_over_instruction  "stepi over vs5 assignment"
+set check_vs5 [get_vector_hexadecimal_valueof "vs5" "default0"]
+
+stepi_over_instruction  "stepi over vs6 assignment"
+set check_vs6 [get_vector_hexadecimal_valueof "vs6" "default0"]
+
+stepi_over_instruction  "stepi over vs7 assignment"
+set check_vs7 [get_vector_hexadecimal_valueof "vs7" "default0"]
+
+set vs4_expected 0xa5b5c5d5a4b4c4d4a3b3c3d3a2b2c2d2
+set vs5_expected 0xa7b7c7d7a6b6c6d6a5b5c5d5a4b4c4d4
+set vs6_expected 0xa9b9c9d9a8b8c8d8a7b7c7d7a6b6c6d6
+set vs7_expected 0xabbbcbdbaabacadaa9b9c9d9a8b8c8d8
+
+if [expr  $check_vs4 != $vs4_expected] {
+    fail "unexpected value vs4;  actual:$check_vs4 expected:$vs4_expected"
+}
+if [expr $check_vs5 != $vs5_expected ] {
+    fail "unexpected value vs5;   actual:$check_vs5 expected:$vs5_expected"
+}
+if [expr $check_vs6 != $vs6_expected ] {
+    fail "unexpected value vs6;   actual:$check_vs6 expected:$vs6_expected"
+}
+if [expr $check_vs7 != $vs7_expected ] {
+    fail "unexpected value vs7;   actual:$check_vs7 expected:$vs7_expected"
+}
+
+gdb_test "info break"
+gdb_test "info register vs4 vs5 vs6 vs7 "
+gdb_test "disas main #2"
+
diff --git a/gdb/testsuite/gdb.arch/powerpc-plxv.s b/gdb/testsuite/gdb.arch/powerpc-plxv.s
new file mode 100644
index 00000000000..0ca6d4775c2
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/powerpc-plxv.s
@@ -0,0 +1,47 @@
+/* This testcase is part of GDB, the GNU debugger.
+
+   Copyright 2021 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>. */
+
+
+# Test to verify that the prefixed instructions that load/store
+# data off of a PC-Relative value behave properly when a
+# breakpoint is set on the instruction and the instruction
+# is executed from a displaced location.
+
+.global main
+.type main,function
+main:
+	nop
+	plxv 4,40(0),1
+	plxv 5,40(0),1
+	plxv 6,40(0),1
+	plxv 7,40(0),1
+check_here:
+	blr
+mydata:
+	.long 0xa1b1c1d1	# <<-
+	.long 0xa2b2c2d2	# <<- loaded into vs4
+	.long 0xa3b3c3d3	# <<- loaded into vs4
+	.long 0xa4b4c4d4	# <<- loaded into vs4, vs5
+	.long 0xa5b5c5d5	# <<- loaded into vs4, vs5
+	.long 0xa6b6c6d6	# <<- loaded into      vs5, vs6
+	.long 0xa7b7c7d7	# <<- loaded into      vs5, vs6
+	.long 0xa8b8c8d8	# <<- loaded into           vs6, vs7
+	.long 0xa9b9c9d9	# <<- loaded into           vs6, vs7
+	.long 0xaabacada	# <<- loaded into                vs7
+	.long 0xabbbcbdb	# <<- loaded into                vs7
+	.long 0xacbcccdc	# <<-
+


      parent reply	other threads:[~2021-03-29 22:44 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-27  0:25 [PATCH,rs6000] " will schmidt
2021-03-27 14:27 ` Andrew Burgess
2021-03-29 15:09   ` will schmidt
2021-03-29 22:43 ` will schmidt [this message]

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