From: Andrew Burgess <andrew.burgess@embecosm.com>
To: binutils@sourceware.org, gdb-patches@sourceware.org
Subject: [PATCH 7/8] gdb/riscv: make riscv target description names global
Date: Wed, 2 Dec 2020 17:39:31 +0000 [thread overview]
Message-ID: <a9b71a18114f8c1c178a5cb8836f54de2f1e3787.1606930261.git.andrew.burgess@embecosm.com> (raw)
In-Reply-To: <cover.1606930261.git.andrew.burgess@embecosm.com>
A later commit will need the names of the RISC-V target description
features in files other than riscv-tdep.c. This commit just makes the
names global strings that can be accessed from other riscv-*.c files.
There should be no user visible changes after this commit.
gdb/ChangeLog:
* riscv-tdep.c (riscv_feature_name_csr): Define.
(riscv_feature_name_cpu): Define.
(riscv_feature_name_fpu): Define.
(riscv_feature_name_virtual): Define.
(riscv_xreg_feature): Use riscv_feature_name_cpu.
(riscv_freg_feature): Use riscv_feature_name_fpu.
(riscv_virtual_feature): Use riscv_feature_name_virtual.
(riscv_csr_feature): Use riscv_feature_name_csr.
* riscv-tdep.h (riscv_feature_name_csr): Declare.
---
gdb/ChangeLog | 12 ++++++++++++
gdb/riscv-tdep.c | 14 ++++++++++----
gdb/riscv-tdep.h | 3 +++
3 files changed, 25 insertions(+), 4 deletions(-)
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index a428f79940d..eb2ccb42d5e 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -74,6 +74,12 @@ static inline bool is_ ## INSN_NAME ## _insn (long insn) \
#include "opcode/riscv-opc.h"
#undef DECLARE_INSN
+/* The names of the RISC-V target description features. */
+const char *riscv_feature_name_csr = "org.gnu.gdb.riscv.csr";
+static const char *riscv_feature_name_cpu = "org.gnu.gdb.riscv.cpu";
+static const char *riscv_feature_name_fpu = "org.gnu.gdb.riscv.fpu";
+static const char *riscv_feature_name_virtual = "org.gnu.gdb.riscv.virtual";
+
/* Cached information about a frame. */
struct riscv_unwind_cache
@@ -252,7 +258,7 @@ riscv_register_feature::register_info::check
static const struct riscv_register_feature riscv_xreg_feature =
{
- "org.gnu.gdb.riscv.cpu", true,
+ riscv_feature_name_cpu, true,
{
{ RISCV_ZERO_REGNUM + 0, { "zero", "x0" }, RISCV_REG_REQUIRED },
{ RISCV_ZERO_REGNUM + 1, { "ra", "x1" }, RISCV_REG_REQUIRED },
@@ -294,7 +300,7 @@ static const struct riscv_register_feature riscv_xreg_feature =
static const struct riscv_register_feature riscv_freg_feature =
{
- "org.gnu.gdb.riscv.fpu", true,
+ riscv_feature_name_fpu, true,
{
{ RISCV_FIRST_FP_REGNUM + 0, { "ft0", "f0" }, RISCV_REG_REQUIRED },
{ RISCV_FIRST_FP_REGNUM + 1, { "ft1", "f1" }, RISCV_REG_REQUIRED },
@@ -344,7 +350,7 @@ static const struct riscv_register_feature riscv_freg_feature =
static const struct riscv_register_feature riscv_virtual_feature =
{
- "org.gnu.gdb.riscv.virtual", false,
+ riscv_feature_name_virtual, false,
{
{ RISCV_PRIV_REGNUM, { "priv" }, RISCV_REG_OPTIONAL }
}
@@ -356,7 +362,7 @@ static const struct riscv_register_feature riscv_virtual_feature =
static struct riscv_register_feature riscv_csr_feature =
{
- "org.gnu.gdb.riscv.csr", false,
+ riscv_feature_name_csr, false,
{
#define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER) \
{ RISCV_ ## VALUE ## _REGNUM, { # NAME }, RISCV_REG_OPTIONAL },
diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h
index 1064ced1192..fc8013cf417 100644
--- a/gdb/riscv-tdep.h
+++ b/gdb/riscv-tdep.h
@@ -155,4 +155,7 @@ extern void riscv_supply_regset (const struct regset *regset,
struct regcache *regcache, int regnum,
const void *regs, size_t len);
+/* The names of the RISC-V target description features. */
+extern const char *riscv_feature_name_csr;
+
#endif /* RISCV_TDEP_H */
--
2.25.4
next prev parent reply other threads:[~2020-12-02 17:39 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-02 17:39 [PATCH 0/8] Bare-metal core dumps for RISC-V Andrew Burgess
2020-12-02 17:39 ` [PATCH 1/8] gdb/riscv: use a single regset supply function for riscv fbsd & linux Andrew Burgess
2021-01-18 14:15 ` Andrew Burgess
2020-12-02 17:39 ` [PATCH 2/8] bfd/binutils: support for gdb target descriptions in the core file Andrew Burgess
2020-12-02 18:21 ` Luis Machado
2020-12-02 22:58 ` Jim Wilson
2020-12-03 12:16 ` Luis Machado
[not found] ` <20201214115512.GI2945@embecosm.com>
2021-01-11 10:19 ` Andrew Burgess
2021-01-11 13:03 ` Luis Machado
2020-12-07 12:48 ` Andrew Burgess
2020-12-02 17:39 ` [PATCH 3/8] gdb: write target description into " Andrew Burgess
2020-12-03 20:36 ` Tom Tromey
2020-12-07 14:38 ` Andrew Burgess
2020-12-02 17:39 ` [PATCH 4/8] bfd/riscv: prepare to handle bare metal core dump creation Andrew Burgess
2020-12-02 23:24 ` Jim Wilson
2020-12-07 14:39 ` Andrew Burgess
2020-12-02 17:39 ` [PATCH 5/8] gdb/riscv: introduce bare metal core dump support Andrew Burgess
2020-12-02 18:12 ` Luis Machado
2020-12-07 15:17 ` Andrew Burgess
2020-12-07 15:58 ` Luis Machado
2020-12-07 16:58 ` Andrew Burgess
2020-12-07 17:24 ` Luis Machado
2020-12-07 18:11 ` Andrew Burgess
2020-12-07 19:00 ` Luis Machado
2020-12-07 19:23 ` Andrew Burgess
2020-12-07 19:39 ` Luis Machado
2020-12-07 19:51 ` Paul Mathieu
2020-12-13 10:13 ` Fredrik Hederstierna
2020-12-02 17:39 ` [PATCH 6/8] bfd/binutils: add support for RISC-V CSRs in core files Andrew Burgess
2020-12-02 23:50 ` Jim Wilson
2020-12-07 15:19 ` Andrew Burgess
2020-12-14 13:37 ` Andrew Burgess
2020-12-02 17:39 ` Andrew Burgess [this message]
2020-12-02 17:39 ` [PATCH 8/8] gdb/riscv: write CSRs into baremetal core dumps Andrew Burgess
2020-12-02 23:59 ` [PATCH 0/8] Bare-metal core dumps for RISC-V Jim Wilson
2020-12-07 12:10 ` Andrew Burgess
2020-12-07 19:57 ` Jim Wilson
2020-12-03 20:40 ` Tom Tromey
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