From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR03-AM7-obe.outbound.protection.outlook.com (mail-am7eur03on2080.outbound.protection.outlook.com [40.107.105.80]) by sourceware.org (Postfix) with ESMTPS id 432E838AA241 for ; Thu, 6 Oct 2022 13:02:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 432E838AA241 ARC-Seal: i=2; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=pass; b=UjWvZm0D9K6+1A3oJzZ8GKMAT6UV8SSUAsLWVxbeIg2F3bEnYGVP+vx6BtRxjNJOD3h5R4QRoH9TpyIrUwY9KSOER5GymC5S7LcNoVmi2FizuRMjQuHX0IhmLR3KWCgWRWpQNwwjAZD9KelUhKHeygH1w1Oorvd0+MNRbnbDwGee/OiQH10TKrj5tn/BFhXKr8JBs9hU4UbPugZHEzYShu/DV4YB9CMwf2mXQq1skQQ9A5H10DFCI1B/npw2s/3pp5AlMn43pi6uzSeRFhzp3zYp5MIPg3AW446Aq4in3ktHvvFLQNbb3bbNpoLw6D929gw6D7kfj/aoHvBqhIM2Dg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=1Fp8bCXvUSOZxMkjvmA3CsF/Ai8M+SGYzEbQHf0sc/k=; b=X4AZnDCEi3asiyJQYxTz0rNAb7Pi87X3sunBP4o2Vj44jpIIsnCgboMNT/QCc45o2JLcAgOv8ihoaRA1e92VTV45qXCRpqXRKYeCsokPUNf70bMXkp/2qT+RRJf1f4pcM3iwkUpvm59GZk5wKuMPTW22hkoM+XndkwjGSxhLfSynQVjCpKDK/tfk48vbPtM1POx0xtjb8GeWV2PAb/uEW7zMTlZcXl5+B38Q4tqTzlmFl0csTEZX7czHuyS13mLYyJ8S9vdj/3VRKbJ9uqGq3zsXMdN5Lvx7gjG2JFVu8dMd7MSHNQ+9p65AntAUdlcrzNUkPC3gtAZQ+7A11yAnJw== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 63.35.35.123) smtp.rcpttodomain=sourceware.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dkim=[1,1,header.d=arm.com] dmarc=[1,1,header.from=arm.com]) Received: from AM6PR02CA0036.eurprd02.prod.outlook.com (2603:10a6:20b:6e::49) by DB8PR08MB5388.eurprd08.prod.outlook.com (2603:10a6:10:11c::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.24; Thu, 6 Oct 2022 13:02:20 +0000 Received: from VE1EUR03FT018.eop-EUR03.prod.protection.outlook.com (2603:10a6:20b:6e:cafe::15) by AM6PR02CA0036.outlook.office365.com (2603:10a6:20b:6e::49) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.32 via Frontend Transport; Thu, 6 Oct 2022 13:02:20 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by VE1EUR03FT018.mail.protection.outlook.com (10.152.18.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5709.10 via Frontend Transport; Thu, 6 Oct 2022 13:02:20 +0000 Received: ("Tessian outbound 99ee3885c6d5:v128"); Thu, 06 Oct 2022 13:02:19 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 04b5fc1448ed0331 X-CR-MTA-TID: 64aa7808 Received: from 0c61a94b0716.3 by 64aa7808-outbound-1.mta.getcheckrecipient.com id CA15ECCB-AAD4-4182-9528-0CDE270D18B7.1; Thu, 06 Oct 2022 13:02:08 +0000 Received: from EUR01-VE1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id 0c61a94b0716.3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Thu, 06 Oct 2022 13:02:08 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Y5as/IZ3pz02JaobZtfnAs20ci/TSG0rjOZySXYIMvcKvJkMwxnxAGn5XQjzUhLSWEC28mwlmKLBW05IxdsPEHatpUrJ+57+49MAER9+PP22jKjaK8YqvrqL6Vn3enP6EQurEN6JPmr+A/zeaSain7NbfDUiPM5q2AptVF6b++DnpnDNnI8TFuUafH081yt0yvEc1bxYKOq8a+iNryeG3pKB3Lws498V9iisSIXWeuSge2d+X8Z/nHodysgKPVnTXqvg6V/Aei9x1vHGC0+we5WewfpApHlxusVAcQh/6Jt/VfwUpYuC4vYfaO9WM3A3uBrryVZlmOS3mU/Dwu0/Hg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=1Fp8bCXvUSOZxMkjvmA3CsF/Ai8M+SGYzEbQHf0sc/k=; b=IaWYC//0ozZnwn4J41EMg+Ps6EB6ttLQTPq/vVERECR4a5+bEvCj6wmF7zTlgqL/cZ7LqGPRDXjP5Pkl4OcJZCNq+QG6+nu1sIFH5vz8UxK2zWp3MY5HCT++ePDr3BwcZimvIWZl4ex5+g8uJC3+oas6ODVn24V66F/Hprr1XAFtEKhcg2hKE0q8llVnzC3k78g681Xb2lkPY+1NaSBsjN9WCyqOw1gZuBPtpHOoVrUl0TRNVHj3etXR75fOSu49ggsFYqlXvNC2lVJLMhOncD9VhKMcMEOvQyGyKifz4q5k2y2nLxwk7a56hTEI6KqhiLKFO32Y/HqKqEYTONsYGA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Received: from AM6PR08MB3911.eurprd08.prod.outlook.com (2603:10a6:20b:80::27) by PAVPR08MB9137.eurprd08.prod.outlook.com (2603:10a6:102:30e::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.24; Thu, 6 Oct 2022 13:02:05 +0000 Received: from AM6PR08MB3911.eurprd08.prod.outlook.com ([fe80::6df4:ba3e:1ac3:734]) by AM6PR08MB3911.eurprd08.prod.outlook.com ([fe80::6df4:ba3e:1ac3:734%4]) with mapi id 15.20.5676.034; Thu, 6 Oct 2022 13:02:05 +0000 Message-ID: Date: Thu, 6 Oct 2022 14:02:04 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH] [Arm] Remove dead FPA code Content-Language: en-US To: Richard Earnshaw , John Baldwin , Pedro Alves , gdb-patches@sourceware.org, David Spickett References: <20220920123012.189293-1-luis.machado@arm.com> <73479562-ab47-dfbf-aadc-7a2203c0f0e4@FreeBSD.org> <56653c70-593a-4b8d-ddf7-52f7dd0608f7@arm.com> <1946bc74-8270-23c4-9483-702b9dbc03de@FreeBSD.org> <3cb2d818-83e8-4e2d-5e1b-9b555d1a2217@arm.com> From: Luis Machado In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: LO4P265CA0092.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:2bc::13) To AM6PR08MB3911.eurprd08.prod.outlook.com (2603:10a6:20b:80::27) MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: AM6PR08MB3911:EE_|PAVPR08MB9137:EE_|VE1EUR03FT018:EE_|DB8PR08MB5388:EE_ X-MS-Office365-Filtering-Correlation-Id: d5b8efea-3dd5-483f-80d3-08daa79b00ce x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: shH/5Sna1+F6fYn28pY3b9GrMB6TfTqKk3B/3OdtqwJ+wJpZR6/Z7mmxpDMP0aJpGXitUT7q4CuE+53Yu0gElayXmgLzVcnVEcJSJULIrzkfu6Fcs2EmQQJOTrNpf9U/e9T3B71AoYhaKhkx0SG//fU7qbdE82R1l/SKAuvxx0s9vySLwR3ArVU3jBHSrqT0n6N77w4S2sN+w2SWJbfWvX7hE0cTHRfLHXhrnGoUhb9jIv/on7oDPOaJKuYp87EGzNlc0CEnup79iYut7S+khiqrR7steVQJY9zSr3dgIqTRRVTNVRVrv/x7r1h4qcb+SKG1/2HKETSQxgSMzuxqUwC97TbRJzXTlBmn2VKshjkdE38N4DCmKsNaUdLuu74VfUshBq2cRBbcL/8k7xbHkSzDvr9bYDVD3jVt2p0Z8HV+NEwR3Fu8/ank5/ZSCZNR7LmC3JpyDAQSYUcepTIOQhuJznkuBsJ6JACEvtIrFCqbs1GpOv48hPPH73BfooQyuLRfKkzFhINX+46rHyuKGEAM+1l1MD2+rfcbs2TzRy6Bk5jk3KC5GFIjPCVx2OUDVzONpUmmKjYJa2WkCInINYx40Mdi93UI7INiOrkeN1fFWwvxm4bUTZRh3r0A1EBu0YzcYrBmNI4jGtzWqcUtnuJ7yoR5smVNWkRpqCGvfChEO8+Z0dGhGm7RVHy58TjrkEQk5TDidIkHuvtyssALmb4cHSrawA3XRgKASffh8jnXN/lmLrnOPpRHYpIvv9rcncMwQ7TZDkZOehcs5HDtA7NlY1g0MAq9oXJu70XKuOQsEGwZJF0AL7lYHZczMztPmV+k62+N37hhxq59JuZjr5a0cCk4IoHy4HRw6+mHGPI= X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM6PR08MB3911.eurprd08.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230022)(4636009)(396003)(136003)(39860400002)(376002)(366004)(346002)(451199015)(31686004)(66899015)(5660300002)(41300700001)(2906002)(44832011)(6506007)(8936002)(8676002)(2616005)(36756003)(66946007)(478600001)(86362001)(38100700002)(966005)(6486002)(26005)(66476007)(31696002)(110136005)(6636002)(53546011)(66556008)(6512007)(316002)(186003)(83380400001)(45980500001)(43740500002); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAVPR08MB9137 Original-Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: VE1EUR03FT018.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 2eb26e59-1b14-46c0-c774-08daa79af7ea X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: JfQF45tJPjhxe1gwc0HOHXIT2UB24wQSSWBP8RlIFwd7KRFvgOZPLaMOma6bvgNk7bvrjt5eh7e/67CMrLt5+I2D77ocXlGYa56TmFoMLq6zDa6uUfP957QnJU43keC6xlRvggl+OkczN4UA2iDP5HqBO9YkhXTSSrnU+xTVuE2GdQxOWZ6HRM5OxYQ8CmkEjgIKNPmVJ6Wyt4uDhcI8rqxb1tJmqdQJ/z4f9knEEYPzIl9yWJdkW6vzZ+apDzMKxiFIYmPKjXqlOrn9UyXrFkznBhHrZja3SNPS2ZVaipBJptvjgYIRvgeF10jgWtEFLkCYovqpPg18NRG/amBHIRt4E8elIr6gBiEi61MV/UwWlYoSabMDbV/oPteYPWPDi9JP38ecsz+RpGTUaIuqSIXA2DW7/fjdbFk2Tpg5GNVdINS7u3VcL5kQZnKw5CFXgUSUkIFgHFmb/mgVZvJYCnlmKKbNY772nN6PmYhqHhgNWvZIdRU9f2340vsxyVCC5pH9HqPrDOAGKgOs4cle9L9Rk5s4AgedGl5oAjNKrS3L0TeOjIkiqTaTzsFzydh12vFbypA6lbeKm8FD9c8TZ0UxLAdMSdE6sq8FWmxAApfpUgctUpimgZTVyYoUVi91QgjQ5jzEfo18nKOpoiVgwGa0a6/1hDxzMvjRmha4YCoj4k/jXacKVNVn5oldhDLEFEK8MecPxLG/MAoDIkiODZCgE7sYETN1QTT8J0sfJJFSi+j46SZ6wazeX4MCKihJWF2VImtHR2007OYa153tjrXe6qM4mSn+hFvSQ8lwqJn0R1UrmnTfRd/JGbt7lOvizZ5q72bPjcug2P9k0C1Zg1PVyWTDXJOvB9IbbGBi9oF3H5ODIVLDLTNlVs9qKRvs X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230022)(4636009)(39860400002)(136003)(346002)(376002)(396003)(451199015)(40470700004)(36840700001)(46966006)(36860700001)(70586007)(186003)(8676002)(47076005)(53546011)(26005)(110136005)(2616005)(316002)(336012)(5660300002)(2906002)(356005)(70206006)(8936002)(41300700001)(81166007)(82740400003)(44832011)(40460700003)(6636002)(31696002)(86362001)(40480700001)(83380400001)(6512007)(6506007)(966005)(6486002)(82310400005)(478600001)(31686004)(36756003)(66899015)(43740500002); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Oct 2022 13:02:20.0086 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d5b8efea-3dd5-483f-80d3-08daa79b00ce X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT018.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB8PR08MB5388 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, BODY_8BITS, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, NICE_REPLY_A, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 06 Oct 2022 13:02:34 -0000 On 10/5/22 17:57, Richard Earnshaw wrote: > > > On 05/10/2022 17:48, John Baldwin wrote: >> On 10/5/22 1:26 AM, Luis Machado wrote: >>> On 10/4/22 22:36, John Baldwin wrote: >>>> On 10/4/22 10:43 AM, Luis Machado wrote: >>>>> On 10/4/22 18:08, John Baldwin wrote: >>>>>> On 10/4/22 1:43 AM, Luis Machado via Gdb-patches wrote: >>>>>>> On 10/3/22 20:16, Pedro Alves wrote: >>>>>>>> On 2022-09-20 1:30 p.m., Luis Machado via Gdb-patches wrote: >>>>>>>> >>>>>>>>> diff --git a/gdb/arch/arm.h b/gdb/arch/arm.h >>>>>>>>> index 36757493406..74a6ba93bc7 100644 >>>>>>>>> --- a/gdb/arch/arm.h >>>>>>>>> +++ b/gdb/arch/arm.h >>>>>>>>> @@ -44,11 +44,6 @@ enum gdb_regnum { >>>>>>>>>        ARM_SP_REGNUM = 13,        /* Contains address of top of stack */ >>>>>>>>>        ARM_LR_REGNUM = 14,        /* address to return to from a function call */ >>>>>>>>>        ARM_PC_REGNUM = 15,        /* Contains program counter */ >>>>>>>>> -  /* F0..F7 are the fp registers for the (obsolete) FPA architecture.  */ >>>>>>>> >>>>>>>> Shouldn't we leave behind a comment explaining why there's a hole between 15 and 25? >>>>>>> >>>>>>> I pondered about this a bit more, and I think we should close the gap and bring CPSR down to >>>>>>> 16, its "natural" position. It is what linux uses for user_regs as well, in gdb/arch/arm-linux.h: >>>>>>> >>>>>>> /* The index to access CSPR in user_regs defined in GLIBC.  */ >>>>>>> #define ARM_CPSR_GREGNUM 16 >>>>>>> >>>>>>>> >>>>>>>> IIRC the numbers can't be changed since we need to handle the case when the target >>>>>>>> doesn't send an xml tdesc, so it'd be good to help future readers understand why >>>>>>>> there's a hole. >>>>>>> >>>>>>> That's correct. Though a 32-bit Arm target that doesn't support XML descriptions these days is not very >>>>>>> common. I haven't seen one in a while. >>>>>>> >>>>>>> I'm willing to declare old 32-bit Arm targets that don't send XML target descriptions back as unsupported. >>>>>>> >>>>>>> To that effect, I suppose we should add a note to make it more explicit. >>>>>>> >>>>>>> More below. >>>>>> >>>>>> FWIW, the GDB stub in FreeBSD's kernel does not use XML target descriptions >>>>>> for any architectures, but it also only tends to do GPRs and not any floating >>>>>> point.  For 32-bit ARM it does not report any register values higher than >>>>>> number 15 (PC), so it would not be affected by changing this. >>>>> >>>>> Does it care about CPSR and/or XPSR? Could you please give it a try to see if the defaults would suit it just fine? >>>> >>>> Hmm, I misread and it does care about CPSR for the current thread.  The >>>> relevant code is here (From https://cgit.freebsd.org/src/tree/sys/arm/arm/gdb_machdep.c): >>>> >>>> void * >>>> gdb_cpu_getreg(int regnum, size_t *regsz) >>>> { >>>> >>>>       *regsz = gdb_cpu_regsz(regnum); >>>> >>>>       if (kdb_thread == curthread) { >>>>           if (regnum < 13) >>>>               return (&kdb_frame->tf_r0 + regnum); >>>>           if (regnum == 13) >>>>               return (&kdb_frame->tf_svc_sp); >>>>           if (regnum == 14) >>>>               return (&kdb_frame->tf_svc_lr); >>>>           if (regnum == 15) >>>>               return (&kdb_frame->tf_pc); >>>>           if (regnum == 25) >>>>               return (&kdb_frame->tf_spsr); >>>>       } >>>> >>>>       switch (regnum) { >>>>       case 4:  return (&kdb_thrctx->pcb_regs.sf_r4); >>>>       case 5:  return (&kdb_thrctx->pcb_regs.sf_r5); >>>>       case 6:  return (&kdb_thrctx->pcb_regs.sf_r6); >>>>       case 7:  return (&kdb_thrctx->pcb_regs.sf_r7); >>>>       case 8:  return (&kdb_thrctx->pcb_regs.sf_r8); >>>>       case 9:  return (&kdb_thrctx->pcb_regs.sf_r9); >>>>       case 10:  return (&kdb_thrctx->pcb_regs.sf_r10); >>>>       case 11:  return (&kdb_thrctx->pcb_regs.sf_r11); >>>>       case 12:  return (&kdb_thrctx->pcb_regs.sf_r12); >>>>       case 13:  stacktest = kdb_thrctx->pcb_regs.sf_sp + 5 * 4; >>>>             return (&stacktest); >>>>       case 15: >>>>             /* >>>>              * On context switch, the PC is not put in the PCB, but >>>>              * we can retrieve it from the stack. >>>>              */ >>>>             if (kdb_thrctx->pcb_regs.sf_sp > KERNBASE) { >>>>                 kdb_thrctx->pcb_regs.sf_pc = *(register_t *) >>>>                     (kdb_thrctx->pcb_regs.sf_sp + 4 * 4); >>>>                 return (&kdb_thrctx->pcb_regs.sf_pc); >>>>             } >>>>       } >>>> >>>>       return (NULL); >>>> } >>>> >>>> The 'kdb_thread == curthread' case is when a thread enters the debugger due >>>> to a crash or breakpoint, etc.  We do return CPSR for that thread, but we do >>>> not return it for other threads.  It looks like we do also know the FPA register >>>> size so that we return enough "xx" bytes in the 'g' reply to mark the FP >>>> registers as unavailable so that we can return the value of CPSR in the 'g' >>>> reply. >>>> >>>>   From https://cgit.freebsd.org/src/tree/sys/arm/include/gdb_machdep.h: >>>> >>>> #define    GDB_NREGS    26 >>>> #define    GDB_REG_SP    13 >>>> #define    GDB_REG_LR    14 >>>> #define    GDB_REG_PC    15 >>>> >>>> static __inline size_t >>>> gdb_cpu_regsz(int regnum) >>>> { >>>>       /* >>>>        * GDB expects the FPA registers f0-f7, each 96 bits wide, to be placed >>>>        * in between the PC and CSPR in response to a "g" packet. >>>>        */ >>>>       return (regnum >= 16 && regnum <= 23 ? 12 : sizeof(int)); >>>> } >>>> >>>> NetBSD's kernel seems to have similar knowledge: >>>> >>>> http://cvsweb.netbsd.org/bsdweb.cgi/src/sys/arch/arm/include/db_machdep.h?rev=1.28&content-type=text/x-cvsweb-markup&only_with_tag=MAIN >>>> >>>> (The kgdb bits near the bottom) >>>> >>>> Linux's kernel also seems to maybe hardcode this knowledge as well: >>>> >>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/kernel/kgdb.c#n21 >>>> >>> >>> Yeah, that's what I was worried about. Register discoveries without XML are not great, and more recently debugging stubs have been >>> exposing more system registers. Having to consider FPA (which was *removed* 10 years ago from GCC, but fell in disuse before then) is not >>> acceptable at this point. >>> >>> If those debugging stubs want to skip XML, I think it would be reasonable for them to at least update the expected 'g' packet to contain just >>> the basic registers, with CPSR as 16. >>> >>> That might need some coordination. I can coordinate this from the Linux Kernel's side, but I never dealt with the BSD kernels. >> >> I can certainly deal with updating FreeBSD.  I can try to find someone over in NetBSD >> land.  Honestly, the simplest approach might be to start exporting XML from the >> kernel.  However, an even simpler workaround for now might be having a knob that >> can be set for older debugger binaries that still places CPSR at the old register >> number vs the newer one. >> > > IMO, exporting an XML description of the register set(s) available is certainly the right way forward.  In fact, I'd strongly suggest we leave the existing packet formats as-is for now and add support for XML to the relevant kernels.  At some point then gdb (and LLDB) can simply stop working with older kernel versions that don't do it the 'right' way. > > R. FTR, I started a thread here for the Linux kernel: https://lore.kernel.org/linux-arm-kernel/5b0d81f2-00ed-cf3c-8869-420326595e0a@arm.com/T/#u I did a bit of background research on the register layout, and it seems to have been put together around late 1992, including the fp registers. When GDB switched to XML descriptions, the same format was kept. Eventually other debugging stubs copied whatever GDB was doing, even if the fp registers were no longer being used. The Linux kgdb states this in one comment: /* * From Kevin Hilman: * * gdb is expecting the following registers layout. * * r0-r15: 1 long word each * f0-f7: unused, 3 long words each !! * fps: unused, 1 long word * cpsr: 1 long word * * Even though f0-f7 and fps are not used, they need to be * present in the registers sent for correct processing in * the host-side gdb. * * In particular, it is crucial that CPSR is in the right place, * otherwise gdb will not be able to correctly interpret stepping over * conditional branches. */ Keeping the compatibility code for now, maybe with a nice warning stating this is deprecated, is the easiest IMO. It should give kgdb's some time to adapt. The switch would allow us to remove the g guess code now, but it would be slightly more annoying for people to use it if they want the non-default case. But still a possibility.