From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 15359 invoked by alias); 30 Dec 2014 12:11:11 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 15315 invoked by uid 89); 30 Dec 2014 12:11:05 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.0 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 X-HELO: relay1.mentorg.com Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 30 Dec 2014 12:11:02 +0000 Received: from nat-ies.mentorg.com ([192.94.31.2] helo=SVR-IES-FEM-01.mgc.mentorg.com) by relay1.mentorg.com with esmtp id 1Y5vda-0003wT-UW from Maciej_Rozycki@mentor.com ; Tue, 30 Dec 2014 04:10:59 -0800 Received: from localhost (137.202.0.76) by SVR-IES-FEM-01.mgc.mentorg.com (137.202.0.104) with Microsoft SMTP Server (TLS) id 14.3.224.2; Tue, 30 Dec 2014 12:10:57 +0000 Date: Tue, 30 Dec 2014 12:11:00 -0000 From: "Maciej W. Rozycki" To: Pedro Alves CC: Yao Qi , Subject: Re: [PATCH] MIPS: Handle the DSP registers for bare metal In-Reply-To: <54A27A7E.4070200@redhat.com> Message-ID: References: <1418909149-29929-1-git-send-email-yao@codesourcery.com> <54930ED2.1080806@redhat.com> <87r3vwqooq.fsf@codesourcery.com> <5494098B.7080002@redhat.com> <54A27A7E.4070200@redhat.com> User-Agent: Alpine 1.10 (DEB 962 2008-03-14) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" X-SW-Source: 2014-12/txt/msg00679.txt.bz2 On Tue, 30 Dec 2014, Pedro Alves wrote: > > I'm not sure offhand whether the piece of patch proposed you refer to > > here is correct or not, but the overall scope of this and the other patch > > Yao has mentioned yet outstanding is support for legacy bare-metal RSP > > stubs that have no notion of target descriptions and may even predate > > GDB's support for these descriptions, and yet they want to make all > > processor registers available for inspection and modification by GDB. > > This code comes from MIPS UK and dates back to early 2000s and I think it > > would be good having it upstream so that standard GDB can talk to these > > stubs. The fixed layout of the g/G packet and corresponding p/P packet > > offsets have been set by the bare-metal SDE toolchain years ago. > > The way to handle that is still through target descriptions -- if a > target doesn't send a target description, GDB maps known layouts to built-in > target descriptions. See mips_register_g_packet_guesses. Register probing Yao mentioned is still needed, because in this fixed packet format the whole set of architecturally defined register slots is exchanged with the RSP stub, e.g. 8 * 32 = 256 CP0 registers, 8 * 32 = 256 CP2 registers, etc. (as documented by the change to mips-tdep.h proposed), even if some are not present, e.g. not all CP0 register slots have already been allocated in the architecture so far and the vast majority of them is optional. The information on which registers are present and which are not will not be supplied by the target and has to be determined by gradual discovery, that is poking at registers as they are determined to be present, i.e. first CP0.PRId that is always there, then CP0.Config0 if present, then CP0.Config1 if present, and so on. Gaps will be present in the packets exchanged for the absent registers as with the ACX registers discussed previously. And if we were to define built-in target descriptions for the possible variants of present register sets, then, as noted by Yao, we hit the issue of having to make some 2^50 templates (slightly fewer actually, as there are some dependencies between the presence of some registers, e.g. you can't have a processor that has a CP0.Config2 register, but does not have CP0.Config1, the reverse is allowed; similarly a CPU can't have the ACX register when it does not have CP0.Config3) which is of course beyond technical capabilities as e.g. a 32-bit host will have fewer bytes of addressable memory even. So some other way has to be invented if you think the current working solution is not good enough for some reason. NB `mips_register_g_packet_guesses' is not necessarily relevant here as there may be registers accessible through the stub via the p/P packets only and not included in the g/G packet layout for performance reasons (the packet may be shorter than the maximum defined) as to transfer all the registers through a JTAG link every time the target is stopped may be exceedingly slow, especially when single-stepping. Maciej