From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp.polymtl.ca (smtp.polymtl.ca [132.207.4.11]) by sourceware.org (Postfix) with ESMTPS id 6750C3858C60 for ; Fri, 8 Sep 2023 16:02:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6750C3858C60 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=polymtl.ca Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=polymtl.ca Received: from simark.ca (simark.ca [158.69.221.121]) (authenticated bits=0) by smtp.polymtl.ca (8.14.7/8.14.7) with ESMTP id 388G2WRx006918 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 8 Sep 2023 12:02:37 -0400 DKIM-Filter: OpenDKIM Filter v2.11.0 smtp.polymtl.ca 388G2WRx006918 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=polymtl.ca; s=default; t=1694188957; bh=HiBGRDRhJ2CAZ5MPiUwm02Q/tH1TEKz9+seICdBOKR4=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=oX7D3Rlc3Cynk4eCcE3B5oXRMtqyBE9NjsLiIGGhIjbBNr3MwsBYx3Ql4stKf8AZ2 F1gPFk19BACh/LkeeD4H/2eExdSPFD7lCm18zINc01iBeup+/pDTIcfhq+BftfbR6a GV+bUvX3At8yMWW3jN8kvwyRndeFLpdJNRMVwbnY= Received: from [172.16.0.192] (192-222-143-198.qc.cable.ebox.net [192.222.143.198]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPSA id 5C5431E092; Fri, 8 Sep 2023 12:02:32 -0400 (EDT) Message-ID: Date: Fri, 8 Sep 2023 12:02:31 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 12/16] [gdb/generic] corefile/bug: Use thread-specific gdbarch when dumping register state to core files Content-Language: fr To: Luis Machado , gdb-patches@sourceware.org Cc: thiago.bauermann@linaro.org References: <20230907152018.1031257-1-luis.machado@arm.com> <20230907152018.1031257-13-luis.machado@arm.com> <971a9e69-a802-7354-728e-573d4c85c3f9@arm.com> <680b67cc-4330-4425-9860-02666f7d0e0b@polymtl.ca> From: Simon Marchi In-Reply-To: <680b67cc-4330-4425-9860-02666f7d0e0b@polymtl.ca> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Poly-FromMTA: (simark.ca [158.69.221.121]) at Fri, 8 Sep 2023 16:02:33 +0000 X-Spam-Status: No, score=-3031.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: > Please remind me, does an AArch64 core file contain one target > description per thread, to account for the fact that different threads > could have different register layouts? Or right now we just hope that > all threads use the same target description (which might be different > from what the inferior started with)? I think that the commit message on the following patch answers my question: there isn't a full target desc for each thread, but using the process-wide target desc plus by reading some bits from the SVE (and eventually SME) state, you can derive on target desc per thread. That sounds right? Simon