Re: [PATCH v3] gdb/arm: Handle lazy FPU register stacking

[Torbjorn SVENSSON <torbjorn.svensson@foss.st.com>]

Hello,

On 2022-09-27 22:08, Thiago Jung Bauermann wrote:
> 
> Hello,
> 
> Torbjörn SVENSSON via Gdb-patches <gdb-patches@sourceware.org> writes:
> 
>> diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
>> index 2810232fcb8..43ce1a45782 100644
>> --- a/gdb/arm-tdep.c
>> +++ b/gdb/arm-tdep.c
>> @@ -68,6 +68,7 @@
>>   #endif
>>   
>>   static bool arm_debug;
>> +static bool force_fpu_regs_from_stack = false;
> 
> I'm a bit concerned about having a global variable to indicate what is
> (IIUC) a per-CPU state. Does this logic work with multi-processor
> inferiors?
> 
> Instead of using a global variable, can arm_m_exception_cache use
> “this_frame->level > 0” to decide whether to get the FPU registers from
> the stack?
> 

I share your concern, but haven't found any better way to achieve the 
required condition.

The content of FPCCR shall only be considered for the first extended 
exception frame on the stack. As there are likely other kinds of frames 
on the stack, the level would not be enough to decide if stack or 
registers should be used.

Do you know a way that this state can be saved per inferior?

On the other hand, I got the impression that the cache is purged when 
the inferior is switched, but this assumption might be wrong.

I've only verified the function with a simple single inferior.

Kind regards,
Torbjörn