From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by sourceware.org (Postfix) with ESMTPS id 340143857BBE for ; Tue, 27 Sep 2022 20:27:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 340143857BBE Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 28RFGsba003654; Tue, 27 Sep 2022 22:27:48 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3jsqamc535-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 27 Sep 2022 22:27:48 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 5379E100034; Tue, 27 Sep 2022 22:27:47 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 4AEEF208901; Tue, 27 Sep 2022 22:27:47 +0200 (CEST) Received: from [10.252.30.137] (10.75.127.123) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2375.31; Tue, 27 Sep 2022 22:27:44 +0200 Message-ID: Date: Tue, 27 Sep 2022 22:27:43 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.3.0 Subject: Re: [PATCH v3] gdb/arm: Handle lazy FPU register stacking Content-Language: en-US To: Thiago Jung Bauermann CC: , , References: <20220927190944.201748-1-torbjorn.svensson@foss.st.com> <87pmfgeg1h.fsf@linaro.org> From: Torbjorn SVENSSON In-Reply-To: <87pmfgeg1h.fsf@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.75.127.123] X-ClientProxiedBy: GPXDAG2NODE4.st.com (10.75.127.68) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-27_10,2022-09-27_01,2022-06-22_01 X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, NICE_REPLY_A, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 27 Sep 2022 20:27:53 -0000 Hello, On 2022-09-27 22:08, Thiago Jung Bauermann wrote: > > Hello, > > Torbjörn SVENSSON via Gdb-patches writes: > >> diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c >> index 2810232fcb8..43ce1a45782 100644 >> --- a/gdb/arm-tdep.c >> +++ b/gdb/arm-tdep.c >> @@ -68,6 +68,7 @@ >> #endif >> >> static bool arm_debug; >> +static bool force_fpu_regs_from_stack = false; > > I'm a bit concerned about having a global variable to indicate what is > (IIUC) a per-CPU state. Does this logic work with multi-processor > inferiors? > > Instead of using a global variable, can arm_m_exception_cache use > “this_frame->level > 0” to decide whether to get the FPU registers from > the stack? > I share your concern, but haven't found any better way to achieve the required condition. The content of FPCCR shall only be considered for the first extended exception frame on the stack. As there are likely other kinds of frames on the stack, the level would not be enough to decide if stack or registers should be used. Do you know a way that this state can be saved per inferior? On the other hand, I got the impression that the cache is purged when the inferior is switched, but this assumption might be wrong. I've only verified the function with a simple single inferior. Kind regards, Torbjörn