From: Andrew Burgess <andrew.burgess@embecosm.com>
To: gdb-patches@sourceware.org
Cc: Nelson Chu <nelson.chu@sifive.com>, Jim Wilson <jimw@sifive.com>,
Tom Tromey <tom@tromey.com>,
palmer@dabbelt.com, Andrew Burgess <andrew.burgess@embecosm.com>
Subject: [PATCH 0/8] RISC-V target description and register handling fixes
Date: Tue, 16 Jun 2020 18:14:39 +0100 [thread overview]
Message-ID: <cover.1592327296.git.andrew.burgess@embecosm.com> (raw)
This series includes a mixed bag of changes around RISC-V's target
description and general register handling. This includes a fix for an
issue Tom reported here:
https://sourceware.org/pipermail/gdb-patches/2020-June/169323.html
Though most of the changes are RISC-V only, patch #6 does make a
change to the generic target description handling code so is probably
worth additional review.
Feedback welcome,
Thanks,
Andrew
---
Andrew Burgess (8):
gdb/riscv: Improved register alias name creation
gdb/riscv: Fix whitespace error
gdb/riscv: Take CSR names from target description
gdb/riscv: Remove CSR feature file
gdb/riscv: Improve support for matching against target descriptions
gdb: Extend target description processing of unknown registers
gdb/riscv: Record information about unknown tdesc registers
gdb/riscv: Loop over all registers for 'info all-registers'
gdb/ChangeLog | 85 +++
gdb/features/Makefile | 6 -
gdb/features/riscv/32bit-csr.c | 253 ---------
gdb/features/riscv/32bit-csr.xml | 251 ---------
gdb/features/riscv/64bit-csr.c | 253 ---------
gdb/features/riscv/64bit-csr.xml | 186 -------
gdb/features/riscv/rebuild-csr-xml.sh | 37 --
gdb/riscv-tdep.c | 519 ++++++++++++------
gdb/riscv-tdep.h | 15 +
gdb/target-descriptions.c | 31 +-
gdb/target-descriptions.h | 27 +-
gdb/testsuite/ChangeLog | 27 +
.../gdb.arch/riscv-tdesc-loading-01.xml | 83 +++
.../gdb.arch/riscv-tdesc-loading-02.xml | 81 +++
.../gdb.arch/riscv-tdesc-loading-03.xml | 79 +++
.../gdb.arch/riscv-tdesc-loading-04.xml | 77 +++
.../gdb.arch/riscv-tdesc-loading.exp | 39 ++
.../gdb.arch/riscv-tdesc-regs-32.xml | 89 +++
.../gdb.arch/riscv-tdesc-regs-64.xml | 93 ++++
gdb/testsuite/gdb.arch/riscv-tdesc-regs.c | 22 +
gdb/testsuite/gdb.arch/riscv-tdesc-regs.exp | 123 +++++
21 files changed, 1235 insertions(+), 1141 deletions(-)
delete mode 100644 gdb/features/riscv/32bit-csr.c
delete mode 100644 gdb/features/riscv/32bit-csr.xml
delete mode 100644 gdb/features/riscv/64bit-csr.c
delete mode 100644 gdb/features/riscv/64bit-csr.xml
delete mode 100755 gdb/features/riscv/rebuild-csr-xml.sh
create mode 100644 gdb/testsuite/gdb.arch/riscv-tdesc-loading-01.xml
create mode 100644 gdb/testsuite/gdb.arch/riscv-tdesc-loading-02.xml
create mode 100644 gdb/testsuite/gdb.arch/riscv-tdesc-loading-03.xml
create mode 100644 gdb/testsuite/gdb.arch/riscv-tdesc-loading-04.xml
create mode 100644 gdb/testsuite/gdb.arch/riscv-tdesc-loading.exp
create mode 100644 gdb/testsuite/gdb.arch/riscv-tdesc-regs-32.xml
create mode 100644 gdb/testsuite/gdb.arch/riscv-tdesc-regs-64.xml
create mode 100644 gdb/testsuite/gdb.arch/riscv-tdesc-regs.c
create mode 100644 gdb/testsuite/gdb.arch/riscv-tdesc-regs.exp
--
2.25.4
next reply other threads:[~2020-06-16 17:14 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-16 17:14 Andrew Burgess [this message]
2020-06-16 17:14 ` [PATCH 1/8] gdb/riscv: Improved register alias name creation Andrew Burgess
2020-06-18 20:36 ` Tom Tromey
2020-06-16 17:14 ` [PATCH 2/8] gdb/riscv: Fix whitespace error Andrew Burgess
2020-06-16 17:14 ` [PATCH 3/8] gdb/riscv: Take CSR names from target description Andrew Burgess
2020-06-16 17:14 ` [PATCH 4/8] gdb/riscv: Remove CSR feature file Andrew Burgess
2020-06-16 17:14 ` [PATCH 5/8] gdb/riscv: Improve support for matching against target descriptions Andrew Burgess
2020-06-16 17:14 ` [PATCH 6/8] gdb: Extend target description processing of unknown registers Andrew Burgess
2020-06-16 17:14 ` [PATCH 7/8] gdb/riscv: Record information about unknown tdesc registers Andrew Burgess
2020-06-16 17:14 ` [PATCH 8/8] gdb/riscv: Loop over all registers for 'info all-registers' Andrew Burgess
2020-06-17 1:31 ` [PATCH 0/8] RISC-V target description and register handling fixes Nelson Chu
2020-06-18 20:45 ` Tom Tromey
2020-06-18 20:54 ` Andrew Burgess
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