From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id BC1053858C54; Tue, 9 Aug 2022 03:37:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org BC1053858C54 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id A5B15300089; Tue, 9 Aug 2022 03:37:35 +0000 (UTC) From: Tsukasa OI To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt , Liao Shihua Cc: binutils@sourceware.org, gdb-patches@sourceware.org Subject: [PATCH v4 0/3] RISC-V: Add 'Zmmul' extension Date: Tue, 9 Aug 2022 12:37:24 +0900 Message-Id: In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-6.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 09 Aug 2022 03:37:43 -0000 Hi RISC-V folks, This patch is PATCH v4 of the Zmmul support patchset primarily for Binutils but also contains some GDB changes (simulator fix and new testcase). ***WARNING (BLOCKER)*** Although I already assigned the copyright for my Binutils contribution, I haven't completed the copyright assignment for my GDB contribution (because the simulator that need to be fixed is a part of GDB). So don't merge this until my copyright assignment completes. Once that's done, I will send a ping to the people concerned. Note: To test the simulator, it requires another patch: that fixes a minor problem on the arch-specific simulator testing. This is also a GDB change so once my copyright assignment is done, I will ping *and* submit the same patch to gdb-patches@sourceware.org. Tracker on GitHub: PATCH v1: PATCH v2: PATCH v3: This is based on the ISA Manual, draft-20220707-f518c25: This patchset also contains generic 'M' extension testcases. [Changes: v3 -> v4] - Minor rebase - Fixed the issue that caused the failure of the simulator test. [Changes: v2 -> v3] - Minor rebase - Fixed an issue which caused the simulator to stop working. [Changes: v1 -> v2] - Minor rebase - On testcases, use macro symbols with no leading underscores (__64_bit__ -> rv64 and __zmmul__ -> zmmul) Thanks to Shihua for feedback. - Renamed some testcases [BUG in PATCH v2: Simulator stopped working after PATCH v2] The cause was simple. The simulator supports I, M and A extensions and the instruction is identified by those instruction classes: - INSN_CLASS_I (for 'I') - INSN_CLASS_M (for 'M') - INSN_CLASS_A (for 'A') I forgot to add INSN_CLASS_ZMMUL (for 'M') and that caused multiply instructions to cause failure. PATCH v3 fixed that and I added a testcase (checks whether all RV32M instructions run without any fault). [RFC: Implied extension (same text as PATCH v2)] Tsukasa OI's (my) patchset implies 'Zmmul' from 'M'. LIAO Shihua's patch does not imply 'Zmmul' from 'M'. c.f. (OI) c.f. (LIAO) My position is derived from existing implications: Zhinx -> Zhinxmin and Zfh -> Zfhmin. Big problem is, those implications are implemented by ME. I have no or a little preference here and I would like to hear your thoughts. Thanks, Tsukasa Tsukasa OI (3): RISC-V: Add 'M' extension testcases RISC-V: Add 'Zmmul' extension RISC-V: Add 'Zmmul' failure testcases bfd/elfxx-riscv.c | 6 +++++ gas/testsuite/gas/riscv/attribute-09.d | 2 +- gas/testsuite/gas/riscv/m-ext-32.d | 18 +++++++++++++ gas/testsuite/gas/riscv/m-ext-64.d | 23 ++++++++++++++++ .../gas/riscv/m-ext-fail-noarch-64.d | 4 +++ .../gas/riscv/m-ext-fail-noarch-64.l | 14 ++++++++++ gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d | 4 +++ gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l | 6 +++++ gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d | 4 +++ gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l | 5 ++++ gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d | 4 +++ gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l | 9 +++++++ gas/testsuite/gas/riscv/m-ext.s | 21 +++++++++++++++ gas/testsuite/gas/riscv/option-arch-02.d | 2 +- gas/testsuite/gas/riscv/zmmul-32.d | 14 ++++++++++ gas/testsuite/gas/riscv/zmmul-64.d | 15 +++++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 26 +++++++++---------- sim/riscv/sim-main.c | 1 + sim/testsuite/riscv/m-ext.s | 18 +++++++++++++ 20 files changed, 182 insertions(+), 15 deletions(-) create mode 100644 gas/testsuite/gas/riscv/m-ext-32.d create mode 100644 gas/testsuite/gas/riscv/m-ext-64.d create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l create mode 100644 gas/testsuite/gas/riscv/m-ext.s create mode 100644 gas/testsuite/gas/riscv/zmmul-32.d create mode 100644 gas/testsuite/gas/riscv/zmmul-64.d create mode 100644 sim/testsuite/riscv/m-ext.s base-commit: 65c9841b6fee984714509acef6e52366363072b6 -- 2.34.1