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From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
 Andrew Burgess <aburgess@redhat.com>, Mike Frysinger <vapier@gentoo.org>,
 Nelson Chu <nelson@rivosinc.com>, Kito Cheng <kito.cheng@sifive.com>,
 Palmer Dabbelt <palmer@dabbelt.com>
Cc: gdb-patches@sourceware.org
Subject: [PATCH 0/1] sim/riscv: Complete tidying up with SBREAK
Date: Sun,  4 Sep 2022 07:45:05 +0000
Message-Id: <cover.1662277499.git.research_trasio@irq.a4lg.com>
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Hello,

This commit removes SBREAK-related references on the simulator as SBREAK
instruction is renamed to EBREAK in the RISC-V ISA 2.1 (May 31, 2016).

This is the simulator part (can be merged independently).




Tsukasa OI (1):
  sim/riscv: Complete tidying up with SBREAK

 sim/riscv/sim-main.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)


base-commit: 148b68a56c57d69bd97a5f40c34fc4700693596a
-- 
2.34.1