From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id BDF723854164 for ; Thu, 6 Oct 2022 10:33:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org BDF723854164 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 1F688300089; Thu, 6 Oct 2022 10:33:08 +0000 (UTC) From: Tsukasa OI To: Tsukasa OI , Palmer Dabbelt Cc: gdb-patches@sourceware.org Subject: [PING^3 PATCH 0/1] sim/riscv: PR29595, Fix broken RISC-V simulater after implementing 'Zmmul' Date: Thu, 6 Oct 2022 10:32:59 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-6.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 06 Oct 2022 10:33:11 -0000 NOTE: the cover letter and subject may change each time I ping. Hello, As I describe later, this patchset fixes now-broken RISC-V instruction simulator. I hope this patchset is approved as fast as possible since it's clearly a functional blocker for GDB 13.1. The patch is a PING (3) of . Issue Tracker on Sourceware Bugzilla: Tracker on GitHub: Previous: 'Zmmul' v5: Due to opcodes changes (to add the 'Zmmul' extension in the commit 0938b032daa5 "RISC-V: Add 'Zmmul' extension in assembler."), the instruction simulator for RISC-V is now broken. For multiply/divide instructions in the 'M' extension, only division / remainder instructions work and **multiply instructions cause a trap**. This is because only one side of my 'Zmmul' patchset is applied and GDB- part of my 'Zmmul' patchset (this) is not approved yet. In the current master, multiply instructions of the RISC-V simulator doesn't work. The cause was simple. The RISC-V simulator supports 'I', 'M' and 'A' extensions and the instruction is identified by those instruction classes: - INSN_CLASS_I (for 'I') - INSN_CLASS_M (for 'M') - INSN_CLASS_A (for 'A') After adding the 'Zmmul' extension, INSN_CLASS_M is splitted to: - INSN_CLASS_ZMMUL (multiply instructions) - INSN_CLASS_M (division instructions) So, the simulator must handle INSN_CLASS_ZMMUL separately. My 'Zmmul' patchset fixed that and I added a testcase (checks whether all RV32M instructions run without any fault) but only opcodes part is applied so it's now broken state for the simulator. This is the simulator part of the original 'Zmmul' patchset (from PATCH v5). Note: To confirm that the simulator is fixed, it requires another patch. Without the patch above, all multiply instructions will still work. Still, testing whether the simulator works with this extension (with `make check-sim') requires it. Regards, Tsukasa Tsukasa OI (1): sim/riscv: PR29595, Fix multiply instructions sim/riscv/sim-main.c | 1 + sim/testsuite/riscv/m-ext.s | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) create mode 100644 sim/testsuite/riscv/m-ext.s base-commit: 80e0c6dc91f52fad32c3ff3cf20da889d77013ac -- 2.34.1