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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Feb 2023 08:11:27.7218 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 50e30e6a-7620-4fce-69f3-08db08e2e992 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT053.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR08MB5776 X-Spam-Status: No, score=-6.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,KAM_DMARC_NONE,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 2/6/23 20:29, Pedro Alves wrote: > On 2023-02-04 3:21 p.m., Thiago Jung Bauermann via Gdb-patches wrote: >> >> Luis Machado writes: >> >>> On 2/2/23 03:47, Simon Marchi wrote: >>>> On 2/1/23 21:54, Thiago Jung Bauermann wrote: >>>>> In any case, it wouldn't be possible to make get_thread_target_desc just >>>>> return thread_info->tdesc because at least the way these patches are >>>>> currently written, when the inferior starts or a new thread of the >>>>> inferior is spawned thread_info->tdesc is nullptr. gdbserver will only >>>>> call get_thread_tdesc after the first stop (in get_thread_regcache, in >>>>> the process of obtaining the pc register), so we will need to cope with >>>>> that situation. >>>> Ok. Would it work if a new thread initially inherited the tdesc from >>>> its process? >>>> >>> >>> It should be fine because the first time we fetch a process target >>> description, it is eventually obtained from the first and only thread. >>> So the SVE vector length should be correct. >>> >>> Any subsequent attempts to use the process' target description (the >>> first one we obtained), after further stops, may end up using an >>> incorrect description. >>> >>> I think this is handled correctly by the target architecture target >>> hook though. But there are other places where this is potentially >>> incorrect. >>> >>> For example... >>> >>> - When using gcore to dump a core file, GDB only dumps a single target >>> description. While this might be correct for a target with a fixed >>> target description or a AArch64 target that doesn't support SVE, it >>> likely won't be correctly for one AArch64 target supporting SVE if its >>> threads changed vector length mid-execution. Either we emit target >>> description notes by thread, or we don't emit a target description >>> note for those cases. >>> >>> - When loading the above/older gcore core files back, GDB will use a >>> potentially incorrect target description. If we decide to emit >>> per-thread target descriptions, it should be fine. Otherwise we may >>> need to have a "thread architecture" hook for core files as well. >>> >>> - The remote has no concept of a thread architecture (Thiago is >>> addressing this with this patch series). >>> >>> - AArch64 frames may have slightly different vg values, which means >>> their gdbarches are different as well. >>> >>> Given the differences between two gdbarches are small, we mostly get >>> away with it. But if there are further differences (different hooks, >>> for example), I fear we may run into a situation where we use an >>> incorrect gdbarch to call a particular hook. >> >> Indeed, good points! Thank you for bringing them up. I can address core >> file dumping/loading after this series. >> >> Regarding frames with different vg values, it's important to be aware of >> this discrepancy but IMHO it makes sense to work on it when it becomes >> a problem... >> > > > Yeah, one thought that keeps crossing my mind is if really modeling all this > stuff as different target descriptions is really the best approach. The Intel AMX > support posted on the list last year also ran into a similar problem, with the > matrix registers height/width changing at runtime, and it is impractical (or really, > it really smells like the wrong approach) to have different target descriptions for > every potential matrix size. Which is not unlike different SVE sizes. It feels like > a single tdesc should be able to be a bit more dynamic. It's a bit funny that ptrace > manages to work with a single registers interface, while we don't. My understanding is that this was a bit hard to justify back when SVE was implemented, as it would have to touch some other bits of the type system to create a sizeless type for SVE vectors, where the size would be determined by context. > > What if we extended the target description mechanism so that a single description > could describe all SVE sizes? For example, what if a tdesc could describe the SVE > width/length as a dynamic property, retrieved from elsewhere, e.g., from another register? > > BTW, for core files, where are we going to retrieve the SVE length from? The thread-specific vector length should be available from the SVE register dump sections.