From: Carl Love <cel@us.ibm.com>
To: will schmidt <will_schmidt@vnet.ibm.com>,
gdb-patches@sourceware.org,
Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
Cc: Rogerio Alves <rogealve@br.ibm.com>, tromey@adacore.com, cel@us.ibm.com
Subject: Re: [PATCH V2 Ping] Powerpc: Update expected floating point output for gdb.arch/altivec-regs.exp and gdb.arch/vsx-regs.exp
Date: Fri, 22 Apr 2022 12:50:52 -0700 [thread overview]
Message-ID: <d925fe1c7617d6688f0d2c88cc46a5381d3af265.camel@us.ibm.com> (raw)
In-Reply-To: <cd3bb2935cb0c5dd2b3388984708df91670408c0.camel@us.ibm.com>
Will, GDB maintainers:
Just checking to see if there were any more comments? If not, is the
patch ready to commit?
Thanks.
Carl Love
On Mon, 2022-04-18 at 13:04 -0700, Carl Love wrote:
> Will, GDB maintainers:
>
> On Mon, 2022-04-18 at 11:20 -0500, will schmidt wrote:
> > On Mon, 2022-04-11 at 21:47 -0700, Carl Love wrote:
> > > GDB maintainers:
> > >
> >
> > Hi.
> > The "Powerpc" in the subject should be "PowerPC". Maybe should
> > actually be rs6000, dunno.. :-)
>
> Changed it to PowerPC.
>
> Updated commit message to indicate the formatting fix, to say
> hexadecimal format and add new float128 entry in the VSX expected
> values.
>
> Fixed up the comment in the test case as Will pointed out.
>
> Retested the Patch on Power 10.
>
> Please let me know if anyone sees any additional issues that need
> fixing. Thanks.
>
> Carl Love
> --------------------------------------------------
> PowerPC: Update expected floating point output for gdb.arch/altivec-
> regs.exp and gdb.arch/vsx-regs.exp
>
> The format for printing the floating point values was changed by
> commit:
>
> commit 56262a931b7ca8ee3ec9104bc7e9e0b40cf3d64e
> Author: Tom Tromey <tromey@adacore.com>
> Date: Thu Feb 17 13:43:59 2022 -0700
>
> Change how "print/x" displays floating-point value
>
> Currently, "print/x" will display a floating-point value by
> first
> casting it to an integer type. This yields weird results
> like:
>
> (gdb) print/x 1.5
> $1 = 0x1
> ...
> Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=16242
>
> The above change results in 417 regression test failures since the
> expected
> Power vector register output no longer match.
>
> This patch updates the expected Altivec floating point register
> prints to the
> hexadecimal format for both big endian and little endian
> systems. The patch
> also fixes a formatting isue with the decimal_vector expected value
> assign
> statements.
>
> The expected VSX vector_register1, vector_register1_vr,
> vector_register2,
> vector_register2_vr are updated to include the new float128 entry.
> Additionally, the initialization of the vs registers is updated in
> vsx-regs.exp
> to inialize both double words.
>
> The patch has been tested on Power 10, Power 8 LE and Power 8 BE.
> ---
> PowerPC: Update expected floating point output for gdb.arch/altivec-
> regs.exp and gdb.arch/vsx-regs.exp
>
> The format for printing the floating point values was changed by
> commit:
>
> commit 56262a931b7ca8ee3ec9104bc7e9e0b40cf3d64e
> Author: Tom Tromey <tromey@adacore.com>
> Date: Thu Feb 17 13:43:59 2022 -0700
>
> Change how "print/x" displays floating-point value
>
> Currently, "print/x" will display a floating-point value by
> first
> casting it to an integer type. This yields weird results
> like:
>
> (gdb) print/x 1.5
> $1 = 0x1
> ...
> Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=16242
>
> The above change results in 417 regression test failures since the
> expected
> Power vector register output no longer match.
>
> This patch updates the expected Altivec floating point register
> prints to the
> hexadecimal format for both big endian and little endian
> systems. The patch
> also fixes a formatting isue with the decimal_vector expected value
> assign
> statements.
>
> The expected VSX vector_register1, vector_register1_vr,
> vector_register2,
> vector_register2_vr variables are updated to include the new float128
> entry.
> Additionally, the comment in the vsx expect file about the
> initialization
> of the vs registers is updated.
>
> The patch has been tested on Power 10, Power 8 LE and Power 8 BE.
> ---
> gdb/testsuite/gdb.arch/altivec-regs.exp | 8 +++----
> gdb/testsuite/gdb.arch/vsx-regs.exp | 31 +++++++++++++--------
> ----
> 2 files changed, 20 insertions(+), 19 deletions(-)
>
> diff --git a/gdb/testsuite/gdb.arch/altivec-regs.exp
> b/gdb/testsuite/gdb.arch/altivec-regs.exp
> index 7bae979b984..d4c13afa8a1 100644
> --- a/gdb/testsuite/gdb.arch/altivec-regs.exp
> +++ b/gdb/testsuite/gdb.arch/altivec-regs.exp
> @@ -84,9 +84,9 @@ set endianness [get_endianness]
> # b) the register read (below) also works.
>
> if {$endianness == "big"} {
> -set vector_register ".uint128 = 0x1000000010000000100000001,
> v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1.,
> v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0,
> 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
> 0x1.."
> +set vector_register ".uint128 = 0x1000000010000000100000001,
> v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1.,
> v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0,
> 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
> 0x1.."
> } else {
> -set vector_register ".uint128 = 0x1000000010000000100000001,
> v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1.,
> v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1,
> 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0,
> 0x0.."
> +set vector_register ".uint128 = 0x1000000010000000100000001,
> v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1.,
> v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1,
> 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0,
> 0x0.."
> }
>
> for {set i 0} {$i < 32} {incr i 1} {
> @@ -104,9 +104,9 @@ gdb_test "info reg vscr" "vscr.*0x1\[ \t\]+1"
> "info reg vscr"
> # the way gdb works.
>
> if {$endianness == "big"} {
> - set decimal_vector ".uint128 = 79228162532711081671548469249,
> v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1,
> 1., v8_int16 = .0, 1, 0, 1, 0, 1, 0, 1., v16_int8 = .0, 0, 0, 1, 0,
> 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1.."
> + set decimal_vector ".uint128 = 79228162532711081671548469249,
> v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1,
> 1., v8_int16 = .0, 1, 0, 1, 0, 1, 0, 1., v16_int8 = .0, 0, 0, 1, 0,
> 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1.."
> } else {
> - set decimal_vector ".uint128 = 79228162532711081671548469249,
> v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1,
> 1., v8_int16 = .1, 0, 1, 0, 1, 0, 1, 0., v16_int8 = .1, 0, 0, 0, 1,
> 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0.."
> + set decimal_vector ".uint128 = 79228162532711081671548469249,
> v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1,
> 1., v8_int16 = .1, 0, 1, 0, 1, 0, 1, 0., v16_int8 = .1, 0, 0, 0, 1,
> 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0.."
> }
>
> for {set i 0} {$i < 32} {incr i 1} {
> diff --git a/gdb/testsuite/gdb.arch/vsx-regs.exp
> b/gdb/testsuite/gdb.arch/vsx-regs.exp
> index 8b3841362fe..56fea796a9b 100644
> --- a/gdb/testsuite/gdb.arch/vsx-regs.exp
> +++ b/gdb/testsuite/gdb.arch/vsx-regs.exp
> @@ -61,29 +61,29 @@ set endianness [get_endianness]
> # Data sets used throughout the test
>
> if {$endianness == "big"} {
> - set vector_register1 ".uint128 =
> 0x3ff4cccccccccccd0000000000000000, v2_double = .0x1, 0x0., v4_float
> = .0x1, 0xf9999998, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccd,
> 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x0, 0x0,
> 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd,
> 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.."
> + set vector_register1 ".float128 =
> 0x3ff4cccccccccccd0000000000000000, uint128 =
> 0x3ff4cccccccccccd0000000000000000, v2_double = .0x3ff4cccccccccccd,
> 0x0., v4_float = .0x3ff4cccc, 0xcccccccd, 0x0, 0x0., v4_int32 =
> .0x3ff4cccc, 0xcccccccd, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc,
> 0xcccc, 0xcccd, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc,
> 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
> 0x0.."
>
> - set vector_register1_vr ".uint128 =
> 0x3ff4cccccccccccd0000000100000001, v4_float = .0x1, 0xf9999998, 0x0,
> 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x1, 0x1., v8_int16 =
> .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x1, 0x0, 0x1., v16_int8 =
> .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x1,
> 0x0, 0x0, 0x0, 0x1.."
> + set vector_register1_vr ".uint128 =
> 0x3ff4cccccccccccd0000000100000001, v4_float = .0x3ff4cccc,
> 0xcccccccd, 0x1, 0x1., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x1, 0x1.,
> v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x1, 0x0, 0x1.,
> v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0,
> 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
>
> - set vector_register2 "uint128 =
> 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x8000000000000000,
> 0x8000000000000000., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 =
> .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead,
> 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 =
> .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe,
> 0xef, 0xde, 0xad, 0xbe, 0xef.."
> + set vector_register2 ".float128 =
> 0xdeadbeefdeadbeefdeadbeefdeadbeef, uint128 =
> 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0xdeadbeefdeadbeef,
> 0xdeadbeefdeadbeef., v4_float = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
> 0xdeadbeef., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
> 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead,
> 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde,
> 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
>
> - set vector_register2_vr "uint128 =
> 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0.,
> v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16
> = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef.,
> v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde,
> 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
> + set vector_register2_vr ".uint128 =
> 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0xdeadbeef,
> 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v4_int32 = .0xdeadbeef,
> 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef,
> 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde,
> 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef,
> 0xde, 0xad, 0xbe, 0xef.."
>
> - set vector_register3 ".uint128 = 0x1000000010000000100000001,
> v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 =
> .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0,
> 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0,
> 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
> + set vector_register3 ".float128 = 0x1000000010000000100000001,
> uint128 = 0x1000000010000000100000001, v2_double = .0x100000001,
> 0x100000001., v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1,
> 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1.,
> v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
> 0x1, 0x0, 0x0, 0x0, 0x1.."
>
> - set vector_register3_vr ".uint128 = 0x1000000010000000100000001,
> v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1.,
> v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0,
> 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
> 0x1.."
> + set vector_register3_vr ".uint128 = 0x1000000010000000100000001,
> v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1.,
> v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0,
> 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
> 0x1.."
> } else {
> - set vector_register1 ".uint128 =
> 0x3ff4cccccccccccd0000000000000000, v2_double = .0x0, 0x1., v4_float
> = .0x0, 0x0, 0xf9999998, 0x1., v4_int32 = .0x0, 0x0, 0xcccccccd,
> 0x3ff4cccc., v8_int16 = .0x0, 0x0, 0x0, 0x0, 0xcccd, 0xcccc, 0xcccc,
> 0x3ff4., v16_int8 = .0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcd,
> 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.."
> + set vector_register1 ".float128 =
> 0x3ff4cccccccccccd0000000000000000, uint128 =
> 0x3ff4cccccccccccd0000000000000000, v2_double = .0x0,
> 0x3ff4cccccccccccd., v4_float = .0x0, 0x0, 0xcccccccd, 0x3ff4cccc.,
> v4_int32 = .0x0, 0x0, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x0, 0x0,
> 0x0, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x0, 0x0, 0x0,
> 0x0, 0x0, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4,
> 0x3f.."
>
> - set vector_register1_vr ".uint128 =
> 0x3ff4cccccccccccd0000000100000001, v4_float = .0x0, 0x0, 0xf9999998,
> 0x1., v4_int32 = .0x1, 0x1, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x1,
> 0x0, 0x1, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x1, 0x0,
> 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc,
> 0xf4, 0x3f.."
> + set vector_register1_vr ".uint128 =
> 0x3ff4cccccccccccd0000000100000001, v4_float = .0x1, 0x1, 0xcccccccd,
> 0x3ff4cccc., v4_int32 = .0x1, 0x1, 0xcccccccd, 0x3ff4cccc., v8_int16
> = .0x1, 0x0, 0x1, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 =
> .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc,
> 0xcc, 0xcc, 0xf4, 0x3f.."
>
> - set vector_register2 "uint128 =
> 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x8000000000000000,
> 0x8000000000000000., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 =
> .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef,
> 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 =
> .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad,
> 0xde, 0xef, 0xbe, 0xad, 0xde.."
> + set vector_register2 ".float128 =
> 0xdeadbeefdeadbeefdeadbeefdeadbeef, uint128 =
> 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0xdeadbeefdeadbeef,
> 0xdeadbeefdeadbeef., v4_float = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
> 0xdeadbeef., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
> 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef,
> 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef,
> 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.."
>
> - set vector_register2_vr "uint128 =
> 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0.,
> v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16
> = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead.,
> v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef,
> 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.."
> + set vector_register2_vr ".uint128 =
> 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0xdeadbeef,
> 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v4_int32 = .0xdeadbeef,
> 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead,
> 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef,
> 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde,
> 0xef, 0xbe, 0xad, 0xde.."
>
> - set vector_register3 ".uint128 = 0x1000000010000000100000001,
> v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 =
> .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1,
> 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0,
> 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
> + set vector_register3 ".float128 = 0x1000000010000000100000001,
> uint128 = 0x1000000010000000100000001, v2_double = .0x100000001,
> 0x100000001., v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1,
> 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0.,
> v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0,
> 0x0, 0x1, 0x0, 0x0, 0x0.."
>
> - set vector_register3_vr ".uint128 = 0x1000000010000000100000001,
> v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1.,
> v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1,
> 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0,
> 0x0.."
> + set vector_register3_vr ".uint128 = 0x1000000010000000100000001,
> v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1.,
> v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1,
> 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0,
> 0x0.."
> }
>
> set float_register ".raw 0xdeadbeefdeadbeef."
> @@ -93,12 +93,13 @@ set float_register ".raw 0xdeadbeefdeadbeef."
> # after updates to F*.
> # Since dl_main uses some VS* registers, and per inspection their
> values are
> # no longer zero when our test reaches main(), we need to explicitly
> -# initialize the doubleword1 portions before we run our tests
> against
> -# values currently in those registers.
> +# initialize the VS* registers before we run our tests against the
> values
> +# currently in those registers.
>
> -# 0: Initialize the (doubleword 1) portion of the VS0-VS31
> registers.
> +# 0: Initialize the (doubleword 0 and 1) portion of the VS0-VS31
> registers.
> for {set i 0} {$i < 32} {incr i 1} {
> gdb_test_no_output "set \$vs$i.v2_double\[0\] = 0"
> + gdb_test_no_output "set \$vs$i.v2_double\[1\] = 0"
> }
>
> # 1: Set F0~F31 registers and check if it reflects on VS0~VS31.
next prev parent reply other threads:[~2022-04-22 19:50 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-12 4:47 Carl Love
2022-04-18 16:20 ` will schmidt
2022-04-18 20:04 ` [PATCH V2] " Carl Love
2022-04-22 19:50 ` Carl Love [this message]
2022-04-26 14:28 ` Ulrich Weigand
2022-04-26 17:24 ` Carl Love
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