From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id BF2B03858C83 for ; Fri, 22 Apr 2022 19:50:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org BF2B03858C83 Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 23MJiAHt012051; Fri, 22 Apr 2022 19:50:56 GMT Received: from ppma02wdc.us.ibm.com (aa.5b.37a9.ip4.static.sl-reverse.com [169.55.91.170]) by mx0a-001b2d01.pphosted.com with ESMTP id 3fjn0ykfmm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Apr 2022 19:50:56 +0000 Received: from pps.filterd (ppma02wdc.us.ibm.com [127.0.0.1]) by ppma02wdc.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 23MJhw6T006104; Fri, 22 Apr 2022 19:50:54 GMT Received: from b03cxnp08027.gho.boulder.ibm.com (b03cxnp08027.gho.boulder.ibm.com [9.17.130.19]) by ppma02wdc.us.ibm.com with ESMTP id 3fg2xwhkwx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Apr 2022 19:50:54 +0000 Received: from b03ledav004.gho.boulder.ibm.com (b03ledav004.gho.boulder.ibm.com [9.17.130.235]) by b03cxnp08027.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 23MJoqbr12517752 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 22 Apr 2022 19:50:53 GMT Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E1B867805E; Fri, 22 Apr 2022 19:50:52 +0000 (GMT) Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 775D37805C; Fri, 22 Apr 2022 19:50:52 +0000 (GMT) Received: from li-e362e14c-2378-11b2-a85c-87d605f3c641.ibm.com (unknown [9.163.11.46]) by b03ledav004.gho.boulder.ibm.com (Postfix) with ESMTP; Fri, 22 Apr 2022 19:50:52 +0000 (GMT) Message-ID: Subject: Re: [PATCH V2 Ping] Powerpc: Update expected floating point output for gdb.arch/altivec-regs.exp and gdb.arch/vsx-regs.exp From: Carl Love To: will schmidt , gdb-patches@sourceware.org, Ulrich Weigand Cc: Rogerio Alves , tromey@adacore.com, cel@us.ibm.com Date: Fri, 22 Apr 2022 12:50:52 -0700 In-Reply-To: References: <22d2e1a1c83cb00ffccc28e381aa9726ee6fc924.camel@vnet.ibm.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-18.el8) X-TM-AS-GCONF: 00 X-Proofpoint-GUID: TZon-QFR6HrkwKWnSidbR60pR8th93O4 X-Proofpoint-ORIG-GUID: TZon-QFR6HrkwKWnSidbR60pR8th93O4 Content-Transfer-Encoding: 7bit X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-04-22_06,2022-04-22_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 bulkscore=0 impostorscore=0 suspectscore=0 mlxscore=0 spamscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 malwarescore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2202240000 definitions=main-2204220083 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_LOTSOFHASH, SCC_10_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Apr 2022 19:51:01 -0000 Will, GDB maintainers: Just checking to see if there were any more comments? If not, is the patch ready to commit? Thanks. Carl Love On Mon, 2022-04-18 at 13:04 -0700, Carl Love wrote: > Will, GDB maintainers: > > On Mon, 2022-04-18 at 11:20 -0500, will schmidt wrote: > > On Mon, 2022-04-11 at 21:47 -0700, Carl Love wrote: > > > GDB maintainers: > > > > > > > Hi. > > The "Powerpc" in the subject should be "PowerPC". Maybe should > > actually be rs6000, dunno.. :-) > > Changed it to PowerPC. > > Updated commit message to indicate the formatting fix, to say > hexadecimal format and add new float128 entry in the VSX expected > values. > > Fixed up the comment in the test case as Will pointed out. > > Retested the Patch on Power 10. > > Please let me know if anyone sees any additional issues that need > fixing. Thanks. > > Carl Love > -------------------------------------------------- > PowerPC: Update expected floating point output for gdb.arch/altivec- > regs.exp and gdb.arch/vsx-regs.exp > > The format for printing the floating point values was changed by > commit: > > commit 56262a931b7ca8ee3ec9104bc7e9e0b40cf3d64e > Author: Tom Tromey > Date: Thu Feb 17 13:43:59 2022 -0700 > > Change how "print/x" displays floating-point value > > Currently, "print/x" will display a floating-point value by > first > casting it to an integer type. This yields weird results > like: > > (gdb) print/x 1.5 > $1 = 0x1 > ... > Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=16242 > > The above change results in 417 regression test failures since the > expected > Power vector register output no longer match. > > This patch updates the expected Altivec floating point register > prints to the > hexadecimal format for both big endian and little endian > systems. The patch > also fixes a formatting isue with the decimal_vector expected value > assign > statements. > > The expected VSX vector_register1, vector_register1_vr, > vector_register2, > vector_register2_vr are updated to include the new float128 entry. > Additionally, the initialization of the vs registers is updated in > vsx-regs.exp > to inialize both double words. > > The patch has been tested on Power 10, Power 8 LE and Power 8 BE. > --- > PowerPC: Update expected floating point output for gdb.arch/altivec- > regs.exp and gdb.arch/vsx-regs.exp > > The format for printing the floating point values was changed by > commit: > > commit 56262a931b7ca8ee3ec9104bc7e9e0b40cf3d64e > Author: Tom Tromey > Date: Thu Feb 17 13:43:59 2022 -0700 > > Change how "print/x" displays floating-point value > > Currently, "print/x" will display a floating-point value by > first > casting it to an integer type. This yields weird results > like: > > (gdb) print/x 1.5 > $1 = 0x1 > ... > Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=16242 > > The above change results in 417 regression test failures since the > expected > Power vector register output no longer match. > > This patch updates the expected Altivec floating point register > prints to the > hexadecimal format for both big endian and little endian > systems. The patch > also fixes a formatting isue with the decimal_vector expected value > assign > statements. > > The expected VSX vector_register1, vector_register1_vr, > vector_register2, > vector_register2_vr variables are updated to include the new float128 > entry. > Additionally, the comment in the vsx expect file about the > initialization > of the vs registers is updated. > > The patch has been tested on Power 10, Power 8 LE and Power 8 BE. > --- > gdb/testsuite/gdb.arch/altivec-regs.exp | 8 +++---- > gdb/testsuite/gdb.arch/vsx-regs.exp | 31 +++++++++++++-------- > ---- > 2 files changed, 20 insertions(+), 19 deletions(-) > > diff --git a/gdb/testsuite/gdb.arch/altivec-regs.exp > b/gdb/testsuite/gdb.arch/altivec-regs.exp > index 7bae979b984..d4c13afa8a1 100644 > --- a/gdb/testsuite/gdb.arch/altivec-regs.exp > +++ b/gdb/testsuite/gdb.arch/altivec-regs.exp > @@ -84,9 +84,9 @@ set endianness [get_endianness] > # b) the register read (below) also works. > > if {$endianness == "big"} { > -set vector_register ".uint128 = 0x1000000010000000100000001, > v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., > v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, > 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, > 0x1.." > +set vector_register ".uint128 = 0x1000000010000000100000001, > v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1., > v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, > 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, > 0x1.." > } else { > -set vector_register ".uint128 = 0x1000000010000000100000001, > v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., > v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, > 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, > 0x0.." > +set vector_register ".uint128 = 0x1000000010000000100000001, > v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1., > v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, > 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, > 0x0.." > } > > for {set i 0} {$i < 32} {incr i 1} { > @@ -104,9 +104,9 @@ gdb_test "info reg vscr" "vscr.*0x1\[ \t\]+1" > "info reg vscr" > # the way gdb works. > > if {$endianness == "big"} { > - set decimal_vector ".uint128 = 79228162532711081671548469249, > v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1, > 1., v8_int16 = .0, 1, 0, 1, 0, 1, 0, 1., v16_int8 = .0, 0, 0, 1, 0, > 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1.." > + set decimal_vector ".uint128 = 79228162532711081671548469249, > v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1, > 1., v8_int16 = .0, 1, 0, 1, 0, 1, 0, 1., v16_int8 = .0, 0, 0, 1, 0, > 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1.." > } else { > - set decimal_vector ".uint128 = 79228162532711081671548469249, > v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1, > 1., v8_int16 = .1, 0, 1, 0, 1, 0, 1, 0., v16_int8 = .1, 0, 0, 0, 1, > 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0.." > + set decimal_vector ".uint128 = 79228162532711081671548469249, > v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1, > 1., v8_int16 = .1, 0, 1, 0, 1, 0, 1, 0., v16_int8 = .1, 0, 0, 0, 1, > 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0.." > } > > for {set i 0} {$i < 32} {incr i 1} { > diff --git a/gdb/testsuite/gdb.arch/vsx-regs.exp > b/gdb/testsuite/gdb.arch/vsx-regs.exp > index 8b3841362fe..56fea796a9b 100644 > --- a/gdb/testsuite/gdb.arch/vsx-regs.exp > +++ b/gdb/testsuite/gdb.arch/vsx-regs.exp > @@ -61,29 +61,29 @@ set endianness [get_endianness] > # Data sets used throughout the test > > if {$endianness == "big"} { > - set vector_register1 ".uint128 = > 0x3ff4cccccccccccd0000000000000000, v2_double = .0x1, 0x0., v4_float > = .0x1, 0xf9999998, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccd, > 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x0, 0x0, > 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, > 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.." > + set vector_register1 ".float128 = > 0x3ff4cccccccccccd0000000000000000, uint128 = > 0x3ff4cccccccccccd0000000000000000, v2_double = .0x3ff4cccccccccccd, > 0x0., v4_float = .0x3ff4cccc, 0xcccccccd, 0x0, 0x0., v4_int32 = > .0x3ff4cccc, 0xcccccccd, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, > 0xcccc, 0xcccd, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, > 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, > 0x0.." > > - set vector_register1_vr ".uint128 = > 0x3ff4cccccccccccd0000000100000001, v4_float = .0x1, 0xf9999998, 0x0, > 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x1, 0x1., v8_int16 = > .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x1, 0x0, 0x1., v16_int8 = > .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x1, > 0x0, 0x0, 0x0, 0x1.." > + set vector_register1_vr ".uint128 = > 0x3ff4cccccccccccd0000000100000001, v4_float = .0x3ff4cccc, > 0xcccccccd, 0x1, 0x1., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x1, 0x1., > v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x1, 0x0, 0x1., > v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, > 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." > > - set vector_register2 "uint128 = > 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x8000000000000000, > 0x8000000000000000., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = > .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, > 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = > .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, > 0xef, 0xde, 0xad, 0xbe, 0xef.." > + set vector_register2 ".float128 = > 0xdeadbeefdeadbeefdeadbeefdeadbeef, uint128 = > 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0xdeadbeefdeadbeef, > 0xdeadbeefdeadbeef., v4_float = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, > 0xdeadbeef., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, > 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, > 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, > 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.." > > - set vector_register2_vr "uint128 = > 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., > v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 > = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., > v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, > 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.." > + set vector_register2_vr ".uint128 = > 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0xdeadbeef, > 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v4_int32 = .0xdeadbeef, > 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, > 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, > 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, > 0xde, 0xad, 0xbe, 0xef.." > > - set vector_register3 ".uint128 = 0x1000000010000000100000001, > v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = > .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, > 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, > 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." > + set vector_register3 ".float128 = 0x1000000010000000100000001, > uint128 = 0x1000000010000000100000001, v2_double = .0x100000001, > 0x100000001., v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, > 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., > v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, > 0x1, 0x0, 0x0, 0x0, 0x1.." > > - set vector_register3_vr ".uint128 = 0x1000000010000000100000001, > v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., > v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, > 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, > 0x1.." > + set vector_register3_vr ".uint128 = 0x1000000010000000100000001, > v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1., > v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, > 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, > 0x1.." > } else { > - set vector_register1 ".uint128 = > 0x3ff4cccccccccccd0000000000000000, v2_double = .0x0, 0x1., v4_float > = .0x0, 0x0, 0xf9999998, 0x1., v4_int32 = .0x0, 0x0, 0xcccccccd, > 0x3ff4cccc., v8_int16 = .0x0, 0x0, 0x0, 0x0, 0xcccd, 0xcccc, 0xcccc, > 0x3ff4., v16_int8 = .0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcd, > 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.." > + set vector_register1 ".float128 = > 0x3ff4cccccccccccd0000000000000000, uint128 = > 0x3ff4cccccccccccd0000000000000000, v2_double = .0x0, > 0x3ff4cccccccccccd., v4_float = .0x0, 0x0, 0xcccccccd, 0x3ff4cccc., > v4_int32 = .0x0, 0x0, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x0, 0x0, > 0x0, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x0, 0x0, 0x0, > 0x0, 0x0, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, > 0x3f.." > > - set vector_register1_vr ".uint128 = > 0x3ff4cccccccccccd0000000100000001, v4_float = .0x0, 0x0, 0xf9999998, > 0x1., v4_int32 = .0x1, 0x1, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x1, > 0x0, 0x1, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x1, 0x0, > 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, > 0xf4, 0x3f.." > + set vector_register1_vr ".uint128 = > 0x3ff4cccccccccccd0000000100000001, v4_float = .0x1, 0x1, 0xcccccccd, > 0x3ff4cccc., v4_int32 = .0x1, 0x1, 0xcccccccd, 0x3ff4cccc., v8_int16 > = .0x1, 0x0, 0x1, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = > .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, > 0xcc, 0xcc, 0xf4, 0x3f.." > > - set vector_register2 "uint128 = > 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x8000000000000000, > 0x8000000000000000., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = > .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, > 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = > .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, > 0xde, 0xef, 0xbe, 0xad, 0xde.." > + set vector_register2 ".float128 = > 0xdeadbeefdeadbeefdeadbeefdeadbeef, uint128 = > 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0xdeadbeefdeadbeef, > 0xdeadbeefdeadbeef., v4_float = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, > 0xdeadbeef., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, > 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, > 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, > 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.." > > - set vector_register2_vr "uint128 = > 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., > v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 > = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., > v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, > 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.." > + set vector_register2_vr ".uint128 = > 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0xdeadbeef, > 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v4_int32 = .0xdeadbeef, > 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, > 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, > 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, > 0xef, 0xbe, 0xad, 0xde.." > > - set vector_register3 ".uint128 = 0x1000000010000000100000001, > v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = > .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, > 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, > 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.." > + set vector_register3 ".float128 = 0x1000000010000000100000001, > uint128 = 0x1000000010000000100000001, v2_double = .0x100000001, > 0x100000001., v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, > 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., > v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, > 0x0, 0x1, 0x0, 0x0, 0x0.." > > - set vector_register3_vr ".uint128 = 0x1000000010000000100000001, > v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., > v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, > 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, > 0x0.." > + set vector_register3_vr ".uint128 = 0x1000000010000000100000001, > v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1., > v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, > 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, > 0x0.." > } > > set float_register ".raw 0xdeadbeefdeadbeef." > @@ -93,12 +93,13 @@ set float_register ".raw 0xdeadbeefdeadbeef." > # after updates to F*. > # Since dl_main uses some VS* registers, and per inspection their > values are > # no longer zero when our test reaches main(), we need to explicitly > -# initialize the doubleword1 portions before we run our tests > against > -# values currently in those registers. > +# initialize the VS* registers before we run our tests against the > values > +# currently in those registers. > > -# 0: Initialize the (doubleword 1) portion of the VS0-VS31 > registers. > +# 0: Initialize the (doubleword 0 and 1) portion of the VS0-VS31 > registers. > for {set i 0} {$i < 32} {incr i 1} { > gdb_test_no_output "set \$vs$i.v2_double\[0\] = 0" > + gdb_test_no_output "set \$vs$i.v2_double\[1\] = 0" > } > > # 1: Set F0~F31 registers and check if it reflects on VS0~VS31.