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References: <20100304180219.GA10826@intel.com> <20100304180408.GA10869@intel.com>  	<20100304180748.GC10869@intel.com> <20100304180901.GD10869@intel.com>
From: Hui Zhu <teawater@gmail.com>
Date: Fri, 05 Mar 2010 03:20:00 -0000
Message-ID: <daef60381003041919j18d135e7g37471e3419374056@mail.gmail.com>
Subject: Re: PATCH: 5/6: Add AVX support (i387 changes)
To: "H.J. Lu" <hjl.tools@gmail.com>
Cc: GDB <gdb-patches@sourceware.org>
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-#define I387_XMM0_REGNUM(tdep) (I387_ST0_REGNUM (tdep) + 16)
+#define I387_VECTOR0_REGNUM(tdep) (I387_ST0_REGNUM (tdep) + 16)

We need this name change?

Thanks,
Hui

On Fri, Mar 5, 2010 at 02:09, H.J. Lu <hongjiu.lu@intel.com> wrote:
> Hi,
>
> Here are i387 changes to support AVX. =A0OK to install?
>
> Thanks.
>
>
> H.J.
> ---
> 2010-03-03 =A0H.J. Lu =A0<hongjiu.lu@intel.com>
>
> =A0 =A0 =A0 =A0* i387-tdep.c: Include "i386-xstate.h".
> =A0 =A0 =A0 =A0(i387_supply_fsave): Replace I387_XMM0_REGNUM with
> =A0 =A0 =A0 =A0I387_VECTOR0_REGNUM.
> =A0 =A0 =A0 =A0(i387_collect_fsave): Likewise.
> =A0 =A0 =A0 =A0(i387_supply_fxsave): Replace I387_XMM0_REGNUM with
> =A0 =A0 =A0 =A0I387_VECTOR0_REGNUM. =A0Replace num_xmm_regs with num_vect=
or_regs.
> =A0 =A0 =A0 =A0Check tdep->xcr0 for AVX.
> =A0 =A0 =A0 =A0(i387_collect_fxsave): Likewise.
> =A0 =A0 =A0 =A0(xsave_sse_offset): New.
> =A0 =A0 =A0 =A0(XSAVE_XSTATE_BV_ADDR): Likewise.
> =A0 =A0 =A0 =A0(XSAVE_SSE_ADDR): Likewise.
> =A0 =A0 =A0 =A0(xsave_avxh_offset): Likewise.
> =A0 =A0 =A0 =A0(XSAVE_AVXH_ADDR): Likewise.
> =A0 =A0 =A0 =A0(i387_supply_xsave): Likewise.
> =A0 =A0 =A0 =A0(i387_collect_xsave): Likewise.
>
> =A0 =A0 =A0 =A0* i387-tdep.h (I387_NUM_XMM_REGS): Renamed to ...
> =A0 =A0 =A0 =A0(I387_NUM_VECTOR_REGS): This.
> =A0 =A0 =A0 =A0(I387_XMM0_REGNUM): Renamed to ...
> =A0 =A0 =A0 =A0(I387_VECTOR0_REGNUM): This.
> =A0 =A0 =A0 =A0(I387_MXCSR_REGNUM): Updated.
> =A0 =A0 =A0 =A0(i387_supply_xsave): New.
> =A0 =A0 =A0 =A0(i387_collect_xsave): Likewise.
>
> diff --git a/gdb/i387-tdep.c b/gdb/i387-tdep.c
> index 3fb5b56..1f4547d 100644
> --- a/gdb/i387-tdep.c
> +++ b/gdb/i387-tdep.c
> @@ -34,6 +34,7 @@
>
> =A0#include "i386-tdep.h"
> =A0#include "i387-tdep.h"
> +#include "i386-xstate.h"
>
> =A0/* Print the floating point number specified by RAW. =A0*/
>
> @@ -398,7 +399,7 @@ i387_supply_fsave (struct regcache *regcache, int reg=
num, const void *fsave)
>
> =A0 gdb_assert (tdep->st0_regnum >=3D I386_ST0_REGNUM);
>
> - =A0for (i =3D I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
> + =A0for (i =3D I387_ST0_REGNUM (tdep); i < I387_VECTOR0_REGNUM (tdep); i=
++)
> =A0 =A0 if (regnum =3D=3D -1 || regnum =3D=3D i)
> =A0 =A0 =A0 {
> =A0 =A0 =A0 =A0if (fsave =3D=3D NULL)
> @@ -425,7 +426,7 @@ i387_supply_fsave (struct regcache *regcache, int reg=
num, const void *fsave)
> =A0 =A0 =A0 }
>
> =A0 /* Provide dummy values for the SSE registers. =A0*/
> - =A0for (i =3D I387_XMM0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i+=
+)
> + =A0for (i =3D I387_VECTOR0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep);=
 i++)
> =A0 =A0 if (regnum =3D=3D -1 || regnum =3D=3D i)
> =A0 =A0 =A0 regcache_raw_supply (regcache, i, NULL);
> =A0 if (regnum =3D=3D -1 || regnum =3D=3D I387_MXCSR_REGNUM (tdep))
> @@ -451,7 +452,7 @@ i387_collect_fsave (const struct regcache *regcache, =
int regnum, void *fsave)
>
> =A0 gdb_assert (tdep->st0_regnum >=3D I386_ST0_REGNUM);
>
> - =A0for (i =3D I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
> + =A0for (i =3D I387_ST0_REGNUM (tdep); i < I387_VECTOR0_REGNUM (tdep); i=
++)
> =A0 =A0 if (regnum =3D=3D -1 || regnum =3D=3D i)
> =A0 =A0 =A0 {
> =A0 =A0 =A0 =A0/* Most of the FPU control registers occupy only 16 bits in
> @@ -541,9 +542,11 @@ i387_supply_fxsave (struct regcache *regcache, int r=
egnum, const void *fxsave)
> =A0 struct gdbarch_tdep *tdep =3D gdbarch_tdep (get_regcache_arch (regcac=
he));
> =A0 const gdb_byte *regs =3D fxsave;
> =A0 int i;
> + =A0gdb_byte raw[I386_MAX_REGISTER_SIZE];
> + =A0const gdb_byte *xmm;
>
> =A0 gdb_assert (tdep->st0_regnum >=3D I386_ST0_REGNUM);
> - =A0gdb_assert (tdep->num_xmm_regs > 0);
> + =A0gdb_assert (tdep->num_vector_regs > 0);
>
> =A0 for (i =3D I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
> =A0 =A0 if (regnum =3D=3D -1 || regnum =3D=3D i)
> @@ -556,7 +559,7 @@ i387_supply_fxsave (struct regcache *regcache, int re=
gnum, const void *fxsave)
>
> =A0 =A0 =A0 =A0/* Most of the FPU control registers occupy only 16 bits in
> =A0 =A0 =A0 =A0 =A0 the fxsave area. =A0Give those a special treatment. =
=A0*/
> - =A0 =A0 =A0 if (i >=3D I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM=
 (tdep)
> + =A0 =A0 =A0 if (i >=3D I387_FCTRL_REGNUM (tdep) && i < I387_VECTOR0_REG=
NUM (tdep)
> =A0 =A0 =A0 =A0 =A0 =A0&& i !=3D I387_FIOFF_REGNUM (tdep) && i !=3D I387_=
FOOFF_REGNUM (tdep))
> =A0 =A0 =A0 =A0 =A0{
> =A0 =A0 =A0 =A0 =A0 =A0gdb_byte val[4];
> @@ -600,7 +603,17 @@ i387_supply_fxsave (struct regcache *regcache, int r=
egnum, const void *fxsave)
> =A0 =A0 =A0 =A0 =A0 =A0regcache_raw_supply (regcache, i, val);
> =A0 =A0 =A0 =A0 =A0}
> =A0 =A0 =A0 =A0else
> - =A0 =A0 =A0 =A0 regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, re=
gs, i));
> + =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 if ((tdep->xcr0 & I386_XSTATE_AVX_MASK)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D=3D I386_XSTATE_AVX_MASK)
> + =A0 =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 memcpy (raw, FXSAVE_ADDR (tdep, regs, i), 1=
6);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 xmm =3D raw;
> + =A0 =A0 =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0 =A0 =A0 else
> + =A0 =A0 =A0 =A0 =A0 =A0 xmm =3D FXSAVE_ADDR (tdep, regs, i);
> + =A0 =A0 =A0 =A0 =A0 regcache_raw_supply (regcache, i, xmm);
> + =A0 =A0 =A0 =A0 }
> =A0 =A0 =A0 }
>
> =A0 if (regnum =3D=3D I387_MXCSR_REGNUM (tdep) || regnum =3D=3D -1)
> @@ -624,16 +637,18 @@ i387_collect_fxsave (const struct regcache *regcach=
e, int regnum, void *fxsave)
> =A0 struct gdbarch_tdep *tdep =3D gdbarch_tdep (get_regcache_arch (regcac=
he));
> =A0 gdb_byte *regs =3D fxsave;
> =A0 int i;
> + =A0gdb_byte raw[I386_MAX_REGISTER_SIZE];
> + =A0gdb_byte *xmm;
>
> =A0 gdb_assert (tdep->st0_regnum >=3D I386_ST0_REGNUM);
> - =A0gdb_assert (tdep->num_xmm_regs > 0);
> + =A0gdb_assert (tdep->num_vector_regs > 0);
>
> =A0 for (i =3D I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
> =A0 =A0 if (regnum =3D=3D -1 || regnum =3D=3D i)
> =A0 =A0 =A0 {
> =A0 =A0 =A0 =A0/* Most of the FPU control registers occupy only 16 bits in
> =A0 =A0 =A0 =A0 =A0 =A0the fxsave area. =A0Give those a special treatment=
. =A0*/
> - =A0 =A0 =A0 if (i >=3D I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM=
 (tdep)
> + =A0 =A0 =A0 if (i >=3D I387_FCTRL_REGNUM (tdep) && i < I387_VECTOR0_REG=
NUM (tdep)
> =A0 =A0 =A0 =A0 =A0 =A0&& i !=3D I387_FIOFF_REGNUM (tdep) && i !=3D I387_=
FOOFF_REGNUM (tdep))
> =A0 =A0 =A0 =A0 =A0{
> =A0 =A0 =A0 =A0 =A0 =A0gdb_byte buf[4];
> @@ -669,7 +684,465 @@ i387_collect_fxsave (const struct regcache *regcach=
e, int regnum, void *fxsave)
> =A0 =A0 =A0 =A0 =A0 =A0memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2);
> =A0 =A0 =A0 =A0 =A0}
> =A0 =A0 =A0 =A0else
> + =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 if ((tdep->xcr0 & I386_XSTATE_AVX_MASK)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D=3D I386_XSTATE_AVX_MASK)
> + =A0 =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 memcpy (raw, FXSAVE_ADDR (tdep, regs, i), 1=
6);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 xmm =3D raw;
> + =A0 =A0 =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0 =A0 =A0 else
> + =A0 =A0 =A0 =A0 =A0 =A0 xmm =3D FXSAVE_ADDR (tdep, regs, i);
> + =A0 =A0 =A0 =A0 =A0 regcache_raw_collect (regcache, i, xmm);
> + =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0}
> +
> + =A0if (regnum =3D=3D I387_MXCSR_REGNUM (tdep) || regnum =3D=3D -1)
> + =A0 =A0regcache_raw_collect (regcache, I387_MXCSR_REGNUM (tdep),
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FXSAVE_MXCSR_ADDR (regs=
));
> +}
> +
> +/* At xsave_sse_offset[REGNUM] you'll find the offset to the location in
> + =A0 the SSE register data structure used by the "xsave" instruction whe=
re
> + =A0 GDB register REGNUM is stored. =A0*/
> +
> +static int xsave_sse_offset[] =3D
> +{
> + =A0160 + 0 * 16, =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* %xmm0 through ... =
=A0*/
> + =A0160 + 1 * 16,
> + =A0160 + 2 * 16,
> + =A0160 + 3 * 16,
> + =A0160 + 4 * 16,
> + =A0160 + 5 * 16,
> + =A0160 + 6 * 16,
> + =A0160 + 7 * 16,
> + =A0160 + 8 * 16,
> + =A0160 + 9 * 16,
> + =A0160 + 10 * 16,
> + =A0160 + 11 * 16,
> + =A0160 + 12 * 16,
> + =A0160 + 13 * 16,
> + =A0160 + 14 * 16,
> + =A0160 + 15 * 16, =A0 =A0 =A0 /* ... %xmm15 (128 bits each). =A0*/
> +};
> +
> +/* `xstate_bv' is at byte offset 512. =A0*/
> +#define XSAVE_XSTATE_BV_ADDR(xsave) (xsave + 512)
> +
> +#define XSAVE_SSE_ADDR(tdep, xsave, regnum) \
> + =A0(xsave + xsave_sse_offset[regnum - I387_VECTOR0_REGNUM (tdep)])
> +
> +/* At xsave_avxh_offset[REGNUM] you'll find the offset to the location in
> + =A0 the upper 128bit of AVX register data structure used by the "xsave"
> + =A0 instruction where GDB register REGNUM is stored. =A0*/
> +
> +static int xsave_avxh_offset[] =3D
> +{
> + =A0576 + 0 * 16, =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* Upper 128bit of %ymm=
0 through ... =A0*/
> + =A0576 + 1 * 16,
> + =A0576 + 2 * 16,
> + =A0576 + 3 * 16,
> + =A0576 + 4 * 16,
> + =A0576 + 5 * 16,
> + =A0576 + 6 * 16,
> + =A0576 + 7 * 16,
> + =A0576 + 8 * 16,
> + =A0576 + 9 * 16,
> + =A0576 + 10 * 16,
> + =A0576 + 11 * 16,
> + =A0576 + 12 * 16,
> + =A0576 + 13 * 16,
> + =A0576 + 14 * 16,
> + =A0576 + 15 * 16, =A0 =A0 =A0 /* Upper 128bit of ... %ymm15 (128 bits e=
ach). =A0*/
> +};
> +
> +#define XSAVE_AVXH_ADDR(tdep, xsave, regnum) \
> + =A0(xsave + xsave_avxh_offset[regnum - I387_VECTOR0_REGNUM (tdep)])
> +
> +/* Similar to i387_supply_fxsave, but use XSAVE extended state. =A0*/
> +
> +void
> +i387_supply_xsave (struct regcache *regcache, int regnum,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0const void *xsave)
> +{
> + =A0struct gdbarch_tdep *tdep =3D gdbarch_tdep (get_regcache_arch (regca=
che));
> + =A0const gdb_byte *regs =3D xsave;
> + =A0int i;
> + =A0unsigned int clear_bv;
> + =A0gdb_byte raw[I386_MAX_REGISTER_SIZE];
> + =A0const gdb_byte *p;
> +
> + =A0gdb_assert (tdep->st0_regnum >=3D I386_ST0_REGNUM);
> + =A0gdb_assert (tdep->num_vector_regs > 0);
> +
> + =A0if (regs !=3D NULL
> + =A0 =A0 =A0&& (regnum =3D=3D -1
> + =A0 =A0 =A0 =A0 || (regnum >=3D I387_VECTOR0_REGNUM(tdep)
> + =A0 =A0 =A0 =A0 =A0 =A0 && regnum < I387_MXCSR_REGNUM (tdep))
> + =A0 =A0 =A0 =A0 || (regnum >=3D I387_ST0_REGNUM (tdep)
> + =A0 =A0 =A0 =A0 =A0 =A0 && regnum < I387_FCTRL_REGNUM (tdep))))
> + =A0 =A0{
> + =A0 =A0 =A0/* Get `xstat_bv'. =A0*/
> + =A0 =A0 =A0const gdb_byte *xstate_bv_p =3D XSAVE_XSTATE_BV_ADDR (regs);
> +
> + =A0 =A0 =A0/* The supported bits in `xstat_bv' are 1 byte. =A0Clear par=
t in
> + =A0 =A0 =A0 =A0vector registers if its bit in xstat_bv is zero. =A0*/
> + =A0 =A0 =A0clear_bv =3D (~(*xstate_bv_p)) & tdep->xcr0;
> + =A0 =A0}
> + =A0else
> + =A0 =A0clear_bv =3D 0;
> +
> + =A0for (i =3D I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
> + =A0 =A0if (regnum =3D=3D -1 || regnum =3D=3D i)
> + =A0 =A0 =A0{
> + =A0 =A0 =A0 if (regs =3D=3D NULL)
> + =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 regcache_raw_supply (regcache, i, NULL);
> + =A0 =A0 =A0 =A0 =A0 continue;
> + =A0 =A0 =A0 =A0 }
> +
> + =A0 =A0 =A0 /* Most of the FPU control registers occupy only 16 bits in
> + =A0 =A0 =A0 =A0 =A0the xsave extended state. =A0Give those a special tr=
eatment. =A0*/
> + =A0 =A0 =A0 if (i >=3D I387_FCTRL_REGNUM (tdep)
> + =A0 =A0 =A0 =A0 =A0 && i < I387_VECTOR0_REGNUM (tdep)
> + =A0 =A0 =A0 =A0 =A0 && i !=3D I387_FIOFF_REGNUM (tdep)
> + =A0 =A0 =A0 =A0 =A0 && i !=3D I387_FOOFF_REGNUM (tdep))
> + =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 gdb_byte val[4];
> +
> + =A0 =A0 =A0 =A0 =A0 memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2);
> + =A0 =A0 =A0 =A0 =A0 val[2] =3D val[3] =3D 0;
> + =A0 =A0 =A0 =A0 =A0 if (i =3D=3D I387_FOP_REGNUM (tdep))
> + =A0 =A0 =A0 =A0 =A0 =A0 val[1] &=3D ((1 << 3) - 1);
> + =A0 =A0 =A0 =A0 =A0 else if (i=3D=3D I387_FTAG_REGNUM (tdep))
> + =A0 =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* The fxsave area contains a simplified ve=
rsion of
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0the tag word. =A0We have to look at =
the actual 80-bit
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0FP data to recreate the traditional =
i387 tag word. =A0*/
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 unsigned long ftag =3D 0;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 int fpreg;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 int top;
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 top =3D ((FXSAVE_ADDR (tdep, regs,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
I387_FSTAT_REGNUM (tdep)))[1] >> 3);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 top &=3D 0x7;
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 for (fpreg =3D 7; fpreg >=3D 0; fpreg--)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 int tag;
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (val[0] & (1 << fpreg))
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 int regnum =3D (fpreg + 8 -=
 top) % 8
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0+ I387_ST0_REGNUM (tdep);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 tag =3D i387_tag (FXSAVE_AD=
DR (tdep, regs, regnum));
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 tag =3D 3; =A0 =A0 =A0 =A0 =A0/=
* Empty */
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ftag |=3D tag << (2 * fpreg);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 val[0] =3D ftag & 0xff;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 val[1] =3D (ftag >> 8) & 0xff;
> + =A0 =A0 =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0 =A0 =A0 regcache_raw_supply (regcache, i, val);
> + =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0 else if (i < I387_VECTOR0_REGNUM (tdep))
> + =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 if (i < I387_FCTRL_REGNUM (tdep)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 && (clear_bv & bit_I386_XSTATE_X87))
> + =A0 =A0 =A0 =A0 =A0 =A0 p =3D NULL;
> + =A0 =A0 =A0 =A0 =A0 else
> + =A0 =A0 =A0 =A0 =A0 =A0 p =3D FXSAVE_ADDR (tdep, regs, i);
> + =A0 =A0 =A0 =A0 =A0 regcache_raw_supply (regcache, i, p);
> + =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0 else
> + =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 if ((tdep->xcr0 & I386_XSTATE_AVX_MASK)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D=3D I386_XSTATE_AVX_MASK)
> + =A0 =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 if ((clear_bv & (bit_I386_XSTATE_SSE | bit_=
I386_XSTATE_AVX))
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D=3D (bit_I386_XSTATE_SSE | bit_I=
386_XSTATE_AVX))
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 p =3D NULL;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 else
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 p =3D raw;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if ((clear_bv & bit_I386_XSTATE_SSE=
))
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 memset (raw, 0, 16);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 memcpy (raw, XSAVE_SSE_ADDR (td=
ep, regs, i), 16);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if ((clear_bv & bit_I386_XSTATE_AVX=
))
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 memset (raw + 16, 0, 16);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 memcpy (raw + 16, XSAVE_AVXH_AD=
DR (tdep, regs, i),
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 16);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0 =A0 =A0 else
> + =A0 =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 if ((clear_bv & bit_I386_XSTATE_SSE))
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 p =3D NULL;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 else
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 p =3D XSAVE_SSE_ADDR (tdep, regs, i);
> + =A0 =A0 =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0 =A0 =A0 regcache_raw_supply (regcache, i, p);
> + =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0}
> +
> + =A0if (regnum =3D=3D I387_MXCSR_REGNUM (tdep) || regnum =3D=3D -1)
> + =A0 =A0{
> + =A0 =A0 =A0if (regs =3D=3D NULL)
> + =A0 =A0 =A0 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), NU=
LL);
> + =A0 =A0 =A0else
> + =A0 =A0 =A0 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep),
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0FXSAVE_MXCSR_ADD=
R (regs));
> + =A0 =A0}
> +}
> +
> +/* Similar to i387_collect_fxsave, but use XSAVE extended state. =A0*/
> +
> +void
> +i387_collect_xsave (const struct regcache *regcache, int regnum,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 void *xsave, int gcore)
> +{
> + =A0struct gdbarch_tdep *tdep =3D gdbarch_tdep (get_regcache_arch (regca=
che));
> + =A0gdb_byte *regs =3D xsave;
> + =A0int i;
> + =A0gdb_byte raw[I386_MAX_REGISTER_SIZE];
> +
> + =A0gdb_assert (tdep->st0_regnum >=3D I386_ST0_REGNUM);
> + =A0gdb_assert (tdep->num_vector_regs > 0);
> +
> + =A0if (gcore)
> + =A0 =A0{
> + =A0 =A0 =A0/* Update XCR0 and `xstate_bv' with XCR0 for gcore. =A0*/
> + =A0 =A0 =A0if (tdep->xsave_xcr0_offset !=3D -1)
> + =A0 =A0 =A0 memcpy (regs + tdep->xsave_xcr0_offset, &tdep->xcr0, 8);
> + =A0 =A0 =A0memcpy (XSAVE_XSTATE_BV_ADDR (regs), &tdep->xcr0, 8);
> + =A0 =A0}
> + =A0else
> + =A0 =A0{
> + =A0 =A0 =A0enum
> + =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 none =3D 0x0,
> + =A0 =A0 =A0 =A0 check =3D 0x1,
> + =A0 =A0 =A0 =A0 x87 =3D 0x2 | check,
> + =A0 =A0 =A0 =A0 vector =3D 0x4 | check,
> + =A0 =A0 =A0 =A0 all =3D 0x8 | check
> + =A0 =A0 =A0 } regclass;
> +
> + =A0 =A0 =A0if (regnum =3D=3D -1)
> + =A0 =A0 =A0 regclass =3D all;
> + =A0 =A0 =A0else if (regnum >=3D I387_VECTOR0_REGNUM(tdep)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0&& regnum < I387_MXCSR_REGNUM (tdep))
> + =A0 =A0 =A0 regclass =3D vector;
> + =A0 =A0 =A0else if (regnum >=3D I387_ST0_REGNUM (tdep)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0&& regnum < I387_FCTRL_REGNUM (tdep))
> + =A0 =A0 =A0 regclass =3D x87;
> + =A0 =A0 =A0else
> + =A0 =A0 =A0 regclass =3D none;
> +
> + =A0 =A0 =A0if ((regclass & check))
> + =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 gdb_byte *xstate_bv_p =3D XSAVE_XSTATE_BV_ADDR (regs);
> + =A0 =A0 =A0 =A0 int num_vector_regs;
> + =A0 =A0 =A0 =A0 unsigned int xstate_bv =3D 0;
> + =A0 =A0 =A0 =A0 /* The supported bits in `xstat_bv' are 1 byte. */
> + =A0 =A0 =A0 =A0 unsigned int clear_bv =3D (~(*xstate_bv_p)) & tdep->xcr=
0;
> +
> + =A0 =A0 =A0 =A0 /* Clear part in vector registers if its bit in xstat_b=
v is
> + =A0 =A0 =A0 =A0 =A0 =A0zero. =A0*/
> + =A0 =A0 =A0 =A0 if (clear_bv)
> + =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 i =3D I387_VECTOR0_REGNUM (tdep);
> + =A0 =A0 =A0 =A0 =A0 =A0 num_vector_regs =3D I387_NUM_VECTOR_REGS(tdep);
> + =A0 =A0 =A0 =A0 =A0 =A0 for (; num_vector_regs; num_vector_regs--, i++)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if ((clear_bv & bit_I386_XSTATE_AVX))
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 memset (XSAVE_AVXH_ADDR (tdep, regs=
, i), 0, 16);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if ((clear_bv & bit_I386_XSTATE_SSE))
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 memset (XSAVE_SSE_ADDR (tdep, regs,=
 i), 0, 16);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 }
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 if ((clear_bv & bit_I386_XSTATE_X87))
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 for (i =3D I387_ST0_REGNUM (tdep);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0i < I387_FCTRL_REGNUM (tdep); i+=
+)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 memset (FXSAVE_ADDR (tdep, regs, i), 0,=
 10);
> + =A0 =A0 =A0 =A0 =A0 }
> +
> + =A0 =A0 =A0 =A0 if (regclass =3D=3D all)
> + =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 i =3D I387_VECTOR0_REGNUM (tdep);
> + =A0 =A0 =A0 =A0 =A0 =A0 num_vector_regs =3D I387_NUM_VECTOR_REGS(tdep);
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 if ((tdep->xcr0 & I386_XSTATE_AVX_MASK)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D=3D I386_XSTATE_AVX_MASK)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* Check if any AVX registers are chang=
ed. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 for (; num_vector_regs; num_vector_regs=
--, i++)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 regcache_raw_read ((struct regc=
ache *) regcache,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0i, raw);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (memcmp (raw + 16,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 XSAVE_A=
VXH_ADDR (tdep, regs, i), 16))
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 xstate_bv |=3D bit_I386_XST=
ATE_AVX;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (memcmp (raw, XSAVE_SSE_ADDR=
 (tdep, regs, i), 16))
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 xstate_bv |=3D bit_I386_XST=
ATE_SSE;
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (xstate_bv
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D=3D (bit_I386_XSTATE=
_AVX | bit_I386_XSTATE_SSE))
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 break;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0 =A0 =A0 =A0 else
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* Check if any SSE registers are chang=
ed. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 for (; num_vector_regs; num_vector_regs=
--, i++)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 regcache_raw_read ((struct regc=
ache *) regcache,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0i, raw);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (memcmp (raw, XSAVE_SSE_ADDR=
 (tdep, regs, i), 16))
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 xstate_bv |=3D bit_I386=
_XSTATE_SSE;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 break;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 }
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 /* Check if any X87 registers are changed. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 for (i =3D I387_ST0_REGNUM (tdep);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0i < I387_FCTRL_REGNUM (tdep); i++)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 regcache_raw_read ((struct regcache *) =
regcache, i, raw);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (memcmp (raw, FXSAVE_ADDR (tdep, reg=
s, i), 10))
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 xstate_bv |=3D bit_I386_XSTATE_=
X87;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 break;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0 =A0 else
> + =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 /* Check if REGNUM is changed. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 regcache_raw_read ((struct regcache *) regcache=
, regnum, raw);
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 if (regclass =3D=3D x87)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* This is an x87 register. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (memcmp (raw, FXSAVE_ADDR (tdep, reg=
s, regnum), 10))
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 xstate_bv |=3D bit_I386_XSTATE_X87;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0 =A0 =A0 =A0 else
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* This is an SSE/AVX register. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if ((tdep->xcr0 & I386_XSTATE_AVX_MASK)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D=3D I386_XSTATE_AVX_MASK)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (memcmp (raw + 16,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 XSAVE_A=
VXH_ADDR (tdep, regs, regnum), 16))
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 xstate_bv |=3D bit_I386_XST=
ATE_AVX;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 }
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (memcmp (raw, XSAVE_SSE_ADDR (tdep, =
regs, regnum), 16))
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 xstate_bv |=3D bit_I386_XSTATE_SSE;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0 =A0 =A0 }
> +
> + =A0 =A0 =A0 =A0 /* Update the corresponding bits in `xstate_bv' if any =
SSE/AVX
> + =A0 =A0 =A0 =A0 =A0 =A0registers are changed. =A0*/
> + =A0 =A0 =A0 =A0 if (xstate_bv)
> + =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 /* The supported bits in `xstat_bv' are 1 byte.=
 =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 *xstate_bv_p |=3D (gdb_byte) xstate_bv;
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 /* Update REGNUM and return. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 if (regclass !=3D all)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (regclass =3D=3D x87)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* x87 register. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 memcpy (FXSAVE_ADDR (tdep, regs=
, regnum), raw, 10);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* SSE/AVX register. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if ((xstate_bv & bit_I386_XSTAT=
E_AVX))
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 memcpy (XSAVE_AVXH_ADDR (td=
ep, regs, regnum),
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 raw + 16, 1=
6);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if ((xstate_bv & bit_I386_XSTAT=
E_SSE))
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 memcpy (XSAVE_SSE_ADDR (tde=
p, regs, regnum), raw, 16);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 return;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0 =A0 else
> + =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 /* Return if REGNUM isn't changed. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 if (regclass !=3D all)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 return;
> + =A0 =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0 }
> + =A0 =A0}
> +
> + =A0for (i =3D I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
> + =A0 =A0if (regnum =3D=3D -1 || regnum =3D=3D i)
> + =A0 =A0 =A0{
> + =A0 =A0 =A0 /* Most of the FPU control registers occupy only 16 bits in
> + =A0 =A0 =A0 =A0 =A0the xsave extended state. =A0Give those a special tr=
eatment. =A0*/
> + =A0 =A0 =A0 if (i >=3D I387_FCTRL_REGNUM (tdep)
> + =A0 =A0 =A0 =A0 =A0 && i < I387_VECTOR0_REGNUM (tdep)
> + =A0 =A0 =A0 =A0 =A0 && i !=3D I387_FIOFF_REGNUM (tdep)
> + =A0 =A0 =A0 =A0 =A0 && i !=3D I387_FOOFF_REGNUM (tdep))
> + =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 gdb_byte buf[4];
> +
> + =A0 =A0 =A0 =A0 =A0 regcache_raw_collect (regcache, i, buf);
> +
> + =A0 =A0 =A0 =A0 =A0 if (i =3D=3D I387_FOP_REGNUM (tdep))
> + =A0 =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* The opcode occupies only 11 bits. =A0Mak=
e sure we
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 don't touch the other bits. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 buf[1] &=3D ((1 << 3) - 1);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 buf[1] |=3D ((FXSAVE_ADDR (tdep, regs, i))[=
1] & ~((1 << 3) - 1));
> + =A0 =A0 =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0 =A0 =A0 else if (i =3D=3D I387_FTAG_REGNUM (tdep))
> + =A0 =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* Converting back is much easier. =A0*/
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 unsigned short ftag;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 int fpreg;
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 ftag =3D (buf[1] << 8) | buf[0];
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 buf[0] =3D 0;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 buf[1] =3D 0;
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 for (fpreg =3D 7; fpreg >=3D 0; fpreg--)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 int tag =3D (ftag >> (fpreg * 2)) &=
 3;
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (tag !=3D 3)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 buf[0] |=3D (1 << fpreg);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0 =A0 =A0 memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2);
> + =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0 else if (i < I387_VECTOR0_REGNUM (tdep))
> =A0 =A0 =A0 =A0 =A0regcache_raw_collect (regcache, i, FXSAVE_ADDR (tdep, =
regs, i));
> + =A0 =A0 =A0 else
> + =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 if ((tdep->xcr0 & I386_XSTATE_AVX_MASK)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D=3D I386_XSTATE_AVX_MASK)
> + =A0 =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 regcache_raw_collect (regcache, i, raw);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 memcpy (XSAVE_SSE_ADDR (tdep, regs, i), raw=
, 16);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 memcpy (XSAVE_AVXH_ADDR (tdep, regs, i),
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 raw + 16, 16);
> + =A0 =A0 =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0 =A0 =A0 else
> + =A0 =A0 =A0 =A0 =A0 =A0 regcache_raw_collect (regcache, i,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 XSA=
VE_SSE_ADDR (tdep, regs, i));
> + =A0 =A0 =A0 =A0 }
> =A0 =A0 =A0 }
>
> =A0 if (regnum =3D=3D I387_MXCSR_REGNUM (tdep) || regnum =3D=3D -1)
> diff --git a/gdb/i387-tdep.h b/gdb/i387-tdep.h
> index 645eb91..f867a1f 100644
> --- a/gdb/i387-tdep.h
> +++ b/gdb/i387-tdep.h
> @@ -31,7 +31,7 @@ struct ui_file;
> =A0#define I387_NUM_REGS =A016
>
> =A0#define I387_ST0_REGNUM(tdep) ((tdep)->st0_regnum)
> -#define I387_NUM_XMM_REGS(tdep) ((tdep)->num_xmm_regs)
> +#define I387_NUM_VECTOR_REGS(tdep) ((tdep)->num_vector_regs)
> =A0#define I387_MM0_REGNUM(tdep) ((tdep)->mm0_regnum)
>
> =A0#define I387_FCTRL_REGNUM(tdep) (I387_ST0_REGNUM (tdep) + 8)
> @@ -42,9 +42,9 @@ struct ui_file;
> =A0#define I387_FOSEG_REGNUM(tdep) (I387_FCTRL_REGNUM (tdep) + 5)
> =A0#define I387_FOOFF_REGNUM(tdep) (I387_FCTRL_REGNUM (tdep) + 6)
> =A0#define I387_FOP_REGNUM(tdep) (I387_FCTRL_REGNUM (tdep) + 7)
> -#define I387_XMM0_REGNUM(tdep) (I387_ST0_REGNUM (tdep) + 16)
> +#define I387_VECTOR0_REGNUM(tdep) (I387_ST0_REGNUM (tdep) + 16)
> =A0#define I387_MXCSR_REGNUM(tdep) \
> - =A0(I387_XMM0_REGNUM (tdep) + I387_NUM_XMM_REGS (tdep))
> + =A0(I387_VECTOR0_REGNUM (tdep) + I387_NUM_VECTOR_REGS (tdep))
>
> =A0/* Print out the i387 floating point state. =A0*/
>
> @@ -99,6 +99,11 @@ extern void i387_collect_fsave (const struct regcache =
*regcache, int regnum,
> =A0extern void i387_supply_fxsave (struct regcache *regcache, int regnum,
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0const void=
 *fxsave);
>
> +/* Similar to i387_supply_fxsave, but use XSAVE extended state. =A0*/
> +
> +extern void i387_supply_xsave (struct regcache *regcache, int regnum,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0const void *=
xsave);
> +
> =A0/* Fill register REGNUM (if it is a floating-point or SSE register) in
> =A0 =A0*FXSAVE with the value from REGCACHE. =A0If REGNUM is -1, do this =
for
> =A0 =A0all registers. =A0This function doesn't touch any of the reserved
> @@ -107,6 +112,11 @@ extern void i387_supply_fxsave (struct regcache *reg=
cache, int regnum,
> =A0extern void i387_collect_fxsave (const struct regcache *regcache, int =
regnum,
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 void *fxs=
ave);
>
> +/* Similar to i387_collect_fxsave, but use XSAVE extended state. =A0*/
> +
> +extern void i387_collect_xsave (const struct regcache *regcache,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 int regnum,=
 void *xsave, int gcore);
> +
> =A0/* Prepare the FPU stack in REGCACHE for a function return. =A0*/
>
> =A0extern void i387_return_value (struct gdbarch *gdbarch,
>