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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Feb 2023 13:33:20.5582 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: be7d0b6b-3180-4e15-6182-08db15a28787 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT020.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS4PR08MB7829 X-Spam-Status: No, score=-6.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,KAM_DMARC_NONE,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 2/23/23 11:04, Eli Zaretskii wrote: >> From: Luis Machado >> CC: >> Date: Thu, 23 Feb 2023 09:52:44 +0000 >> >> Similar to the arm target documentation situation, the documentation of the >> XML features for AArch64 targets is rather brief. I have received the same >> feedback that what gdb carries in the documentation is quite unclear from the >> perspective of what debugging servers should define in the XML features, how and >> what the outcome is in gdb. >> >> This patch attempts to clarify a bit more what all the possible features are. > > Thanks. > >> The @samp{org.gnu.gdb.aarch64.core} feature is required for AArch64 >> -targets. It should contain registers @samp{x0} through @samp{x30}, >> -@samp{sp}, @samp{pc}, and @samp{cpsr}. >> +targets. It must contain the following: >> + >> +@itemize @minus >> +@item >> +@samp{x0} through @samp{x30}, with size of 64-bit. Register @samp{x30} is > > This doesn't say these are registers, please add that. > >> +also known as the link register @samp{lr}. > > The "link register" part should probably be in @dfn, and "@samp{lr}" > should probably be ", or @samp{lr}", as it's an alternative name AFAIU. > >> +@item >> +@samp{pc}, the program counter register. It is 64-bit in size and has a type >> +of @samp{code_ptr}. ^^ > > Two spaces there, please. > >> +The @samp{cpsr} flags type gets updated based on new architectural >> +features. > > "flags type gets updated" sounds awkward and confusing. What did you > mean by that? what is updated? > Some flags/fields are reserved to be used in future extensions of the architecture. For example, suppose bit 26 in 32-bit register is undefined, but then gets defined for a new architecture extension. We need to update the XML to reflect that. >> +@item >> +@samp{v0} through @samp{v31}, the vector registers with size of 128-bit. The > ^^^^^^^ > The dash is redundant there and should be dropped. > >> +@samp{z0} through @samp{z31}, the scalable vector registers. Their sizes are >> +variable and a multiple of 128-bit up to a maximum of 2048-bit. Their type is > > Same here. > >> +@samp{p0} through @samp{p15}, the predicate registers. Their sizes are >> +variable, based on the current vector length, and a multiple of 16-bit. Their > > And here. > >> +@item >> +@samp{ffr}, the First Fault register. It has a variable size based on the >> +current vector length and is a multiple of 16-bit. The type is the same as > > And here. Also, "and is" is ambiguous: you mean the size is a > multiple, but the text can be interpreted as alluding to the register, > not its size. Indeed. I'll fix that and the other comments. Thanks! > > Reviewed-By: Eli Zaretskii