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From: Andrew Burgess <andrew.burgess@embecosm.com>
To: gdb-patches@sourceware.org
Cc: Nelson Chu <nelson.chu@sifive.com>, Jim Wilson <jimw@sifive.com>,
	Tom Tromey <tom@tromey.com>,
	palmer@dabbelt.com, Andrew Burgess <andrew.burgess@embecosm.com>
Subject: [PATCH 8/8] gdb/riscv: Loop over all registers for 'info all-registers'
Date: Tue, 16 Jun 2020 18:14:47 +0100	[thread overview]
Message-ID: <e24e63d67a01916d342eff82ebfae09ebe54a48b.1592327296.git.andrew.burgess@embecosm.com> (raw)
In-Reply-To: <cover.1592327296.git.andrew.burgess@embecosm.com>

Currently the 'info all-registers' command only loops over those
registers that are known to GDB.  Any registers that are unknown, that
is, are mentioned in the target description, but are not something GDB
otherwise knows, will not be displayed.

This feels wrong, so this commit fixes this mistake.  The output of
'info all-registers' now matches 'info registers all'.

gdb/ChangeLog:

	* riscv-tdep.c (riscv_print_registers_info): Loop over all
	registers, not just the known core set of registers.

gdb/testsuite/ChangeLog:

	* gdb.arch/riscv-tdesc-regs.exp: New test cases.
---
 gdb/ChangeLog                               |  5 +++++
 gdb/riscv-tdep.c                            |  2 +-
 gdb/testsuite/ChangeLog                     |  4 ++++
 gdb/testsuite/gdb.arch/riscv-tdesc-regs.exp | 10 +++++++---
 4 files changed, 17 insertions(+), 4 deletions(-)

diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 37ea0ee81a4..0028572d844 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -1071,7 +1071,7 @@ riscv_print_registers_info (struct gdbarch *gdbarch,
       else
 	reggroup = general_reggroup;
 
-      for (regnum = 0; regnum <= RISCV_LAST_REGNUM; ++regnum)
+      for (regnum = 0; regnum < gdbarch_num_cooked_regs (gdbarch); ++regnum)
 	{
 	  /* Zero never changes, so might as well hide by default.  */
 	  if (regnum == RISCV_ZERO_REGNUM && !print_all)
diff --git a/gdb/testsuite/gdb.arch/riscv-tdesc-regs.exp b/gdb/testsuite/gdb.arch/riscv-tdesc-regs.exp
index 9feddbad074..1be32e0e8a1 100644
--- a/gdb/testsuite/gdb.arch/riscv-tdesc-regs.exp
+++ b/gdb/testsuite/gdb.arch/riscv-tdesc-regs.exp
@@ -80,11 +80,15 @@ gdb_test "info registers \$csr0" "Invalid register `csr0'"
 gdb_test "info registers \$dscratch0" "dscratch0\[ \t\]+.*"
 gdb_test "info registers \$dscratch" "dscratch\[ \t\]+.*"
 
-foreach rgroup {all save restore} {
+foreach rgroup {x_all all save restore} {
     # Now use 'info registers all' to see how many times the floating
     # point status registers show up in the output.
     array set reg_counts {}
-    set test "info registers $rgroup"
+    if {$rgroup == "x_all"} {
+	set test "info all-registers"
+    } else {
+	set test "info registers $rgroup"
+    }
     gdb_test_multiple $test $test {
 	-re ".*info registers all\r\n" {
 	    verbose -log "Skip to first register"
@@ -107,7 +111,7 @@ foreach rgroup {all save restore} {
 	    set count 0
 	}
 	if {($reg == "unknown_csr" || $reg == "dscratch") \
-		&& $rgroup != "all"} {
+		&& $rgroup != "all" && $rgroup != "x_all"} {
 	    gdb_assert {$count == 0} \
 		"register $reg not seen in reggroup $rgroup"
 	} else {
-- 
2.25.4


  parent reply	other threads:[~2020-06-16 17:15 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-16 17:14 [PATCH 0/8] RISC-V target description and register handling fixes Andrew Burgess
2020-06-16 17:14 ` [PATCH 1/8] gdb/riscv: Improved register alias name creation Andrew Burgess
2020-06-18 20:36   ` Tom Tromey
2020-06-16 17:14 ` [PATCH 2/8] gdb/riscv: Fix whitespace error Andrew Burgess
2020-06-16 17:14 ` [PATCH 3/8] gdb/riscv: Take CSR names from target description Andrew Burgess
2020-06-16 17:14 ` [PATCH 4/8] gdb/riscv: Remove CSR feature file Andrew Burgess
2020-06-16 17:14 ` [PATCH 5/8] gdb/riscv: Improve support for matching against target descriptions Andrew Burgess
2020-06-16 17:14 ` [PATCH 6/8] gdb: Extend target description processing of unknown registers Andrew Burgess
2020-06-16 17:14 ` [PATCH 7/8] gdb/riscv: Record information about unknown tdesc registers Andrew Burgess
2020-06-16 17:14 ` Andrew Burgess [this message]
2020-06-17  1:31 ` [PATCH 0/8] RISC-V target description and register handling fixes Nelson Chu
2020-06-18 20:45 ` Tom Tromey
2020-06-18 20:54   ` Andrew Burgess

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