[RFA 3/5] Prec: x86 segment register support: target

[RFA 3/5] Prec: x86 segment register support: target

[Hui Zhu]

[-- Attachment #1: Type: text/plain, Size: 230 bytes --]

This patch add a interface to let GDB get segment base message from inferior.

Thanks,
Hui

2010-03-16  Hui Zhu  <teawater@gmail.com>

	* target.c (update_current_target): Add to_get_segment_base.
	* target.h (target_ops): Ditto.

[-- Attachment #2: prec-segment-target.txt --]
[-- Type: text/plain, Size: 943 bytes --]

---
 target.c |    1 +
 target.h |    4 ++++
 2 files changed, 5 insertions(+)

--- a/target.c
+++ b/target.c
@@ -659,6 +659,7 @@ update_current_target (void)
       INHERIT (to_upload_trace_state_variables, t);
       INHERIT (to_get_raw_trace_data, t);
       INHERIT (to_set_disconnected_tracing, t);
+      INHERIT (to_get_segment_base, t);
       INHERIT (to_magic, t);
       /* Do not inherit to_memory_map.  */
       /* Do not inherit to_flash_erase.  */
--- a/target.h
+++ b/target.h
@@ -673,6 +673,10 @@ struct target_ops
        right now, or in this debug session, or for this target -- return -1.  */
     int (*to_core_of_thread) (struct target_ops *, ptid_t ptid);
 
+    /* Get the segment base of current inferior to BASE.
+       Return 0 if success.  */
+    int (*to_get_segment_base) (int idx, ULONGEST *base);
+
     int to_magic;
     /* Need sub-structure for target machine related rather than comm related?
      */

Re: [RFA 3/5] Prec: x86 segment register support: target

[Michael Snyder]

Hui Zhu wrote:
> This patch add a interface to let GDB get segment base message from inferior.
> 
> Thanks,
> Hui
> 
> 2010-03-16  Hui Zhu  <teawater@gmail.com>
> 
> 	* target.c (update_current_target): Add to_get_segment_base.
> 	* target.h (target_ops): Ditto.

Hi Hui,

I'm glad you're doing this.

However, isn't target.c the wrong place for this function?
Wouldn't it belong better in the gdbarch?  It is architecture-
specific, if I understand correctly.

That is, this will be the same between i386-ptrace and i386-remote,
but different between i386-remote and (say) mips-remote.

Michael

Re: [RFA 3/5] Prec: x86 segment register support: target

[Daniel Jacobowitz]

On Tue, Mar 16, 2010 at 11:12:49AM -0700, Michael Snyder wrote:
> However, isn't target.c the wrong place for this function?
> Wouldn't it belong better in the gdbarch?  It is architecture-
> specific, if I understand correctly.
> 
> That is, this will be the same between i386-ptrace and i386-remote,
> but different between i386-remote and (say) mips-remote.

IMO, these should simply be added as new registers.  Since the name
$gs is already taken, why not add a $gs_base register?

H.J. Lu has recently converted the i386 target to use target
descriptions; it should be easy to add new registers now.
They could go in 32bit-linux.xml or in some other file that could be
shared among OS's.  H.J. may have some more ideas.

-- 
Daniel Jacobowitz
CodeSourcery

Re: [RFA 3/5] Prec: x86 segment register support: target

[Hui Zhu]

[-- Attachment #1: Type: text/plain, Size: 2409 bytes --]

Thanks Michael and Daniel.

I make a patch to add base of segments registers to x86-32:
(gdb) info reg
eax            0xffffd514	-10988
ecx            0x1eda96c5	517641925
edx            0x1	1
ebx            0xf7fb1ff4	-134537228
esp            0xffffd488	0xffffd488
ebp            0xffffd488	0xffffd488
esi            0x8048510	134513936
edi            0x80483d0	134513616
eip            0x8048487	0x8048487 <main+3>
eflags         0x246	[ PF ZF IF ]
cs             0x23	35
ss             0x2b	43
ds             0x2b	43
es             0x2b	43
fs             0x0	0
gs             0x63	99
cs_base        0x0	0
ss_base        0x0	0
ds_base        0x0	0
es_base        0x0	0
fs_base        0x0	0
gs_base        0xf7e528d0	-135976752

I try it in x86-32 pc and 32bit code in x86-64.  It works OK.

Please help me review it.

Best regards,
Hui

2010-03-22  Hui Zhu  <teawater@gmail.com>

	* features/i386/32bit-linux.xml (org.gnu.gdb.i386.linux): Add
	cs_base, ss_base, ds_base, es_base, fs_base and gs_base.
	* i386-tdep.h (i386_segment_base_regnum): New enum.
	* amd64-linux-nat.c (GDT_ENTRY_TLS_MIN,
	GDT_ENTRY_TLS_MAX): New marco.
	(ps_get_thread_area): New extern.
	(amd64_linux_fetch_inferior_registers): Add
	code to get 32 bits segment registers base.
	* i386-linux-nat.c (GDT_ENTRY_TLS_ENTRIES,
	GDT_ENTRY_TLS_MIN,
	GDT_ENTRY_TLS_MAX): New marco.
	(ps_get_thread_area): New extern.
	(i386_linux_fetch_inferior_registers): Add
	code to get segment registers base.

On Wed, Mar 17, 2010 at 04:04, Daniel Jacobowitz <dan@codesourcery.com> wrote:
> On Tue, Mar 16, 2010 at 11:12:49AM -0700, Michael Snyder wrote:
>> However, isn't target.c the wrong place for this function?
>> Wouldn't it belong better in the gdbarch?  It is architecture-
>> specific, if I understand correctly.
>>
>> That is, this will be the same between i386-ptrace and i386-remote,
>> but different between i386-remote and (say) mips-remote.
>
> IMO, these should simply be added as new registers.  Since the name
> $gs is already taken, why not add a $gs_base register?
>
> H.J. Lu has recently converted the i386 target to use target
> descriptions; it should be easy to add new registers now.
> They could go in 32bit-linux.xml or in some other file that could be
> shared among OS's.  H.J. may have some more ideas.
>
> --
> Daniel Jacobowitz
> CodeSourcery
>

[-- Attachment #2: add-segment-base.txt --]
[-- Type: text/plain, Size: 5295 bytes --]

---
 amd64-linux-nat.c             |   33 +++++++++++++++++++++++++++++++++
 features/i386/32bit-linux.xml |    6 ++++++
 features/i386/i386-linux.c    |    6 ++++++
 i386-linux-nat.c              |   34 ++++++++++++++++++++++++++++++++++
 i386-tdep.h                   |   10 ++++++++++
 5 files changed, 89 insertions(+)

--- a/amd64-linux-nat.c
+++ b/amd64-linux-nat.c
@@ -155,6 +155,12 @@ fill_fpregset (const struct regcache *re
    this for all registers (including the floating point and SSE
    registers).  */
 
+#define GDT_ENTRY_TLS_MIN 12
+#define GDT_ENTRY_TLS_MAX 14
+
+extern ps_err_e ps_get_thread_area (const struct ps_prochandle *ph,
+		                    lwpid_t lwpid, int idx, void **base);
+
 static void
 amd64_linux_fetch_inferior_registers (struct target_ops *ops,
 				      struct regcache *regcache, int regnum)
@@ -188,6 +194,33 @@ amd64_linux_fetch_inferior_registers (st
 
       amd64_supply_fxsave (regcache, -1, &fpregs);
     }
+
+  if (gdbarch_ptr_bit (gdbarch) == 32
+      && regnum >= I386_CS_BASE_REGNUM && regnum <= I386_GS_BASE_REGNUM)
+    {
+      ULONGEST idx;
+      int base;
+
+      /* Get the idx.  */
+      regcache_raw_read_unsigned (regcache,
+                                  regnum - I386_CS_BASE_REGNUM + I386_CS_REGNUM,
+				  &idx);
+      idx >>= 3;
+
+      /* The base will be 0 if the idx is not TLS.  */
+      if (idx < GDT_ENTRY_TLS_MIN || idx > GDT_ENTRY_TLS_MAX)
+        {
+          regcache_raw_supply (regcache, regnum, NULL);
+          return;
+        }
+
+      /* Get the base.  */
+      if (ps_get_thread_area (NULL, tid, idx, (void *)&base) == PS_ERR)
+        perror_with_name (_("Couldn't get registers"));
+
+      regcache_raw_supply (regcache, regnum, &base);
+      return;
+    }
 }
 
 /* Store register REGNUM back into the child process.  If REGNUM is
--- a/features/i386/32bit-linux.xml
+++ b/features/i386/32bit-linux.xml
@@ -8,4 +8,10 @@
 <!DOCTYPE feature SYSTEM "gdb-target.dtd">
 <feature name="org.gnu.gdb.i386.linux">
   <reg name="orig_eax" bitsize="32" type="int" regnum="41"/>
+  <reg name="cs_base" bitsize="32" type="int" regnum="42"/>
+  <reg name="ss_base" bitsize="32" type="int" regnum="43"/>
+  <reg name="ds_base" bitsize="32" type="int" regnum="44"/>
+  <reg name="es_base" bitsize="32" type="int" regnum="45"/>
+  <reg name="fs_base" bitsize="32" type="int" regnum="46"/>
+  <reg name="gs_base" bitsize="32" type="int" regnum="47"/>
 </feature>
--- a/features/i386/i386-linux.c
+++ b/features/i386/i386-linux.c
@@ -71,6 +71,12 @@ initialize_tdesc_i386_linux (void)
 
   feature = tdesc_create_feature (result, "org.gnu.gdb.i386.linux");
   tdesc_create_reg (feature, "orig_eax", 41, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "cs_base", 42, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "ss_base", 43, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "ds_base", 44, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "es_base", 45, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "fs_base", 46, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "gs_base", 47, 1, NULL, 32, "int");
 
   feature = tdesc_create_feature (result, "org.gnu.gdb.i386.sse");
   field_type = tdesc_named_type (feature, "ieee_single");
--- a/i386-linux-nat.c
+++ b/i386-linux-nat.c
@@ -450,6 +450,13 @@ static int store_fpxregs (const struct r
    this for all registers (including the floating point and SSE
    registers).  */
 
+#define GDT_ENTRY_TLS_ENTRIES	3
+#define GDT_ENTRY_TLS_MIN	6
+#define GDT_ENTRY_TLS_MAX 	(GDT_ENTRY_TLS_MIN + GDT_ENTRY_TLS_ENTRIES - 1)
+
+extern ps_err_e ps_get_thread_area (const struct ps_prochandle *ph,
+		                    lwpid_t lwpid, int idx, void **base);
+
 static void
 i386_linux_fetch_inferior_registers (struct target_ops *ops,
 				     struct regcache *regcache, int regno)
@@ -516,6 +523,33 @@ i386_linux_fetch_inferior_registers (str
       return;
     }
 
+  /* Get the base of segment registers.  */
+  if (regno >= I386_CS_BASE_REGNUM && regno <= I386_GS_BASE_REGNUM)
+    {
+      ULONGEST idx;
+      int base;
+
+      /* Get the idx.  */
+      regcache_raw_read_unsigned (regcache,
+                                  regno - I386_CS_BASE_REGNUM + I386_CS_REGNUM,
+				  &idx);
+      idx >>= 3;
+
+      /* The base will be 0 if the idx is not TLS.  */
+      if (idx < GDT_ENTRY_TLS_MIN || idx > GDT_ENTRY_TLS_MAX)
+        {
+          regcache_raw_supply (regcache, regno, NULL);
+          return;
+        }
+
+      /* Get the base.  */
+      if (ps_get_thread_area (NULL, tid, idx, (void *)&base) == PS_ERR)
+        perror_with_name (_("Couldn't get registers"));
+
+      regcache_raw_supply (regcache, regno, &base);
+      return;
+    }
+
   internal_error (__FILE__, __LINE__,
 		  _("Got request for bad register number %d."), regno);
 }
--- a/i386-tdep.h
+++ b/i386-tdep.h
@@ -231,6 +231,16 @@ enum i386_regnum
   I386_MXCSR_REGNUM = 40	/* %mxcsr */ 
 };
 
+enum i386_segment_base_regnum
+{
+  I386_CS_BASE_REGNUM = 42,	/* %cs_base */
+  I386_SS_BASE_REGNUM,		/* %ss_base */
+  I386_DS_BASE_REGNUM,		/* %ds_base */
+  I386_ES_BASE_REGNUM,		/* %es_base */
+  I386_FS_BASE_REGNUM,		/* %fs_base */
+  I386_GS_BASE_REGNUM,		/* %gs_base */
+};
+
 /* Register numbers of RECORD_REGMAP.  */
 
 enum record_i386_regnum

Re: [RFA 3/5] Prec: x86 segment register support: target

[H.J. Lu]

On Mon, Mar 22, 2010 at 7:02 AM, Hui Zhu <teawater@gmail.com> wrote:
> Thanks Michael and Daniel.
>
> I make a patch to add base of segments registers to x86-32:
> (gdb) info reg
> eax            0xffffd514       -10988
> ecx            0x1eda96c5       517641925
> edx            0x1      1
> ebx            0xf7fb1ff4       -134537228
> esp            0xffffd488       0xffffd488
> ebp            0xffffd488       0xffffd488
> esi            0x8048510        134513936
> edi            0x80483d0        134513616
> eip            0x8048487        0x8048487 <main+3>
> eflags         0x246    [ PF ZF IF ]
> cs             0x23     35
> ss             0x2b     43
> ds             0x2b     43
> es             0x2b     43
> fs             0x0      0
> gs             0x63     99
> cs_base        0x0      0
> ss_base        0x0      0
> ds_base        0x0      0
> es_base        0x0      0
> fs_base        0x0      0
> gs_base        0xf7e528d0       -135976752
>
> I try it in x86-32 pc and 32bit code in x86-64.  It works OK.
>
> Please help me review it.
>
> Best regards,
> Hui
>
> 2010-03-22  Hui Zhu  <teawater@gmail.com>
>
>        * features/i386/32bit-linux.xml (org.gnu.gdb.i386.linux): Add
>        cs_base, ss_base, ds_base, es_base, fs_base and gs_base.
>        * i386-tdep.h (i386_segment_base_regnum): New enum.
>        * amd64-linux-nat.c (GDT_ENTRY_TLS_MIN,
>        GDT_ENTRY_TLS_MAX): New marco.
>        (ps_get_thread_area): New extern.
>        (amd64_linux_fetch_inferior_registers): Add
>        code to get 32 bits segment registers base.
>        * i386-linux-nat.c (GDT_ENTRY_TLS_ENTRIES,
>        GDT_ENTRY_TLS_MIN,
>        GDT_ENTRY_TLS_MAX): New marco.
>        (ps_get_thread_area): New extern.
>        (i386_linux_fetch_inferior_registers): Add
>        code to get segment registers base.

Are we going to support them on other OSes? If not,
the contents of i386_segment_base_regnum should be
moved to i386-linux-tdep.h and those values should
be after

/* Register number for the "orig_eax" pseudo-register.  If this
   pseudo-register contains a value >= 0 it is interpreted as the
   system call number that the kernel is supposed to restart.  */
#define I386_LINUX_ORIG_EAX_REGNUM I386_SSE_NUM_REGS

In any cases, they shouldn't be hard-coded to any values.
Otherwise, it won't work with AVX, which will add more registers.


-- 
H.J.

Re: [RFA 3/5] Prec: x86 segment register support: target

[Mark Kettenis]

> From: Hui Zhu <teawater@gmail.com>
> Date: Mon, 22 Mar 2010 22:02:52 +0800
> 
> Thanks Michael and Daniel.
> 
> I make a patch to add base of segments registers to x86-32:
> (gdb) info reg
> eax            0xffffd514	-10988
> ecx            0x1eda96c5	517641925
> edx            0x1	1
> ebx            0xf7fb1ff4	-134537228
> esp            0xffffd488	0xffffd488
> ebp            0xffffd488	0xffffd488
> esi            0x8048510	134513936
> edi            0x80483d0	134513616
> eip            0x8048487	0x8048487 <main+3>
> eflags         0x246	[ PF ZF IF ]
> cs             0x23	35
> ss             0x2b	43
> ds             0x2b	43
> es             0x2b	43
> fs             0x0	0
> gs             0x63	99
> cs_base        0x0	0
> ss_base        0x0	0
> ds_base        0x0	0
> es_base        0x0	0
> fs_base        0x0	0
> gs_base        0xf7e528d0	-135976752
> 
> I try it in x86-32 pc and 32bit code in x86-64.  It works OK.

Sorry, but I don't think adding these xx_base registers is a good
idea.  They are not acrhitected registers so they don't beling in the
list of registers.

Re: [RFA 3/5] Prec: x86 segment register support: target

[Hui Zhu]

Prec i386 code is not OS special.  So the base will not be OS special too.

Thanks,
Hui

On Mon, Mar 22, 2010 at 22:35, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Mon, Mar 22, 2010 at 7:02 AM, Hui Zhu <teawater@gmail.com> wrote:
>> Thanks Michael and Daniel.
>>
>> I make a patch to add base of segments registers to x86-32:
>> (gdb) info reg
>> eax            0xffffd514       -10988
>> ecx            0x1eda96c5       517641925
>> edx            0x1      1
>> ebx            0xf7fb1ff4       -134537228
>> esp            0xffffd488       0xffffd488
>> ebp            0xffffd488       0xffffd488
>> esi            0x8048510        134513936
>> edi            0x80483d0        134513616
>> eip            0x8048487        0x8048487 <main+3>
>> eflags         0x246    [ PF ZF IF ]
>> cs             0x23     35
>> ss             0x2b     43
>> ds             0x2b     43
>> es             0x2b     43
>> fs             0x0      0
>> gs             0x63     99
>> cs_base        0x0      0
>> ss_base        0x0      0
>> ds_base        0x0      0
>> es_base        0x0      0
>> fs_base        0x0      0
>> gs_base        0xf7e528d0       -135976752
>>
>> I try it in x86-32 pc and 32bit code in x86-64.  It works OK.
>>
>> Please help me review it.
>>
>> Best regards,
>> Hui
>>
>> 2010-03-22  Hui Zhu  <teawater@gmail.com>
>>
>>        * features/i386/32bit-linux.xml (org.gnu.gdb.i386.linux): Add
>>        cs_base, ss_base, ds_base, es_base, fs_base and gs_base.
>>        * i386-tdep.h (i386_segment_base_regnum): New enum.
>>        * amd64-linux-nat.c (GDT_ENTRY_TLS_MIN,
>>        GDT_ENTRY_TLS_MAX): New marco.
>>        (ps_get_thread_area): New extern.
>>        (amd64_linux_fetch_inferior_registers): Add
>>        code to get 32 bits segment registers base.
>>        * i386-linux-nat.c (GDT_ENTRY_TLS_ENTRIES,
>>        GDT_ENTRY_TLS_MIN,
>>        GDT_ENTRY_TLS_MAX): New marco.
>>        (ps_get_thread_area): New extern.
>>        (i386_linux_fetch_inferior_registers): Add
>>        code to get segment registers base.
>
> Are we going to support them on other OSes? If not,
> the contents of i386_segment_base_regnum should be
> moved to i386-linux-tdep.h and those values should
> be after
>
> /* Register number for the "orig_eax" pseudo-register.  If this
>   pseudo-register contains a value >= 0 it is interpreted as the
>   system call number that the kernel is supposed to restart.  */
> #define I386_LINUX_ORIG_EAX_REGNUM I386_SSE_NUM_REGS
>
> In any cases, they shouldn't be hard-coded to any values.
> Otherwise, it won't work with AVX, which will add more registers.
>
>
> --
> H.J.
>

Re: [RFA 3/5] Prec: x86 segment register support: target

[Hui Zhu]

Agree with you.   But I cannot find how to remove it from this list.  :(

Could you help me with it?

Thanks,
Hui

On Mon, Mar 22, 2010 at 22:33, Mark Kettenis <mark.kettenis@xs4all.nl> wrote:
>> From: Hui Zhu <teawater@gmail.com>
>> Date: Mon, 22 Mar 2010 22:02:52 +0800
>>
>> Thanks Michael and Daniel.
>>
>> I make a patch to add base of segments registers to x86-32:
>> (gdb) info reg
>> eax            0xffffd514     -10988
>> ecx            0x1eda96c5     517641925
>> edx            0x1    1
>> ebx            0xf7fb1ff4     -134537228
>> esp            0xffffd488     0xffffd488
>> ebp            0xffffd488     0xffffd488
>> esi            0x8048510      134513936
>> edi            0x80483d0      134513616
>> eip            0x8048487      0x8048487 <main+3>
>> eflags         0x246  [ PF ZF IF ]
>> cs             0x23   35
>> ss             0x2b   43
>> ds             0x2b   43
>> es             0x2b   43
>> fs             0x0    0
>> gs             0x63   99
>> cs_base        0x0    0
>> ss_base        0x0    0
>> ds_base        0x0    0
>> es_base        0x0    0
>> fs_base        0x0    0
>> gs_base        0xf7e528d0     -135976752
>>
>> I try it in x86-32 pc and 32bit code in x86-64.  It works OK.
>
> Sorry, but I don't think adding these xx_base registers is a good
> idea.  They are not acrhitected registers so they don't beling in the
> list of registers.
>

Re: [RFA 3/5] Prec: x86 segment register support: target

[Daniel Jacobowitz]

On Mon, Mar 22, 2010 at 03:33:55PM +0100, Mark Kettenis wrote:
> Sorry, but I don't think adding these xx_base registers is a good
> idea.  They are not acrhitected registers so they don't beling in the
> list of registers.

What do you suggest instead?

I don't know a lot about the details of the x86 architecture.  But
I've heard a lot of complaints that what people want to see when they
say "print $gs" is not what we're showing them, and that this base
address is useful.

-- 
Daniel Jacobowitz
CodeSourcery

Re: [RFA 3/5] Prec: x86 segment register support: target

[Mark Kettenis]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain, Size: 2940 bytes --]

> Date: Mon, 22 Mar 2010 07:35:00 -0700
> From: "H.J. Lu" <hjl.tools@gmail.com>
> 
> On Mon, Mar 22, 2010 at 7:02 AM, Hui Zhu <teawater@gmail.com> wrote:
> > Thanks Michael and Daniel.
> >
> > I make a patch to add base of segments registers to x86-32:
> > (gdb) info reg
> > eax            0xffffd514       -10988
> > ecx            0x1eda96c5       517641925
> > edx            0x1      1
> > ebx            0xf7fb1ff4       -134537228
> > esp            0xffffd488       0xffffd488
> > ebp            0xffffd488       0xffffd488
> > esi            0x8048510        134513936
> > edi            0x80483d0        134513616
> > eip            0x8048487        0x8048487 <main+3>
> > eflags         0x246    [ PF ZF IF ]
> > cs             0x23     35
> > ss             0x2b     43
> > ds             0x2b     43
> > es             0x2b     43
> > fs             0x0      0
> > gs             0x63     99
> > cs_base        0x0      0
> > ss_base        0x0      0
> > ds_base        0x0      0
> > es_base        0x0      0
> > fs_base        0x0      0
> > gs_base        0xf7e528d0       -135976752
> >
> > I try it in x86-32 pc and 32bit code in x86-64.  It works OK.
> >
> > Please help me review it.
> >
> > Best regards,
> > Hui
> >
> > 2010-03-22  Hui Zhu  <teawater@gmail.com>
> >
> >        * features/i386/32bit-linux.xml (org.gnu.gdb.i386.linux): Add
> >        cs_base, ss_base, ds_base, es_base, fs_base and gs_base.
> >        * i386-tdep.h (i386_segment_base_regnum): New enum.
> >        * amd64-linux-nat.c (GDT_ENTRY_TLS_MIN,
> >        GDT_ENTRY_TLS_MAX): New marco.
> >        (ps_get_thread_area): New extern.
> >        (amd64_linux_fetch_inferior_registers): Add
> >        code to get 32 bits segment registers base.
> >        * i386-linux-nat.c (GDT_ENTRY_TLS_ENTRIES,
> >        GDT_ENTRY_TLS_MIN,
> >        GDT_ENTRY_TLS_MAX): New marco.
> >        (ps_get_thread_area): New extern.
> >        (i386_linux_fetch_inferior_registers): Add
> >        code to get segment registers base.
> 
> Are we going to support them on other OSes? If not,
> the contents of i386_segment_base_regnum should be
> moved to i386-linux-tdep.h and those values should
> be after
> 
> /* Register number for the "orig_eax" pseudo-register.  If this
>    pseudo-register contains a value >= 0 it is interpreted as the
>    system call number that the kernel is supposed to restart.  */
> #define I386_LINUX_ORIG_EAX_REGNUM I386_SSE_NUM_REGS
> 
> In any cases, they shouldn't be hard-coded to any values.
> Otherwise, it won't work with AVX, which will add more registers.

In any case; this stuff will have to wait until we're done withe the
AVX stuff, which I'll be looking at again tonight.

Re: [RFA 3/5] Prec: x86 segment register support: target

[Doug Evans]

On Mon, Mar 22, 2010 at 7:33 AM, Mark Kettenis <mark.kettenis@xs4all.nl> wrote:
>> From: Hui Zhu <teawater@gmail.com>
>> Date: Mon, 22 Mar 2010 22:02:52 +0800
>>
>> Thanks Michael and Daniel.
>>
>> I make a patch to add base of segments registers to x86-32:
>> (gdb) info reg
>> eax            0xffffd514     -10988
>> ecx            0x1eda96c5     517641925
>> edx            0x1    1
>> ebx            0xf7fb1ff4     -134537228
>> esp            0xffffd488     0xffffd488
>> ebp            0xffffd488     0xffffd488
>> esi            0x8048510      134513936
>> edi            0x80483d0      134513616
>> eip            0x8048487      0x8048487 <main+3>
>> eflags         0x246  [ PF ZF IF ]
>> cs             0x23   35
>> ss             0x2b   43
>> ds             0x2b   43
>> es             0x2b   43
>> fs             0x0    0
>> gs             0x63   99
>> cs_base        0x0    0
>> ss_base        0x0    0
>> ds_base        0x0    0
>> es_base        0x0    0
>> fs_base        0x0    0
>> gs_base        0xf7e528d0     -135976752
>>
>> I try it in x86-32 pc and 32bit code in x86-64.  It works OK.
>
> Sorry, but I don't think adding these xx_base registers is a good
> idea.  They are not acrhitected registers so they don't beling in the
> list of registers.
>

fwiw, I think it's a great idea.

Re: [RFA 3/5] Prec: x86 segment register support: target

[Eli Zaretskii]

> Date: Mon, 22 Mar 2010 10:53:35 -0400
> From: Daniel Jacobowitz <dan@codesourcery.com>
> Cc: teawater@gmail.com, msnyder@vmware.com, gdb-patches@sourceware.org, 	hjl.tools@gmail.com
> 
> On Mon, Mar 22, 2010 at 03:33:55PM +0100, Mark Kettenis wrote:
> > Sorry, but I don't think adding these xx_base registers is a good
> > idea.  They are not acrhitected registers so they don't beling in the
> > list of registers.
> 
> What do you suggest instead?

Would a separate command fit the bill?  (The DJGPP build already has
something similar, see "info dos ldt" and its description in the
manual with an example of how to use it to display the DS segment base
address and limit.)

Re: [RFA 3/5] Prec: x86 segment register support: target

[Doug Evans]

On Mon, Mar 22, 2010 at 11:04 AM, Eli Zaretskii <eliz@gnu.org> wrote:
>> Date: Mon, 22 Mar 2010 10:53:35 -0400
>> From: Daniel Jacobowitz <dan@codesourcery.com>
>> Cc: teawater@gmail.com, msnyder@vmware.com, gdb-patches@sourceware.org,       hjl.tools@gmail.com
>>
>> On Mon, Mar 22, 2010 at 03:33:55PM +0100, Mark Kettenis wrote:
>> > Sorry, but I don't think adding these xx_base registers is a good
>> > idea.  They are not acrhitected registers so they don't beling in the
>> > list of registers.
>>
>> What do you suggest instead?
>
> Would a separate command fit the bill?  (The DJGPP build already has
> something similar, see "info dos ldt" and its description in the
> manual with an example of how to use it to display the DS segment base
> address and limit.)

I'd have the regs in a separate info command (out of "info regs"),
there's more than just base, there's the limit and flags regs too, and
having them would really reduce the S/N ratio of "info reg", but
having $gs_base, et.al. usable in expressions is really useful (and
long overdue).  Either that or make "gs:<offset>" as an address work -
you'd still want to be able to fold it to a "flat" address though.