From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 62930 invoked by alias); 27 Jun 2018 12:43:47 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 62910 invoked by uid 89); 27 Jun 2018 12:43:47 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-24.4 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,KAM_LAZY_DOMAIN_SECURITY,SPF_HELO_PASS autolearn=ham version=3.3.2 spammy=inferiors, HTo:U*uweigand, 00431a78b28f, *thread X-HELO: mx1.redhat.com Received: from mx3-rdu2.redhat.com (HELO mx1.redhat.com) (66.187.233.73) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 27 Jun 2018 12:43:45 +0000 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.rdu2.redhat.com [10.11.54.5]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id CAC374023337; Wed, 27 Jun 2018 12:43:43 +0000 (UTC) Received: from [127.0.0.1] (ovpn04.gateway.prod.ext.ams2.redhat.com [10.39.146.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id EFE091C5B9; Wed, 27 Jun 2018 12:43:42 +0000 (UTC) Subject: [PATCH] Fix Cell debugging regression (Re: [PATCH] Use thread_info and inferior pointers more throughout) To: Ulrich Weigand References: <20180627113347.04B6ED801C0@oc3748833570.ibm.com> Cc: Tom Tromey , gdb-patches@sourceware.org From: Pedro Alves Message-ID: Date: Wed, 27 Jun 2018 12:43:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0 MIME-Version: 1.0 In-Reply-To: <20180627113347.04B6ED801C0@oc3748833570.ibm.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-SW-Source: 2018-06/txt/msg00641.txt.bz2 On 06/27/2018 12:33 PM, Ulrich Weigand wrote: > Pedro Alves wrote: > >> ps_err_e >> ps_lgetregs (struct ps_prochandle *ph, lwpid_t lwpid, prgregset_t gregset) >> { >> - ptid_t ptid = ptid_build (ptid_get_pid (ph->ptid), lwpid, 0); >> - struct regcache *regcache >> - = get_thread_arch_regcache (ptid, target_gdbarch ()); >> + struct regcache *regcache = get_thread_regcache (ph->thread); > > This change (and the related ones in the following routines > completely break Cell multi-arch debugging. The point of using > get_thread_arch_regcache with target_gdbarch() instead of just > plain get_thread_regcache is that the proc-service routines > must always operated on the "main" (in this case PowerPC) > architecture, because that's the register set libthread_db > expects to be using. > The change above switches the behavior to use the SPU architecture > if GDB happens to interrupt SPU code. This is wrong and causes > internal GDB errors pretty much instantly when starting an SPU ... Sorry, missed that. Some comments here would be helpful. I think this should fix it. WDYT? >From d4b27737d93f466955a34c89a3f304bf4d3579d2 Mon Sep 17 00:00:00 2001 From: Pedro Alves Date: Wed, 27 Jun 2018 12:54:50 +0100 Subject: [PATCH] Fix Cell debugging regression Commit 00431a78b28f ("Use thread_info and inferior pointers more throughout") broke Cell multi-arch debugging, because it made the proc-service routines (ps_lgetregs etc.) access registers using the SPU architecture if GDB happens to interrupt SPU code. The proc-service routines must always operate on the "main" (in this case PowerPC) architecture, because that's the register set libthread_db expects to be using. Restore the previous behavior, but wrapped in a new get_thread_main_regcache function with a describing comment hinting at multi-arch scenarios. gdb/ChangeLog: 2018-06-27 Pedro Alves * proc-service.c (ps_lgetregs, ps_lsetregs, ps_lgetfpregs) (ps_lsetfpregs): Use get_thread_main_regcache. * regcache.c (get_thread_main_regcache): Define. * regcache.h (get_thread_main_regcache): Declare. --- gdb/proc-service.c | 14 ++++++++++---- gdb/regcache.c | 8 ++++++++ gdb/regcache.h | 8 ++++++++ 3 files changed, 26 insertions(+), 4 deletions(-) diff --git a/gdb/proc-service.c b/gdb/proc-service.c index 04867d227b..d96a689490 100644 --- a/gdb/proc-service.c +++ b/gdb/proc-service.c @@ -126,13 +126,19 @@ ps_pdwrite (struct ps_prochandle *ph, psaddr_t addr, return ps_xfer_memory (ph, addr, (gdb_byte *) buf, size, 1); } +/* The following register-related routines use + get_thread_main_regcache instead of get_thread_regcache because in + Cell debugging, the proc-service routines must always operate on + the "main" (in this case PowerPC) architecture, because that's the + register set libthread_db expects to be using. */ + /* Get the general registers of LWP LWPID within the target process PH and store them in GREGSET. */ ps_err_e ps_lgetregs (struct ps_prochandle *ph, lwpid_t lwpid, prgregset_t gregset) { - struct regcache *regcache = get_thread_regcache (ph->thread); + struct regcache *regcache = get_thread_main_regcache (ph->thread); target_fetch_registers (regcache, -1); fill_gregset (regcache, (gdb_gregset_t *) gregset, -1); @@ -146,7 +152,7 @@ ps_lgetregs (struct ps_prochandle *ph, lwpid_t lwpid, prgregset_t gregset) ps_err_e ps_lsetregs (struct ps_prochandle *ph, lwpid_t lwpid, const prgregset_t gregset) { - struct regcache *regcache = get_thread_regcache (ph->thread); + struct regcache *regcache = get_thread_main_regcache (ph->thread); supply_gregset (regcache, (const gdb_gregset_t *) gregset); target_store_registers (regcache, -1); @@ -160,7 +166,7 @@ ps_lsetregs (struct ps_prochandle *ph, lwpid_t lwpid, const prgregset_t gregset) ps_err_e ps_lgetfpregs (struct ps_prochandle *ph, lwpid_t lwpid, gdb_prfpregset_t *fpregset) { - struct regcache *regcache = get_thread_regcache (ph->thread); + struct regcache *regcache = get_thread_main_regcache (ph->thread); target_fetch_registers (regcache, -1); fill_fpregset (regcache, (gdb_fpregset_t *) fpregset, -1); @@ -175,7 +181,7 @@ ps_err_e ps_lsetfpregs (struct ps_prochandle *ph, lwpid_t lwpid, const gdb_prfpregset_t *fpregset) { - struct regcache *regcache = get_thread_regcache (ph->thread); + struct regcache *regcache = get_thread_main_regcache (ph->thread); supply_fpregset (regcache, (const gdb_fpregset_t *) fpregset); target_store_registers (regcache, -1); diff --git a/gdb/regcache.c b/gdb/regcache.c index 1bc4f0de88..6380f3cbea 100644 --- a/gdb/regcache.c +++ b/gdb/regcache.c @@ -399,6 +399,14 @@ get_thread_regcache (thread_info *thread) return get_thread_regcache (thread->ptid); } +/* See regcache.h. */ + +struct regcache * +get_thread_main_regcache (thread_info *thread) +{ + return get_thread_arch_regcache (thread->ptid, thread->inf->gdbarch); +} + struct regcache * get_current_regcache (void) { diff --git a/gdb/regcache.h b/gdb/regcache.h index 983137f6ad..efeb29c1bd 100644 --- a/gdb/regcache.h +++ b/gdb/regcache.h @@ -34,6 +34,14 @@ extern struct regcache *get_thread_regcache (ptid_t ptid); /* Get the regcache of THREAD. */ extern struct regcache *get_thread_regcache (thread_info *thread); +/* Get the thread's regcache using its inferior's "main" architecture. + In multi-arch debugging scenarios, the thread's architecture may + differ from the inferior's "main" architecture. E.g., in the Cell + combined debugger, if GDB happens to interrupt SPU code, the + thread's architecture is SPU, and the main architecture is + PowerPC. */ +extern struct regcache *get_thread_main_regcache (thread_info *thread); + extern struct regcache *get_thread_arch_regcache (ptid_t, struct gdbarch *); extern struct regcache *get_thread_arch_aspace_regcache (ptid_t, struct gdbarch *, -- 2.14.4