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From: Luis Machado <luis.machado@arm.com>
To: gdb-patches@sourceware.org
Subject: Re: [PATCH] [AArch64] Update FPSR/FPCR fields for FPU and SVE
Date: Tue, 4 Oct 2022 09:15:20 +0100	[thread overview]
Message-ID: <e8a80fa4-5eb0-6cd6-746c-ed6434c1f6b5@arm.com> (raw)
In-Reply-To: <20220923103946.96804-1-luis.machado@arm.com>

On 9/23/22 11:39, Luis Machado via Gdb-patches wrote:
> I noticed some missing flags/fields from FPSR and FPCR registers in
> both the FPU and SVE target descriptions.
> 
> This patch adds those and makes the SVE versions of FPSR and FPCR
> use the proper flags/bitfields types.
> ---
>   gdb/features/aarch64-fpu.c   |  3 +++
>   gdb/features/aarch64-fpu.xml | 14 +++++++++++++
>   gdb/features/aarch64-sve.c   | 39 ++++++++++++++++++++++++++++++++++--
>   3 files changed, 54 insertions(+), 2 deletions(-)
> 
> diff --git a/gdb/features/aarch64-fpu.c b/gdb/features/aarch64-fpu.c
> index a80b7d4c1b8..27e75524cfe 100644
> --- a/gdb/features/aarch64-fpu.c
> +++ b/gdb/features/aarch64-fpu.c
> @@ -126,8 +126,11 @@ create_feature_aarch64_fpu (struct target_desc *result, long regnum)
>     tdesc_add_flag (type_with_fields, 10, "OFE");
>     tdesc_add_flag (type_with_fields, 11, "UFE");
>     tdesc_add_flag (type_with_fields, 12, "IXE");
> +  tdesc_add_flag (type_with_fields, 13, "EBF");
>     tdesc_add_flag (type_with_fields, 15, "IDE");
> +  tdesc_add_bitfield (type_with_fields, "Len", 16, 18);
>     tdesc_add_flag (type_with_fields, 19, "FZ16");
> +  tdesc_add_bitfield (type_with_fields, "Stride", 20, 21);
>     tdesc_add_bitfield (type_with_fields, "RMode", 22, 23);
>     tdesc_add_flag (type_with_fields, 24, "FZ");
>     tdesc_add_flag (type_with_fields, 25, "DN");
> diff --git a/gdb/features/aarch64-fpu.xml b/gdb/features/aarch64-fpu.xml
> index 4db5c50f250..89bbcc0a855 100644
> --- a/gdb/features/aarch64-fpu.xml
> +++ b/gdb/features/aarch64-fpu.xml
> @@ -142,11 +142,25 @@
>       <field name="UFE" start="11" end="11"/>
>       <!-- Inexact floating-point exception trap enable.  -->
>       <field name="IXE" start="12" end="12"/>
> +    <!-- The value of this bit controls the numeric behaviors of BFloat16 dot
> +	 product calculations performed by the BFDOT, BFMMLA, BFMOPA, and
> +	 BFMOPS instructions when FEAT_EBF16 is implemented.  -->
> +    <field name="EBF" start="13" end="13"/>
>       <!-- Input Denormal floating-point exception trap enable.  -->
>       <field name="IDE" start="15" end="15"/>
> +    <!-- This field has no function in AArch64 state, and non-zero values are
> +	 ignored during execution in AArch64 state.
> +	 This field is included only for context saving and restoration of
> +	 the AArch32 FPSCR.Len field.  -->
> +    <field name="Len" start="16" end="18"/>
>       <!-- Flush-to-zero mode control bit on half-precision data-processing
>            instructions.  -->
>       <field name="FZ16" start="19" end="19"/>
> +    <!-- This field has no function in AArch64 state, and non-zero values are
> +	 ignored during execution in AArch64 state.
> +	 This field is included only for context saving and restoration of the
> +	 AArch32 FPSCR.Stride field.  -->
> +    <field name="Stride" start="20" end="21"/>
>       <!-- Rounding Mode control field.  -->
>       <field name="RMode" start="22" end="23"/>
>       <!-- Flush-to-zero mode control bit.  -->
> diff --git a/gdb/features/aarch64-sve.c b/gdb/features/aarch64-sve.c
> index 9f6c2522b4c..7b4a510633d 100644
> --- a/gdb/features/aarch64-sve.c
> +++ b/gdb/features/aarch64-sve.c
> @@ -40,6 +40,41 @@ create_feature_aarch64_sve (struct target_desc *result, long regnum,
>     size_t p_size = scale << 4;
>     tdesc_create_vector (feature, "svep", element_type, p_size >> 3);
>   
> +  /* FPSR register type */
> +  tdesc_type_with_fields *type_with_fields
> +    = tdesc_create_flags (feature, "fpsr_flags", 4);
> +  tdesc_add_flag (type_with_fields, 0, "IOC");
> +  tdesc_add_flag (type_with_fields, 1, "DZC");
> +  tdesc_add_flag (type_with_fields, 2, "OFC");
> +  tdesc_add_flag (type_with_fields, 3, "UFC");
> +  tdesc_add_flag (type_with_fields, 4, "IXC");
> +  tdesc_add_flag (type_with_fields, 7, "IDC");
> +  tdesc_add_flag (type_with_fields, 27, "QC");
> +  tdesc_add_flag (type_with_fields, 28, "V");
> +  tdesc_add_flag (type_with_fields, 29, "C");
> +  tdesc_add_flag (type_with_fields, 30, "Z");
> +  tdesc_add_flag (type_with_fields, 31, "N");
> +
> +  /* FPCR register type */
> +  type_with_fields = tdesc_create_flags (feature, "fpcr_flags", 4);
> +  tdesc_add_flag (type_with_fields, 0, "FIZ");
> +  tdesc_add_flag (type_with_fields, 1, "AH");
> +  tdesc_add_flag (type_with_fields, 2, "NEP");
> +  tdesc_add_flag (type_with_fields, 8, "IOE");
> +  tdesc_add_flag (type_with_fields, 9, "DZE");
> +  tdesc_add_flag (type_with_fields, 10, "OFE");
> +  tdesc_add_flag (type_with_fields, 11, "UFE");
> +  tdesc_add_flag (type_with_fields, 12, "IXE");
> +  tdesc_add_flag (type_with_fields, 13, "EBF");
> +  tdesc_add_flag (type_with_fields, 15, "IDE");
> +  tdesc_add_bitfield (type_with_fields, "Len", 16, 18);
> +  tdesc_add_flag (type_with_fields, 19, "FZ16");
> +  tdesc_add_bitfield (type_with_fields, "Stride", 20, 21);
> +  tdesc_add_bitfield (type_with_fields, "RMode", 22, 23);
> +  tdesc_add_flag (type_with_fields, 24, "FZ");
> +  tdesc_add_flag (type_with_fields, 25, "DN");
> +  tdesc_add_flag (type_with_fields, 26, "AHP");
> +
>     tdesc_create_reg (feature, "z0", regnum++, 1, nullptr, z_size, "svez");
>     tdesc_create_reg (feature, "z1", regnum++, 1, nullptr, z_size, "svez");
>     tdesc_create_reg (feature, "z2", regnum++, 1, nullptr, z_size, "svez");
> @@ -72,8 +107,8 @@ create_feature_aarch64_sve (struct target_desc *result, long regnum,
>     tdesc_create_reg (feature, "z29", regnum++, 1, nullptr, z_size, "svez");
>     tdesc_create_reg (feature, "z30", regnum++, 1, nullptr, z_size, "svez");
>     tdesc_create_reg (feature, "z31", regnum++, 1, nullptr, z_size, "svez");
> -  tdesc_create_reg (feature, "fpsr", regnum++, 1, nullptr, 32, "int");
> -  tdesc_create_reg (feature, "fpcr", regnum++, 1, nullptr, 32, "int");
> +  tdesc_create_reg (feature, "fpsr", regnum++, 1, nullptr, 32, "fpsr_flags");
> +  tdesc_create_reg (feature, "fpcr", regnum++, 1, nullptr, 32, "fpcr_flags");
>     tdesc_create_reg (feature, "p0", regnum++, 1, nullptr, p_size, "svep");
>     tdesc_create_reg (feature, "p1", regnum++, 1, nullptr, p_size, "svep");
>     tdesc_create_reg (feature, "p2", regnum++, 1, nullptr, p_size, "svep");

Pushed now.

      reply	other threads:[~2022-10-04  8:15 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-23 10:39 Luis Machado
2022-10-04  8:15 ` Luis Machado [this message]

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