* [PATCH 4/8] gdb/riscv: Remove CSR feature file
2020-06-16 17:14 [PATCH 0/8] RISC-V target description and register handling fixes Andrew Burgess
` (2 preceding siblings ...)
2020-06-16 17:14 ` [PATCH 3/8] gdb/riscv: Take CSR names from target description Andrew Burgess
@ 2020-06-16 17:14 ` Andrew Burgess
2020-06-16 17:14 ` [PATCH 5/8] gdb/riscv: Improve support for matching against target descriptions Andrew Burgess
` (5 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Andrew Burgess @ 2020-06-16 17:14 UTC (permalink / raw)
To: gdb-patches; +Cc: Nelson Chu, Jim Wilson, Tom Tromey, palmer, Andrew Burgess
There is currently a bug in the RISC-V CSR/FPU feature files. The
CSRs containing the FPU status registers are mentioned in both the FPU
feature file and the CSR feature file.
My original thinking when adding the FPU feature file was that it made
more sense to group the FPU status registers with the other FPU
state. This opened up the possibility of debugging very
simple (possibly simulator only) targets that had little more than CPU
and FPU available for GDB to access.
When I then added code to automatically generate the CSR XML file I
forgot to filter out the FPU status CSRs, so these registers were
mentioned twice.
Now for GDB's default RISC-V target descriptions this doesn't actually
matter. I did consider adding the CSRs to the default target
description, but in the end I didn't bother. The reasoning again was
simplicity; the default target description is only to be used when the
target doesn't supply its own description, and NOT supplying the CSRs
actually serves to encourage targets to supply an accurate
description. Combine this with the fact that the CSRs change from
revision to revision, sometimes in non-backward compatible ways, then
having a "default" set of CSRs just feels like a path to confusion and
complaints.
However, having a broken CSR XML file in the GDB source tree has had
one negative effect, QEMU has copied this file into its source tree,
and is using this as its description that it passes to GDB. That is
QEMU announces the FPU status registers twice, once in the FPU
feature, and once in the CSR feature.
This commit starts along the path back to sanity by deleting the
default CSR XML files from within GDB. These files were not used in
any way by current GDB, so there is absolutely no loss of
functionality with this change.
gdb/ChangeLog:
* features/Makefile: Remove all references to the deleted files
below.
* features/riscv/32bit-csr.c: Deleted.
* features/riscv/32bit-csr.xml: Deleted.
* features/riscv/64bit-csr.c: Deleted.
* features/riscv/64bit-csr.xml: Deleted.
* features/riscv/rebuild-csr-xml.sh: Deleted.
---
gdb/ChangeLog | 10 +
gdb/features/Makefile | 6 -
gdb/features/riscv/32bit-csr.c | 253 --------------------------
gdb/features/riscv/32bit-csr.xml | 251 -------------------------
gdb/features/riscv/64bit-csr.c | 253 --------------------------
gdb/features/riscv/64bit-csr.xml | 186 -------------------
gdb/features/riscv/rebuild-csr-xml.sh | 37 ----
7 files changed, 10 insertions(+), 986 deletions(-)
delete mode 100644 gdb/features/riscv/32bit-csr.c
delete mode 100644 gdb/features/riscv/32bit-csr.xml
delete mode 100644 gdb/features/riscv/64bit-csr.c
delete mode 100644 gdb/features/riscv/64bit-csr.xml
delete mode 100755 gdb/features/riscv/rebuild-csr-xml.sh
diff --git a/gdb/features/Makefile b/gdb/features/Makefile
index cc65baa6eda..88236e5e946 100644
--- a/gdb/features/Makefile
+++ b/gdb/features/Makefile
@@ -232,10 +232,8 @@ FEATURE_XMLFILES = aarch64-core.xml \
i386/64bit-sse.xml \
i386/x32-core.xml \
riscv/32bit-cpu.xml \
- riscv/32bit-csr.xml \
riscv/32bit-fpu.xml \
riscv/64bit-cpu.xml \
- riscv/64bit-csr.xml \
riscv/64bit-fpu.xml \
rx.xml \
tic6x-c6xp.xml \
@@ -268,10 +266,6 @@ $(FEATURE_CFILES): %.c: %.xml.tmp
echo "</target>" >> $@.tmp
sh ../../move-if-change $@.tmp $@
-# Regenerate RISC-V CSR feature lists.
-riscv/32bit-csr.xml riscv/64bit-csr.xml: ../../include/opcode/riscv-opc.h
- ./riscv/rebuild-csr-xml.sh ../../include/opcode/riscv-opc.h ./riscv
-
# 'all' doesn't build the C files, so don't delete them in 'clean'
# either.
clean-cfiles:
diff --git a/gdb/features/riscv/32bit-csr.c b/gdb/features/riscv/32bit-csr.c
deleted file mode 100644
index d306bc8d293..00000000000
--- a/gdb/features/riscv/32bit-csr.c
+++ /dev/null
@@ -1,253 +0,0 @@
-/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro:
- Original: 32bit-csr.xml */
-
-#include "gdbsupport/tdesc.h"
-
-static int
-create_feature_riscv_32bit_csr (struct target_desc *result, long regnum)
-{
- struct tdesc_feature *feature;
-
- feature = tdesc_create_feature (result, "org.gnu.gdb.riscv.csr");
- tdesc_create_reg (feature, "ustatus", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "uie", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "utvec", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "uscratch", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "uepc", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "ucause", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "utval", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "uip", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "fflags", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "frm", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "fcsr", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "cycle", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "time", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "instret", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter3", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter4", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter5", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter6", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter7", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter8", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter9", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter10", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter11", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter12", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter13", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter14", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter15", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter16", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter17", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter18", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter19", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter20", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter21", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter22", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter23", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter24", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter25", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter26", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter27", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter28", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter29", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter30", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter31", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "cycleh", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "timeh", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "instreth", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter3h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter4h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter5h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter6h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter7h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter8h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter9h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter10h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter11h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter12h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter13h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter14h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter15h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter16h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter17h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter18h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter19h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter20h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter21h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter22h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter23h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter24h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter25h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter26h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter27h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter28h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter29h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter30h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hpmcounter31h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "sstatus", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "sedeleg", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "sideleg", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "sie", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "stvec", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "scounteren", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "sscratch", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "sepc", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "scause", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "stval", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "sip", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "satp", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mvendorid", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "marchid", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mimpid", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhartid", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mstatus", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "misa", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "medeleg", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mideleg", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mie", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mtvec", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mcounteren", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mscratch", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mepc", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mcause", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mtval", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mip", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "pmpcfg0", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "pmpcfg1", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "pmpcfg2", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "pmpcfg3", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "pmpaddr0", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "pmpaddr1", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "pmpaddr2", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "pmpaddr3", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "pmpaddr4", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "pmpaddr5", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "pmpaddr6", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "pmpaddr7", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "pmpaddr8", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "pmpaddr9", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "pmpaddr10", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "pmpaddr11", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "pmpaddr12", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "pmpaddr13", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "pmpaddr14", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "pmpaddr15", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mcycle", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "minstret", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter3", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter4", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter5", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter6", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter7", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter8", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter9", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter10", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter11", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter12", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter13", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter14", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter15", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter16", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter17", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter18", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter19", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter20", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter21", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter22", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter23", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter24", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter25", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter26", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter27", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter28", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter29", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter30", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter31", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mcycleh", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "minstreth", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter3h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter4h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter5h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter6h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter7h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter8h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter9h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter10h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter11h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter12h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter13h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter14h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter15h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter16h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter17h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter18h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter19h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter20h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter21h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter22h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter23h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter24h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter25h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter26h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter27h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter28h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter29h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter30h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmcounter31h", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmevent3", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmevent4", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmevent5", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmevent6", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmevent7", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmevent8", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmevent9", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmevent10", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmevent11", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmevent12", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmevent13", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmevent14", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmevent15", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmevent16", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmevent17", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmevent18", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmevent19", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmevent20", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmevent21", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmevent22", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmevent23", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmevent24", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmevent25", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmevent26", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmevent27", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmevent28", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmevent29", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmevent30", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhpmevent31", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "tselect", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "tdata1", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "tdata2", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "tdata3", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "dcsr", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "dpc", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "dscratch", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hstatus", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hedeleg", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hideleg", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hie", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "htvec", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hscratch", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hepc", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hcause", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hbadaddr", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "hip", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mbase", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mbound", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mibase", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mibound", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mdbase", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mdbound", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mucounteren", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mscounteren", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "mhcounteren", regnum++, 1, NULL, 32, "int");
- return regnum;
-}
diff --git a/gdb/features/riscv/32bit-csr.xml b/gdb/features/riscv/32bit-csr.xml
deleted file mode 100644
index 8173eebda1c..00000000000
--- a/gdb/features/riscv/32bit-csr.xml
+++ /dev/null
@@ -1,251 +0,0 @@
-<?xml version="1.0"?>
-<!-- Copyright (C) 2018-2020 Free Software Foundation, Inc.
-
- Copying and distribution of this file, with or without modification,
- are permitted in any medium without royalty provided the copyright
- notice and this notice are preserved. -->
-
-<!DOCTYPE feature SYSTEM "gdb-target.dtd">
-<feature name="org.gnu.gdb.riscv.csr">
- <reg name="ustatus" bitsize="32"/>
- <reg name="uie" bitsize="32"/>
- <reg name="utvec" bitsize="32"/>
- <reg name="uscratch" bitsize="32"/>
- <reg name="uepc" bitsize="32"/>
- <reg name="ucause" bitsize="32"/>
- <reg name="utval" bitsize="32"/>
- <reg name="uip" bitsize="32"/>
- <reg name="fflags" bitsize="32"/>
- <reg name="frm" bitsize="32"/>
- <reg name="fcsr" bitsize="32"/>
- <reg name="cycle" bitsize="32"/>
- <reg name="time" bitsize="32"/>
- <reg name="instret" bitsize="32"/>
- <reg name="hpmcounter3" bitsize="32"/>
- <reg name="hpmcounter4" bitsize="32"/>
- <reg name="hpmcounter5" bitsize="32"/>
- <reg name="hpmcounter6" bitsize="32"/>
- <reg name="hpmcounter7" bitsize="32"/>
- <reg name="hpmcounter8" bitsize="32"/>
- <reg name="hpmcounter9" bitsize="32"/>
- <reg name="hpmcounter10" bitsize="32"/>
- <reg name="hpmcounter11" bitsize="32"/>
- <reg name="hpmcounter12" bitsize="32"/>
- <reg name="hpmcounter13" bitsize="32"/>
- <reg name="hpmcounter14" bitsize="32"/>
- <reg name="hpmcounter15" bitsize="32"/>
- <reg name="hpmcounter16" bitsize="32"/>
- <reg name="hpmcounter17" bitsize="32"/>
- <reg name="hpmcounter18" bitsize="32"/>
- <reg name="hpmcounter19" bitsize="32"/>
- <reg name="hpmcounter20" bitsize="32"/>
- <reg name="hpmcounter21" bitsize="32"/>
- <reg name="hpmcounter22" bitsize="32"/>
- <reg name="hpmcounter23" bitsize="32"/>
- <reg name="hpmcounter24" bitsize="32"/>
- <reg name="hpmcounter25" bitsize="32"/>
- <reg name="hpmcounter26" bitsize="32"/>
- <reg name="hpmcounter27" bitsize="32"/>
- <reg name="hpmcounter28" bitsize="32"/>
- <reg name="hpmcounter29" bitsize="32"/>
- <reg name="hpmcounter30" bitsize="32"/>
- <reg name="hpmcounter31" bitsize="32"/>
- <reg name="cycleh" bitsize="32"/>
- <reg name="timeh" bitsize="32"/>
- <reg name="instreth" bitsize="32"/>
- <reg name="hpmcounter3h" bitsize="32"/>
- <reg name="hpmcounter4h" bitsize="32"/>
- <reg name="hpmcounter5h" bitsize="32"/>
- <reg name="hpmcounter6h" bitsize="32"/>
- <reg name="hpmcounter7h" bitsize="32"/>
- <reg name="hpmcounter8h" bitsize="32"/>
- <reg name="hpmcounter9h" bitsize="32"/>
- <reg name="hpmcounter10h" bitsize="32"/>
- <reg name="hpmcounter11h" bitsize="32"/>
- <reg name="hpmcounter12h" bitsize="32"/>
- <reg name="hpmcounter13h" bitsize="32"/>
- <reg name="hpmcounter14h" bitsize="32"/>
- <reg name="hpmcounter15h" bitsize="32"/>
- <reg name="hpmcounter16h" bitsize="32"/>
- <reg name="hpmcounter17h" bitsize="32"/>
- <reg name="hpmcounter18h" bitsize="32"/>
- <reg name="hpmcounter19h" bitsize="32"/>
- <reg name="hpmcounter20h" bitsize="32"/>
- <reg name="hpmcounter21h" bitsize="32"/>
- <reg name="hpmcounter22h" bitsize="32"/>
- <reg name="hpmcounter23h" bitsize="32"/>
- <reg name="hpmcounter24h" bitsize="32"/>
- <reg name="hpmcounter25h" bitsize="32"/>
- <reg name="hpmcounter26h" bitsize="32"/>
- <reg name="hpmcounter27h" bitsize="32"/>
- <reg name="hpmcounter28h" bitsize="32"/>
- <reg name="hpmcounter29h" bitsize="32"/>
- <reg name="hpmcounter30h" bitsize="32"/>
- <reg name="hpmcounter31h" bitsize="32"/>
- <reg name="sstatus" bitsize="32"/>
- <reg name="sedeleg" bitsize="32"/>
- <reg name="sideleg" bitsize="32"/>
- <reg name="sie" bitsize="32"/>
- <reg name="stvec" bitsize="32"/>
- <reg name="scounteren" bitsize="32"/>
- <reg name="sscratch" bitsize="32"/>
- <reg name="sepc" bitsize="32"/>
- <reg name="scause" bitsize="32"/>
- <reg name="stval" bitsize="32"/>
- <reg name="sip" bitsize="32"/>
- <reg name="satp" bitsize="32"/>
- <reg name="mvendorid" bitsize="32"/>
- <reg name="marchid" bitsize="32"/>
- <reg name="mimpid" bitsize="32"/>
- <reg name="mhartid" bitsize="32"/>
- <reg name="mstatus" bitsize="32"/>
- <reg name="misa" bitsize="32"/>
- <reg name="medeleg" bitsize="32"/>
- <reg name="mideleg" bitsize="32"/>
- <reg name="mie" bitsize="32"/>
- <reg name="mtvec" bitsize="32"/>
- <reg name="mcounteren" bitsize="32"/>
- <reg name="mscratch" bitsize="32"/>
- <reg name="mepc" bitsize="32"/>
- <reg name="mcause" bitsize="32"/>
- <reg name="mtval" bitsize="32"/>
- <reg name="mip" bitsize="32"/>
- <reg name="pmpcfg0" bitsize="32"/>
- <reg name="pmpcfg1" bitsize="32"/>
- <reg name="pmpcfg2" bitsize="32"/>
- <reg name="pmpcfg3" bitsize="32"/>
- <reg name="pmpaddr0" bitsize="32"/>
- <reg name="pmpaddr1" bitsize="32"/>
- <reg name="pmpaddr2" bitsize="32"/>
- <reg name="pmpaddr3" bitsize="32"/>
- <reg name="pmpaddr4" bitsize="32"/>
- <reg name="pmpaddr5" bitsize="32"/>
- <reg name="pmpaddr6" bitsize="32"/>
- <reg name="pmpaddr7" bitsize="32"/>
- <reg name="pmpaddr8" bitsize="32"/>
- <reg name="pmpaddr9" bitsize="32"/>
- <reg name="pmpaddr10" bitsize="32"/>
- <reg name="pmpaddr11" bitsize="32"/>
- <reg name="pmpaddr12" bitsize="32"/>
- <reg name="pmpaddr13" bitsize="32"/>
- <reg name="pmpaddr14" bitsize="32"/>
- <reg name="pmpaddr15" bitsize="32"/>
- <reg name="mcycle" bitsize="32"/>
- <reg name="minstret" bitsize="32"/>
- <reg name="mhpmcounter3" bitsize="32"/>
- <reg name="mhpmcounter4" bitsize="32"/>
- <reg name="mhpmcounter5" bitsize="32"/>
- <reg name="mhpmcounter6" bitsize="32"/>
- <reg name="mhpmcounter7" bitsize="32"/>
- <reg name="mhpmcounter8" bitsize="32"/>
- <reg name="mhpmcounter9" bitsize="32"/>
- <reg name="mhpmcounter10" bitsize="32"/>
- <reg name="mhpmcounter11" bitsize="32"/>
- <reg name="mhpmcounter12" bitsize="32"/>
- <reg name="mhpmcounter13" bitsize="32"/>
- <reg name="mhpmcounter14" bitsize="32"/>
- <reg name="mhpmcounter15" bitsize="32"/>
- <reg name="mhpmcounter16" bitsize="32"/>
- <reg name="mhpmcounter17" bitsize="32"/>
- <reg name="mhpmcounter18" bitsize="32"/>
- <reg name="mhpmcounter19" bitsize="32"/>
- <reg name="mhpmcounter20" bitsize="32"/>
- <reg name="mhpmcounter21" bitsize="32"/>
- <reg name="mhpmcounter22" bitsize="32"/>
- <reg name="mhpmcounter23" bitsize="32"/>
- <reg name="mhpmcounter24" bitsize="32"/>
- <reg name="mhpmcounter25" bitsize="32"/>
- <reg name="mhpmcounter26" bitsize="32"/>
- <reg name="mhpmcounter27" bitsize="32"/>
- <reg name="mhpmcounter28" bitsize="32"/>
- <reg name="mhpmcounter29" bitsize="32"/>
- <reg name="mhpmcounter30" bitsize="32"/>
- <reg name="mhpmcounter31" bitsize="32"/>
- <reg name="mcycleh" bitsize="32"/>
- <reg name="minstreth" bitsize="32"/>
- <reg name="mhpmcounter3h" bitsize="32"/>
- <reg name="mhpmcounter4h" bitsize="32"/>
- <reg name="mhpmcounter5h" bitsize="32"/>
- <reg name="mhpmcounter6h" bitsize="32"/>
- <reg name="mhpmcounter7h" bitsize="32"/>
- <reg name="mhpmcounter8h" bitsize="32"/>
- <reg name="mhpmcounter9h" bitsize="32"/>
- <reg name="mhpmcounter10h" bitsize="32"/>
- <reg name="mhpmcounter11h" bitsize="32"/>
- <reg name="mhpmcounter12h" bitsize="32"/>
- <reg name="mhpmcounter13h" bitsize="32"/>
- <reg name="mhpmcounter14h" bitsize="32"/>
- <reg name="mhpmcounter15h" bitsize="32"/>
- <reg name="mhpmcounter16h" bitsize="32"/>
- <reg name="mhpmcounter17h" bitsize="32"/>
- <reg name="mhpmcounter18h" bitsize="32"/>
- <reg name="mhpmcounter19h" bitsize="32"/>
- <reg name="mhpmcounter20h" bitsize="32"/>
- <reg name="mhpmcounter21h" bitsize="32"/>
- <reg name="mhpmcounter22h" bitsize="32"/>
- <reg name="mhpmcounter23h" bitsize="32"/>
- <reg name="mhpmcounter24h" bitsize="32"/>
- <reg name="mhpmcounter25h" bitsize="32"/>
- <reg name="mhpmcounter26h" bitsize="32"/>
- <reg name="mhpmcounter27h" bitsize="32"/>
- <reg name="mhpmcounter28h" bitsize="32"/>
- <reg name="mhpmcounter29h" bitsize="32"/>
- <reg name="mhpmcounter30h" bitsize="32"/>
- <reg name="mhpmcounter31h" bitsize="32"/>
- <reg name="mcountinhibit" bitsize="32"/>
- <reg name="mhpmevent3" bitsize="32"/>
- <reg name="mhpmevent4" bitsize="32"/>
- <reg name="mhpmevent5" bitsize="32"/>
- <reg name="mhpmevent6" bitsize="32"/>
- <reg name="mhpmevent7" bitsize="32"/>
- <reg name="mhpmevent8" bitsize="32"/>
- <reg name="mhpmevent9" bitsize="32"/>
- <reg name="mhpmevent10" bitsize="32"/>
- <reg name="mhpmevent11" bitsize="32"/>
- <reg name="mhpmevent12" bitsize="32"/>
- <reg name="mhpmevent13" bitsize="32"/>
- <reg name="mhpmevent14" bitsize="32"/>
- <reg name="mhpmevent15" bitsize="32"/>
- <reg name="mhpmevent16" bitsize="32"/>
- <reg name="mhpmevent17" bitsize="32"/>
- <reg name="mhpmevent18" bitsize="32"/>
- <reg name="mhpmevent19" bitsize="32"/>
- <reg name="mhpmevent20" bitsize="32"/>
- <reg name="mhpmevent21" bitsize="32"/>
- <reg name="mhpmevent22" bitsize="32"/>
- <reg name="mhpmevent23" bitsize="32"/>
- <reg name="mhpmevent24" bitsize="32"/>
- <reg name="mhpmevent25" bitsize="32"/>
- <reg name="mhpmevent26" bitsize="32"/>
- <reg name="mhpmevent27" bitsize="32"/>
- <reg name="mhpmevent28" bitsize="32"/>
- <reg name="mhpmevent29" bitsize="32"/>
- <reg name="mhpmevent30" bitsize="32"/>
- <reg name="mhpmevent31" bitsize="32"/>
- <reg name="tselect" bitsize="32"/>
- <reg name="tdata1" bitsize="32"/>
- <reg name="tdata2" bitsize="32"/>
- <reg name="tdata3" bitsize="32"/>
- <reg name="dcsr" bitsize="32"/>
- <reg name="dpc" bitsize="32"/>
- <reg name="dscratch0" bitsize="32"/>
- <reg name="dscratch1" bitsize="32"/>
- <reg name="hstatus" bitsize="32"/>
- <reg name="hedeleg" bitsize="32"/>
- <reg name="hideleg" bitsize="32"/>
- <reg name="hie" bitsize="32"/>
- <reg name="htvec" bitsize="32"/>
- <reg name="hscratch" bitsize="32"/>
- <reg name="hepc" bitsize="32"/>
- <reg name="hcause" bitsize="32"/>
- <reg name="hbadaddr" bitsize="32"/>
- <reg name="hip" bitsize="32"/>
- <reg name="mbase" bitsize="32"/>
- <reg name="mbound" bitsize="32"/>
- <reg name="mibase" bitsize="32"/>
- <reg name="mibound" bitsize="32"/>
- <reg name="mdbase" bitsize="32"/>
- <reg name="mdbound" bitsize="32"/>
- <reg name="mscounteren" bitsize="32"/>
- <reg name="mhcounteren" bitsize="32"/>
-</feature>
diff --git a/gdb/features/riscv/64bit-csr.c b/gdb/features/riscv/64bit-csr.c
deleted file mode 100644
index e46a77f3051..00000000000
--- a/gdb/features/riscv/64bit-csr.c
+++ /dev/null
@@ -1,253 +0,0 @@
-/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro:
- Original: 64bit-csr.xml */
-
-#include "gdbsupport/tdesc.h"
-
-static int
-create_feature_riscv_64bit_csr (struct target_desc *result, long regnum)
-{
- struct tdesc_feature *feature;
-
- feature = tdesc_create_feature (result, "org.gnu.gdb.riscv.csr");
- tdesc_create_reg (feature, "ustatus", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "uie", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "utvec", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "uscratch", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "uepc", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "ucause", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "utval", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "uip", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "fflags", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "frm", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "fcsr", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "cycle", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "time", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "instret", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter3", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter4", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter5", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter6", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter7", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter8", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter9", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter10", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter11", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter12", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter13", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter14", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter15", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter16", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter17", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter18", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter19", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter20", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter21", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter22", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter23", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter24", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter25", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter26", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter27", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter28", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter29", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter30", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter31", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "cycleh", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "timeh", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "instreth", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter3h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter4h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter5h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter6h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter7h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter8h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter9h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter10h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter11h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter12h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter13h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter14h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter15h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter16h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter17h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter18h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter19h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter20h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter21h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter22h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter23h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter24h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter25h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter26h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter27h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter28h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter29h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter30h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hpmcounter31h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "sstatus", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "sedeleg", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "sideleg", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "sie", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "stvec", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "scounteren", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "sscratch", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "sepc", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "scause", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "stval", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "sip", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "satp", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mvendorid", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "marchid", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mimpid", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhartid", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mstatus", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "misa", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "medeleg", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mideleg", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mie", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mtvec", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mcounteren", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mscratch", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mepc", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mcause", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mtval", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mip", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "pmpcfg0", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "pmpcfg1", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "pmpcfg2", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "pmpcfg3", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "pmpaddr0", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "pmpaddr1", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "pmpaddr2", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "pmpaddr3", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "pmpaddr4", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "pmpaddr5", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "pmpaddr6", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "pmpaddr7", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "pmpaddr8", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "pmpaddr9", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "pmpaddr10", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "pmpaddr11", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "pmpaddr12", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "pmpaddr13", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "pmpaddr14", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "pmpaddr15", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mcycle", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "minstret", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter3", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter4", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter5", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter6", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter7", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter8", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter9", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter10", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter11", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter12", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter13", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter14", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter15", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter16", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter17", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter18", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter19", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter20", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter21", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter22", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter23", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter24", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter25", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter26", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter27", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter28", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter29", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter30", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter31", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mcycleh", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "minstreth", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter3h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter4h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter5h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter6h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter7h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter8h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter9h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter10h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter11h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter12h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter13h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter14h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter15h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter16h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter17h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter18h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter19h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter20h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter21h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter22h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter23h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter24h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter25h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter26h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter27h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter28h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter29h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter30h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmcounter31h", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmevent3", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmevent4", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmevent5", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmevent6", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmevent7", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmevent8", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmevent9", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmevent10", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmevent11", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmevent12", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmevent13", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmevent14", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmevent15", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmevent16", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmevent17", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmevent18", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmevent19", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmevent20", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmevent21", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmevent22", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmevent23", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmevent24", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmevent25", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmevent26", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmevent27", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmevent28", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmevent29", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmevent30", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhpmevent31", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "tselect", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "tdata1", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "tdata2", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "tdata3", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "dcsr", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "dpc", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "dscratch", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hstatus", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hedeleg", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hideleg", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hie", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "htvec", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hscratch", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hepc", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hcause", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hbadaddr", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "hip", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mbase", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mbound", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mibase", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mibound", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mdbase", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mdbound", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mucounteren", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mscounteren", regnum++, 1, NULL, 64, "int");
- tdesc_create_reg (feature, "mhcounteren", regnum++, 1, NULL, 64, "int");
- return regnum;
-}
diff --git a/gdb/features/riscv/64bit-csr.xml b/gdb/features/riscv/64bit-csr.xml
deleted file mode 100644
index ed28964ac35..00000000000
--- a/gdb/features/riscv/64bit-csr.xml
+++ /dev/null
@@ -1,186 +0,0 @@
-<?xml version="1.0"?>
-<!-- Copyright (C) 2018-2020 Free Software Foundation, Inc.
-
- Copying and distribution of this file, with or without modification,
- are permitted in any medium without royalty provided the copyright
- notice and this notice are preserved. -->
-
-<!DOCTYPE feature SYSTEM "gdb-target.dtd">
-<feature name="org.gnu.gdb.riscv.csr">
- <reg name="ustatus" bitsize="64"/>
- <reg name="uie" bitsize="64"/>
- <reg name="utvec" bitsize="64"/>
- <reg name="uscratch" bitsize="64"/>
- <reg name="uepc" bitsize="64"/>
- <reg name="ucause" bitsize="64"/>
- <reg name="utval" bitsize="64"/>
- <reg name="uip" bitsize="64"/>
- <reg name="fflags" bitsize="64"/>
- <reg name="frm" bitsize="64"/>
- <reg name="fcsr" bitsize="64"/>
- <reg name="cycle" bitsize="64"/>
- <reg name="time" bitsize="64"/>
- <reg name="instret" bitsize="64"/>
- <reg name="hpmcounter3" bitsize="64"/>
- <reg name="hpmcounter4" bitsize="64"/>
- <reg name="hpmcounter5" bitsize="64"/>
- <reg name="hpmcounter6" bitsize="64"/>
- <reg name="hpmcounter7" bitsize="64"/>
- <reg name="hpmcounter8" bitsize="64"/>
- <reg name="hpmcounter9" bitsize="64"/>
- <reg name="hpmcounter10" bitsize="64"/>
- <reg name="hpmcounter11" bitsize="64"/>
- <reg name="hpmcounter12" bitsize="64"/>
- <reg name="hpmcounter13" bitsize="64"/>
- <reg name="hpmcounter14" bitsize="64"/>
- <reg name="hpmcounter15" bitsize="64"/>
- <reg name="hpmcounter16" bitsize="64"/>
- <reg name="hpmcounter17" bitsize="64"/>
- <reg name="hpmcounter18" bitsize="64"/>
- <reg name="hpmcounter19" bitsize="64"/>
- <reg name="hpmcounter20" bitsize="64"/>
- <reg name="hpmcounter21" bitsize="64"/>
- <reg name="hpmcounter22" bitsize="64"/>
- <reg name="hpmcounter23" bitsize="64"/>
- <reg name="hpmcounter24" bitsize="64"/>
- <reg name="hpmcounter25" bitsize="64"/>
- <reg name="hpmcounter26" bitsize="64"/>
- <reg name="hpmcounter27" bitsize="64"/>
- <reg name="hpmcounter28" bitsize="64"/>
- <reg name="hpmcounter29" bitsize="64"/>
- <reg name="hpmcounter30" bitsize="64"/>
- <reg name="hpmcounter31" bitsize="64"/>
- <reg name="sstatus" bitsize="64"/>
- <reg name="sedeleg" bitsize="64"/>
- <reg name="sideleg" bitsize="64"/>
- <reg name="sie" bitsize="64"/>
- <reg name="stvec" bitsize="64"/>
- <reg name="scounteren" bitsize="64"/>
- <reg name="sscratch" bitsize="64"/>
- <reg name="sepc" bitsize="64"/>
- <reg name="scause" bitsize="64"/>
- <reg name="stval" bitsize="64"/>
- <reg name="sip" bitsize="64"/>
- <reg name="satp" bitsize="64"/>
- <reg name="mvendorid" bitsize="64"/>
- <reg name="marchid" bitsize="64"/>
- <reg name="mimpid" bitsize="64"/>
- <reg name="mhartid" bitsize="64"/>
- <reg name="mstatus" bitsize="64"/>
- <reg name="misa" bitsize="64"/>
- <reg name="medeleg" bitsize="64"/>
- <reg name="mideleg" bitsize="64"/>
- <reg name="mie" bitsize="64"/>
- <reg name="mtvec" bitsize="64"/>
- <reg name="mcounteren" bitsize="64"/>
- <reg name="mscratch" bitsize="64"/>
- <reg name="mepc" bitsize="64"/>
- <reg name="mcause" bitsize="64"/>
- <reg name="mtval" bitsize="64"/>
- <reg name="mip" bitsize="64"/>
- <reg name="pmpcfg0" bitsize="64"/>
- <reg name="pmpcfg2" bitsize="64"/>
- <reg name="pmpaddr0" bitsize="64"/>
- <reg name="pmpaddr1" bitsize="64"/>
- <reg name="pmpaddr2" bitsize="64"/>
- <reg name="pmpaddr3" bitsize="64"/>
- <reg name="pmpaddr4" bitsize="64"/>
- <reg name="pmpaddr5" bitsize="64"/>
- <reg name="pmpaddr6" bitsize="64"/>
- <reg name="pmpaddr7" bitsize="64"/>
- <reg name="pmpaddr8" bitsize="64"/>
- <reg name="pmpaddr9" bitsize="64"/>
- <reg name="pmpaddr10" bitsize="64"/>
- <reg name="pmpaddr11" bitsize="64"/>
- <reg name="pmpaddr12" bitsize="64"/>
- <reg name="pmpaddr13" bitsize="64"/>
- <reg name="pmpaddr14" bitsize="64"/>
- <reg name="pmpaddr15" bitsize="64"/>
- <reg name="mcycle" bitsize="64"/>
- <reg name="minstret" bitsize="64"/>
- <reg name="mhpmcounter3" bitsize="64"/>
- <reg name="mhpmcounter4" bitsize="64"/>
- <reg name="mhpmcounter5" bitsize="64"/>
- <reg name="mhpmcounter6" bitsize="64"/>
- <reg name="mhpmcounter7" bitsize="64"/>
- <reg name="mhpmcounter8" bitsize="64"/>
- <reg name="mhpmcounter9" bitsize="64"/>
- <reg name="mhpmcounter10" bitsize="64"/>
- <reg name="mhpmcounter11" bitsize="64"/>
- <reg name="mhpmcounter12" bitsize="64"/>
- <reg name="mhpmcounter13" bitsize="64"/>
- <reg name="mhpmcounter14" bitsize="64"/>
- <reg name="mhpmcounter15" bitsize="64"/>
- <reg name="mhpmcounter16" bitsize="64"/>
- <reg name="mhpmcounter17" bitsize="64"/>
- <reg name="mhpmcounter18" bitsize="64"/>
- <reg name="mhpmcounter19" bitsize="64"/>
- <reg name="mhpmcounter20" bitsize="64"/>
- <reg name="mhpmcounter21" bitsize="64"/>
- <reg name="mhpmcounter22" bitsize="64"/>
- <reg name="mhpmcounter23" bitsize="64"/>
- <reg name="mhpmcounter24" bitsize="64"/>
- <reg name="mhpmcounter25" bitsize="64"/>
- <reg name="mhpmcounter26" bitsize="64"/>
- <reg name="mhpmcounter27" bitsize="64"/>
- <reg name="mhpmcounter28" bitsize="64"/>
- <reg name="mhpmcounter29" bitsize="64"/>
- <reg name="mhpmcounter30" bitsize="64"/>
- <reg name="mhpmcounter31" bitsize="64"/>
- <reg name="mcountinhibit" bitsize="64"/>
- <reg name="mhpmevent3" bitsize="64"/>
- <reg name="mhpmevent4" bitsize="64"/>
- <reg name="mhpmevent5" bitsize="64"/>
- <reg name="mhpmevent6" bitsize="64"/>
- <reg name="mhpmevent7" bitsize="64"/>
- <reg name="mhpmevent8" bitsize="64"/>
- <reg name="mhpmevent9" bitsize="64"/>
- <reg name="mhpmevent10" bitsize="64"/>
- <reg name="mhpmevent11" bitsize="64"/>
- <reg name="mhpmevent12" bitsize="64"/>
- <reg name="mhpmevent13" bitsize="64"/>
- <reg name="mhpmevent14" bitsize="64"/>
- <reg name="mhpmevent15" bitsize="64"/>
- <reg name="mhpmevent16" bitsize="64"/>
- <reg name="mhpmevent17" bitsize="64"/>
- <reg name="mhpmevent18" bitsize="64"/>
- <reg name="mhpmevent19" bitsize="64"/>
- <reg name="mhpmevent20" bitsize="64"/>
- <reg name="mhpmevent21" bitsize="64"/>
- <reg name="mhpmevent22" bitsize="64"/>
- <reg name="mhpmevent23" bitsize="64"/>
- <reg name="mhpmevent24" bitsize="64"/>
- <reg name="mhpmevent25" bitsize="64"/>
- <reg name="mhpmevent26" bitsize="64"/>
- <reg name="mhpmevent27" bitsize="64"/>
- <reg name="mhpmevent28" bitsize="64"/>
- <reg name="mhpmevent29" bitsize="64"/>
- <reg name="mhpmevent30" bitsize="64"/>
- <reg name="mhpmevent31" bitsize="64"/>
- <reg name="tselect" bitsize="64"/>
- <reg name="tdata1" bitsize="64"/>
- <reg name="tdata2" bitsize="64"/>
- <reg name="tdata3" bitsize="64"/>
- <reg name="dcsr" bitsize="64"/>
- <reg name="dpc" bitsize="64"/>
- <reg name="dscratch0" bitsize="64"/>
- <reg name="dscratch1" bitsize="64"/>
- <reg name="hstatus" bitsize="64"/>
- <reg name="hedeleg" bitsize="64"/>
- <reg name="hideleg" bitsize="64"/>
- <reg name="hie" bitsize="64"/>
- <reg name="htvec" bitsize="64"/>
- <reg name="hscratch" bitsize="64"/>
- <reg name="hepc" bitsize="64"/>
- <reg name="hcause" bitsize="64"/>
- <reg name="hbadaddr" bitsize="64"/>
- <reg name="hip" bitsize="64"/>
- <reg name="mbase" bitsize="64"/>
- <reg name="mbound" bitsize="64"/>
- <reg name="mibase" bitsize="64"/>
- <reg name="mibound" bitsize="64"/>
- <reg name="mdbase" bitsize="64"/>
- <reg name="mdbound" bitsize="64"/>
- <reg name="mscounteren" bitsize="64"/>
- <reg name="mhcounteren" bitsize="64"/>
-</feature>
diff --git a/gdb/features/riscv/rebuild-csr-xml.sh b/gdb/features/riscv/rebuild-csr-xml.sh
deleted file mode 100755
index bff79b0371f..00000000000
--- a/gdb/features/riscv/rebuild-csr-xml.sh
+++ /dev/null
@@ -1,37 +0,0 @@
-#! /bin/bash
-
-RISCV_OPC_FILE=$1
-RISCV_FEATURE_DIR=$2
-
-function gen_csr_xml ()
-{
- bitsize=$1
-
- cat <<EOF
-<?xml version="1.0"?>
-<!-- Copyright (C) 2018-2020 Free Software Foundation, Inc.
-
- Copying and distribution of this file, with or without modification,
- are permitted in any medium without royalty provided the copyright
- notice and this notice are preserved. -->
-
-<!DOCTYPE feature SYSTEM "gdb-target.dtd">
-<feature name="org.gnu.gdb.riscv.csr">
-EOF
-
-if [ "$bitsize" = "64" ]; then
- grep "^DECLARE_CSR(" ${RISCV_OPC_FILE} \
- | sed /CSR_CLASS_.*_32/d \
- | sed -e "s!DECLARE_CSR(\(.*\), .*, .*, .*, .*! <reg name=\"\1\" bitsize=\"$bitsize\"/>!"
-
- echo "</feature>"
-else
- grep "^DECLARE_CSR(" ${RISCV_OPC_FILE} \
- | sed -e "s!DECLARE_CSR(\(.*\), .*, .*, .*, .*! <reg name=\"\1\" bitsize=\"$bitsize\"/>!"
-
- echo "</feature>"
-fi
-}
-
-gen_csr_xml 32 > ${RISCV_FEATURE_DIR}/32bit-csr.xml
-gen_csr_xml 64 > ${RISCV_FEATURE_DIR}/64bit-csr.xml
--
2.25.4
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 5/8] gdb/riscv: Improve support for matching against target descriptions
2020-06-16 17:14 [PATCH 0/8] RISC-V target description and register handling fixes Andrew Burgess
` (3 preceding siblings ...)
2020-06-16 17:14 ` [PATCH 4/8] gdb/riscv: Remove CSR feature file Andrew Burgess
@ 2020-06-16 17:14 ` Andrew Burgess
2020-06-16 17:14 ` [PATCH 6/8] gdb: Extend target description processing of unknown registers Andrew Burgess
` (4 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Andrew Burgess @ 2020-06-16 17:14 UTC (permalink / raw)
To: gdb-patches; +Cc: Nelson Chu, Jim Wilson, Tom Tromey, palmer, Andrew Burgess
For the RISC-V target it is desirable if the three floating pointer
status CSRs fflags, frm, and fcsr can be placed into either the FPU
feature or the CSR feature. This allows different targets to build
the features in a way that better reflects their target.
The change to support this within GDB is fairly simple, so this is
done in this commit, and some tests added to check this new
functionality.
gdb/ChangeLog:
* riscv-tdep.c (value_of_riscv_user_reg): Moved to here from later
in the file.
(class riscv_pending_register_alias): Likewise.
(riscv_register_feature::register_info): Change 'required_p' field
to 'required', and change its type. Add 'check' member function.
(riscv_register_feature::register_info::check): Define new member
function.
(riscv_xreg_feature): Change initialisation of 'required' field.
(riscv_freg_feature): Likewise.
(riscv_virtual_feature): Likewise.
(riscv_csr_feature): Likewise.
(riscv_check_tdesc_feature): Take extra parameter, the csr
tdesc_feature, rewrite the function to use the new
riscv_register_feature::register_info::check function.
(riscv_gdbarch_init): Pass the csr tdesc_feature where needed.
gdb/testsuite/ChangeLog:
* gdb.arch/riscv-tdesc-loading-01.xml: New file.
* gdb.arch/riscv-tdesc-loading-02.xml: New file.
* gdb.arch/riscv-tdesc-loading-03.xml: New file.
* gdb.arch/riscv-tdesc-loading-04.xml: New file.
* gdb.arch/riscv-tdesc-loading.exp: New file.
---
gdb/ChangeLog | 18 +
gdb/riscv-tdep.c | 335 ++++++++++--------
gdb/testsuite/ChangeLog | 8 +
.../gdb.arch/riscv-tdesc-loading-01.xml | 83 +++++
.../gdb.arch/riscv-tdesc-loading-02.xml | 81 +++++
.../gdb.arch/riscv-tdesc-loading-03.xml | 79 +++++
.../gdb.arch/riscv-tdesc-loading-04.xml | 77 ++++
.../gdb.arch/riscv-tdesc-loading.exp | 39 ++
8 files changed, 578 insertions(+), 142 deletions(-)
create mode 100644 gdb/testsuite/gdb.arch/riscv-tdesc-loading-01.xml
create mode 100644 gdb/testsuite/gdb.arch/riscv-tdesc-loading-02.xml
create mode 100644 gdb/testsuite/gdb.arch/riscv-tdesc-loading-03.xml
create mode 100644 gdb/testsuite/gdb.arch/riscv-tdesc-loading-04.xml
create mode 100644 gdb/testsuite/gdb.arch/riscv-tdesc-loading.exp
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index b136cbdfbf4..f161c1ac625 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -101,6 +101,66 @@ struct riscv_unwind_cache
static reggroup *csr_reggroup = NULL;
+/* Callback function for user_reg_add. */
+
+static struct value *
+value_of_riscv_user_reg (struct frame_info *frame, const void *baton)
+{
+ const int *reg_p = (const int *) baton;
+ return value_of_register (*reg_p, frame);
+}
+
+/* Information about a register alias that needs to be set up for this
+ target. These are collected when the target's XML description is
+ analysed, and then processed later, once the gdbarch has been created. */
+
+class riscv_pending_register_alias
+{
+public:
+ /* Constructor. */
+
+ riscv_pending_register_alias (const char *name, const void *baton)
+ : m_name (name),
+ m_baton (baton)
+ { /* Nothing. */ }
+
+ /* Convert this into a user register for GDBARCH. */
+
+ void create (struct gdbarch *gdbarch) const
+ {
+ user_reg_add (gdbarch, m_name, value_of_riscv_user_reg, m_baton);
+ }
+
+private:
+ /* The name for this alias. */
+ const char *m_name;
+
+ /* The baton value for passing to user_reg_add. This must point to some
+ data that will live for at least as long as the gdbarch object to
+ which the user register is attached. */
+ const void *m_baton;
+};
+
+/* Registers in the RISCV_REGISTER_FEATURE lists below are either optional,
+ or required. For example the $pc register is always going to be a
+ required register, you can't do much debugging without that. In
+ contrast, most of the CSRs are optional, GDB doesn't require them in
+ order to have a useful debug session. This enum models the difference
+ between these register types. */
+
+enum riscv_register_required_status
+{
+ /* This register is optional within this feature. */
+ RISCV_REG_OPTIONAL,
+
+ /* This register is required within this feature. */
+ RISCV_REG_REQUIRED,
+
+ /* This register is required, the register must either be in this
+ feature, or it could appear within the CSR feature. */
+ RISCV_REG_REQUIRED_MAYBE_CSR
+};
+
/* A set of registers that we expect to find in a tdesc_feature. These
are use in RISCV_GDBARCH_INIT when processing the target description. */
@@ -117,8 +177,18 @@ struct riscv_register_feature
register. */
std::vector<const char *> names;
- /* When true this register is required in this feature set. */
- bool required_p;
+ /* Is this register required within this feature? In some cases the
+ register could be required, but might also be in the CSR feature. */
+ riscv_register_required_status required;
+
+ /* Look in FEATURE for a register with a name from this classes names
+ list. If the register is found then register its number with
+ TDESC_DATA and add all its aliases to the ALIASES list. REG_SET is
+ used to help create the aliases. */
+ bool check (struct tdesc_arch_data *tdesc_data,
+ const struct tdesc_feature *feature,
+ const struct riscv_register_feature *reg_set,
+ std::vector<riscv_pending_register_alias> *aliases) const;
};
/* The name for this feature. This is the name used to find this feature
@@ -144,45 +214,79 @@ struct riscv_register_feature
std::vector<struct register_info> registers;
};
+/* See description in the class declaration above. */
+
+bool
+riscv_register_feature::register_info::check
+ (struct tdesc_arch_data *tdesc_data,
+ const struct tdesc_feature *feature,
+ const struct riscv_register_feature *reg_set,
+ std::vector<riscv_pending_register_alias> *aliases) const
+{
+ for (const char *name : this->names)
+ {
+ bool found = tdesc_numbered_register (feature, tdesc_data,
+ this->regnum, name);
+ if (found)
+ {
+ /* We know that the target description mentions this
+ register. In RISCV_REGISTER_NAME we ensure that GDB
+ always uses the first name for each register, so here we
+ add aliases for all of the remaining names. */
+ bool prefer_first_name = reg_set->prefer_first_name;
+ int start_index = prefer_first_name ? 1 : 0;
+ for (int i = start_index; i < this->names.size (); ++i)
+ {
+ const char *alias = this->names[i];
+ if (alias == name && !prefer_first_name)
+ continue;
+ aliases->emplace_back (alias, (void *)&this->regnum);
+ }
+ return true;
+ }
+ }
+ return false;
+}
+
/* The general x-registers feature set. */
static const struct riscv_register_feature riscv_xreg_feature =
{
"org.gnu.gdb.riscv.cpu", true,
{
- { RISCV_ZERO_REGNUM + 0, { "zero", "x0" }, true },
- { RISCV_ZERO_REGNUM + 1, { "ra", "x1" }, true },
- { RISCV_ZERO_REGNUM + 2, { "sp", "x2" }, true },
- { RISCV_ZERO_REGNUM + 3, { "gp", "x3" }, true },
- { RISCV_ZERO_REGNUM + 4, { "tp", "x4" }, true },
- { RISCV_ZERO_REGNUM + 5, { "t0", "x5" }, true },
- { RISCV_ZERO_REGNUM + 6, { "t1", "x6" }, true },
- { RISCV_ZERO_REGNUM + 7, { "t2", "x7" }, true },
- { RISCV_ZERO_REGNUM + 8, { "fp", "x8", "s0" }, true },
- { RISCV_ZERO_REGNUM + 9, { "s1", "x9" }, true },
- { RISCV_ZERO_REGNUM + 10, { "a0", "x10" }, true },
- { RISCV_ZERO_REGNUM + 11, { "a1", "x11" }, true },
- { RISCV_ZERO_REGNUM + 12, { "a2", "x12" }, true },
- { RISCV_ZERO_REGNUM + 13, { "a3", "x13" }, true },
- { RISCV_ZERO_REGNUM + 14, { "a4", "x14" }, true },
- { RISCV_ZERO_REGNUM + 15, { "a5", "x15" }, true },
- { RISCV_ZERO_REGNUM + 16, { "a6", "x16" }, true },
- { RISCV_ZERO_REGNUM + 17, { "a7", "x17" }, true },
- { RISCV_ZERO_REGNUM + 18, { "s2", "x18" }, true },
- { RISCV_ZERO_REGNUM + 19, { "s3", "x19" }, true },
- { RISCV_ZERO_REGNUM + 20, { "s4", "x20" }, true },
- { RISCV_ZERO_REGNUM + 21, { "s5", "x21" }, true },
- { RISCV_ZERO_REGNUM + 22, { "s6", "x22" }, true },
- { RISCV_ZERO_REGNUM + 23, { "s7", "x23" }, true },
- { RISCV_ZERO_REGNUM + 24, { "s8", "x24" }, true },
- { RISCV_ZERO_REGNUM + 25, { "s9", "x25" }, true },
- { RISCV_ZERO_REGNUM + 26, { "s10", "x26" }, true },
- { RISCV_ZERO_REGNUM + 27, { "s11", "x27" }, true },
- { RISCV_ZERO_REGNUM + 28, { "t3", "x28" }, true },
- { RISCV_ZERO_REGNUM + 29, { "t4", "x29" }, true },
- { RISCV_ZERO_REGNUM + 30, { "t5", "x30" }, true },
- { RISCV_ZERO_REGNUM + 31, { "t6", "x31" }, true },
- { RISCV_ZERO_REGNUM + 32, { "pc" }, true }
+ { RISCV_ZERO_REGNUM + 0, { "zero", "x0" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 1, { "ra", "x1" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 2, { "sp", "x2" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 3, { "gp", "x3" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 4, { "tp", "x4" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 5, { "t0", "x5" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 6, { "t1", "x6" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 7, { "t2", "x7" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 8, { "fp", "x8", "s0" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 9, { "s1", "x9" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 10, { "a0", "x10" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 11, { "a1", "x11" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 12, { "a2", "x12" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 13, { "a3", "x13" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 14, { "a4", "x14" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 15, { "a5", "x15" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 16, { "a6", "x16" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 17, { "a7", "x17" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 18, { "s2", "x18" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 19, { "s3", "x19" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 20, { "s4", "x20" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 21, { "s5", "x21" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 22, { "s6", "x22" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 23, { "s7", "x23" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 24, { "s8", "x24" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 25, { "s9", "x25" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 26, { "s10", "x26" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 27, { "s11", "x27" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 28, { "t3", "x28" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 29, { "t4", "x29" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 30, { "t5", "x30" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 31, { "t6", "x31" }, RISCV_REG_REQUIRED },
+ { RISCV_ZERO_REGNUM + 32, { "pc" }, RISCV_REG_REQUIRED }
}
};
@@ -192,42 +296,42 @@ static const struct riscv_register_feature riscv_freg_feature =
{
"org.gnu.gdb.riscv.fpu", true,
{
- { RISCV_FIRST_FP_REGNUM + 0, { "ft0", "f0" }, true },
- { RISCV_FIRST_FP_REGNUM + 1, { "ft1", "f1" }, true },
- { RISCV_FIRST_FP_REGNUM + 2, { "ft2", "f2" }, true },
- { RISCV_FIRST_FP_REGNUM + 3, { "ft3", "f3" }, true },
- { RISCV_FIRST_FP_REGNUM + 4, { "ft4", "f4" }, true },
- { RISCV_FIRST_FP_REGNUM + 5, { "ft5", "f5" }, true },
- { RISCV_FIRST_FP_REGNUM + 6, { "ft6", "f6" }, true },
- { RISCV_FIRST_FP_REGNUM + 7, { "ft7", "f7" }, true },
- { RISCV_FIRST_FP_REGNUM + 8, { "fs0", "f8" }, true },
- { RISCV_FIRST_FP_REGNUM + 9, { "fs1", "f9" }, true },
- { RISCV_FIRST_FP_REGNUM + 10, { "fa0", "f10" }, true },
- { RISCV_FIRST_FP_REGNUM + 11, { "fa1", "f11" }, true },
- { RISCV_FIRST_FP_REGNUM + 12, { "fa2", "f12" }, true },
- { RISCV_FIRST_FP_REGNUM + 13, { "fa3", "f13" }, true },
- { RISCV_FIRST_FP_REGNUM + 14, { "fa4", "f14" }, true },
- { RISCV_FIRST_FP_REGNUM + 15, { "fa5", "f15" }, true },
- { RISCV_FIRST_FP_REGNUM + 16, { "fa6", "f16" }, true },
- { RISCV_FIRST_FP_REGNUM + 17, { "fa7", "f17" }, true },
- { RISCV_FIRST_FP_REGNUM + 18, { "fs2", "f18" }, true },
- { RISCV_FIRST_FP_REGNUM + 19, { "fs3", "f19" }, true },
- { RISCV_FIRST_FP_REGNUM + 20, { "fs4", "f20" }, true },
- { RISCV_FIRST_FP_REGNUM + 21, { "fs5", "f21" }, true },
- { RISCV_FIRST_FP_REGNUM + 22, { "fs6", "f22" }, true },
- { RISCV_FIRST_FP_REGNUM + 23, { "fs7", "f23" }, true },
- { RISCV_FIRST_FP_REGNUM + 24, { "fs8", "f24" }, true },
- { RISCV_FIRST_FP_REGNUM + 25, { "fs9", "f25" }, true },
- { RISCV_FIRST_FP_REGNUM + 26, { "fs10", "f26" }, true },
- { RISCV_FIRST_FP_REGNUM + 27, { "fs11", "f27" }, true },
- { RISCV_FIRST_FP_REGNUM + 28, { "ft8", "f28" }, true },
- { RISCV_FIRST_FP_REGNUM + 29, { "ft9", "f29" }, true },
- { RISCV_FIRST_FP_REGNUM + 30, { "ft10", "f30" }, true },
- { RISCV_FIRST_FP_REGNUM + 31, { "ft11", "f31" }, true },
-
- { RISCV_CSR_FFLAGS_REGNUM, { "fflags" }, true },
- { RISCV_CSR_FRM_REGNUM, { "frm" }, true },
- { RISCV_CSR_FCSR_REGNUM, { "fcsr" }, true },
+ { RISCV_FIRST_FP_REGNUM + 0, { "ft0", "f0" }, RISCV_REG_REQUIRED },
+ { RISCV_FIRST_FP_REGNUM + 1, { "ft1", "f1" }, RISCV_REG_REQUIRED },
+ { RISCV_FIRST_FP_REGNUM + 2, { "ft2", "f2" }, RISCV_REG_REQUIRED },
+ { RISCV_FIRST_FP_REGNUM + 3, { "ft3", "f3" }, RISCV_REG_REQUIRED },
+ { RISCV_FIRST_FP_REGNUM + 4, { "ft4", "f4" }, RISCV_REG_REQUIRED },
+ { RISCV_FIRST_FP_REGNUM + 5, { "ft5", "f5" }, RISCV_REG_REQUIRED },
+ { RISCV_FIRST_FP_REGNUM + 6, { "ft6", "f6" }, RISCV_REG_REQUIRED },
+ { RISCV_FIRST_FP_REGNUM + 7, { "ft7", "f7" }, RISCV_REG_REQUIRED },
+ { RISCV_FIRST_FP_REGNUM + 8, { "fs0", "f8" }, RISCV_REG_REQUIRED },
+ { RISCV_FIRST_FP_REGNUM + 9, { "fs1", "f9" }, RISCV_REG_REQUIRED },
+ { RISCV_FIRST_FP_REGNUM + 10, { "fa0", "f10" }, RISCV_REG_REQUIRED },
+ { RISCV_FIRST_FP_REGNUM + 11, { "fa1", "f11" }, RISCV_REG_REQUIRED },
+ { RISCV_FIRST_FP_REGNUM + 12, { "fa2", "f12" }, RISCV_REG_REQUIRED },
+ { RISCV_FIRST_FP_REGNUM + 13, { "fa3", "f13" }, RISCV_REG_REQUIRED },
+ { RISCV_FIRST_FP_REGNUM + 14, { "fa4", "f14" }, RISCV_REG_REQUIRED },
+ { RISCV_FIRST_FP_REGNUM + 15, { "fa5", "f15" }, RISCV_REG_REQUIRED },
+ { RISCV_FIRST_FP_REGNUM + 16, { "fa6", "f16" }, RISCV_REG_REQUIRED },
+ { RISCV_FIRST_FP_REGNUM + 17, { "fa7", "f17" }, RISCV_REG_REQUIRED },
+ { RISCV_FIRST_FP_REGNUM + 18, { "fs2", "f18" }, RISCV_REG_REQUIRED },
+ { RISCV_FIRST_FP_REGNUM + 19, { "fs3", "f19" }, RISCV_REG_REQUIRED },
+ { RISCV_FIRST_FP_REGNUM + 20, { "fs4", "f20" }, RISCV_REG_REQUIRED },
+ { RISCV_FIRST_FP_REGNUM + 21, { "fs5", "f21" }, RISCV_REG_REQUIRED },
+ { RISCV_FIRST_FP_REGNUM + 22, { "fs6", "f22" }, RISCV_REG_REQUIRED },
+ { RISCV_FIRST_FP_REGNUM + 23, { "fs7", "f23" }, RISCV_REG_REQUIRED },
+ { RISCV_FIRST_FP_REGNUM + 24, { "fs8", "f24" }, RISCV_REG_REQUIRED },
+ { RISCV_FIRST_FP_REGNUM + 25, { "fs9", "f25" }, RISCV_REG_REQUIRED },
+ { RISCV_FIRST_FP_REGNUM + 26, { "fs10", "f26" }, RISCV_REG_REQUIRED },
+ { RISCV_FIRST_FP_REGNUM + 27, { "fs11", "f27" }, RISCV_REG_REQUIRED },
+ { RISCV_FIRST_FP_REGNUM + 28, { "ft8", "f28" }, RISCV_REG_REQUIRED },
+ { RISCV_FIRST_FP_REGNUM + 29, { "ft9", "f29" }, RISCV_REG_REQUIRED },
+ { RISCV_FIRST_FP_REGNUM + 30, { "ft10", "f30" }, RISCV_REG_REQUIRED },
+ { RISCV_FIRST_FP_REGNUM + 31, { "ft11", "f31" }, RISCV_REG_REQUIRED },
+
+ { RISCV_CSR_FFLAGS_REGNUM, { "fflags", "csr1" }, RISCV_REG_REQUIRED_MAYBE_CSR },
+ { RISCV_CSR_FRM_REGNUM, { "frm", "csr2" }, RISCV_REG_REQUIRED_MAYBE_CSR },
+ { RISCV_CSR_FCSR_REGNUM, { "fcsr", "csr3" }, RISCV_REG_REQUIRED_MAYBE_CSR },
}
};
@@ -242,7 +346,7 @@ static const struct riscv_register_feature riscv_virtual_feature =
{
"org.gnu.gdb.riscv.virtual", false,
{
- { RISCV_PRIV_REGNUM, { "priv" }, false }
+ { RISCV_PRIV_REGNUM, { "priv" }, RISCV_REG_OPTIONAL }
}
};
@@ -255,7 +359,7 @@ static struct riscv_register_feature riscv_csr_feature =
"org.gnu.gdb.riscv.csr", false,
{
#define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER) \
- { RISCV_ ## VALUE ## _REGNUM, { # NAME }, false },
+ { RISCV_ ## VALUE ## _REGNUM, { # NAME }, RISCV_REG_OPTIONAL },
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
}
@@ -475,15 +579,6 @@ riscv_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
}
}
-/* Callback function for user_reg_add. */
-
-static struct value *
-value_of_riscv_user_reg (struct frame_info *frame, const void *baton)
-{
- const int *reg_p = (const int *) baton;
- return value_of_register (*reg_p, frame);
-}
-
/* Implement the register_name gdbarch method. This is used instead of
the function supplied by calling TDESC_USE_REGISTERS so that we can
ensure the preferred names are offered for x-regs and f-regs. */
@@ -2965,37 +3060,6 @@ riscv_find_default_target_description (const struct gdbarch_info info)
return riscv_lookup_target_description (features);
}
-/* Information about a register alias that needs to be set up for this
- target. These are collected when the target's XML description is
- analysed, and then processed later, once the gdbarch has been created. */
-
-class riscv_pending_register_alias
-{
-public:
- /* Constructor. */
-
- riscv_pending_register_alias (const char *name, const void *baton)
- : m_name (name),
- m_baton (baton)
- { /* Nothing. */ }
-
- /* Convert this into a user register for GDBARCH. */
-
- void create (struct gdbarch *gdbarch) const
- {
- user_reg_add (gdbarch, m_name, value_of_riscv_user_reg, m_baton);
- }
-
-private:
- /* The name for this alias. */
- const char *m_name;
-
- /* The baton value for passing to user_reg_add. This must point to some
- data that will live for at least as long as the gdbarch object to
- which the user register is attached. */
- const void *m_baton;
-};
-
/* All of the registers in REG_SET are checked for in FEATURE, TDESC_DATA
is updated with the register numbers for each register as listed in
REG_SET. If any register marked as required in REG_SET is not found in
@@ -3003,40 +3067,26 @@ class riscv_pending_register_alias
static bool
riscv_check_tdesc_feature (struct tdesc_arch_data *tdesc_data,
- const struct tdesc_feature *feature,
+ const struct tdesc_feature *main_feature,
+ const struct tdesc_feature *csr_feature,
const struct riscv_register_feature *reg_set,
std::vector<riscv_pending_register_alias> *aliases)
{
for (const auto ® : reg_set->registers)
{
- bool found = false;
+ bool found = reg.check (tdesc_data, main_feature, reg_set, aliases);
- for (const char *name : reg.names)
+ if (!found && reg.required != RISCV_REG_OPTIONAL)
{
- found = tdesc_numbered_register (feature, tdesc_data, reg.regnum,
- name);
-
- if (found)
- {
- /* We know that the target description mentions this
- register. In RISCV_REGISTER_NAME we ensure that GDB
- always uses the first name for each register, so here we
- add aliases for all of the remaining names. */
- bool prefer_first_name = reg_set->prefer_first_name;
- int start_index = prefer_first_name ? 1 : 0;
- for (int i = start_index; i < reg.names.size (); ++i)
- {
- const char *alias = reg.names[i];
- if (alias == name && !prefer_first_name)
- continue;
- aliases->emplace_back (alias, (void *)®.regnum);
- }
- break;
- }
+ if (reg.required == RISCV_REG_REQUIRED_MAYBE_CSR
+ && csr_feature != nullptr)
+ {
+ gdb_assert (main_feature != csr_feature);
+ found = reg.check (tdesc_data, csr_feature, reg_set, aliases);
+ }
+ if (!found)
+ return false;
}
-
- if (!found && reg.required_p)
- return false;
}
return true;
@@ -3166,7 +3216,7 @@ riscv_gdbarch_init (struct gdbarch_info info,
std::vector<riscv_pending_register_alias> pending_aliases;
bool valid_p = riscv_check_tdesc_feature (tdesc_data,
- feature_cpu,
+ feature_cpu, feature_csr,
&riscv_xreg_feature,
&pending_aliases);
if (valid_p)
@@ -3188,6 +3238,7 @@ riscv_gdbarch_init (struct gdbarch_info info,
if (feature_fpu != NULL)
{
valid_p &= riscv_check_tdesc_feature (tdesc_data, feature_fpu,
+ feature_csr,
&riscv_freg_feature,
&pending_aliases);
@@ -3224,12 +3275,12 @@ riscv_gdbarch_init (struct gdbarch_info info,
}
if (feature_virtual)
- riscv_check_tdesc_feature (tdesc_data, feature_virtual,
+ riscv_check_tdesc_feature (tdesc_data, feature_virtual, feature_csr,
&riscv_virtual_feature,
&pending_aliases);
if (feature_csr)
- riscv_check_tdesc_feature (tdesc_data, feature_csr,
+ riscv_check_tdesc_feature (tdesc_data, feature_csr, nullptr,
&riscv_csr_feature,
&pending_aliases);
diff --git a/gdb/testsuite/gdb.arch/riscv-tdesc-loading-01.xml b/gdb/testsuite/gdb.arch/riscv-tdesc-loading-01.xml
new file mode 100644
index 00000000000..39bde201c63
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/riscv-tdesc-loading-01.xml
@@ -0,0 +1,83 @@
+<?xml version="1.0"?>
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+ <architecture>riscv</architecture>
+ <feature name="org.gnu.gdb.riscv.cpu">
+ <reg name="zero" bitsize="64" type="int"/>
+ <reg name="ra" bitsize="64" type="code_ptr"/>
+ <reg name="sp" bitsize="64" type="data_ptr"/>
+ <reg name="gp" bitsize="64" type="data_ptr"/>
+ <reg name="tp" bitsize="64" type="data_ptr"/>
+ <reg name="t0" bitsize="64" type="int"/>
+ <reg name="t1" bitsize="64" type="int"/>
+ <reg name="t2" bitsize="64" type="int"/>
+ <reg name="fp" bitsize="64" type="data_ptr"/>
+ <reg name="s1" bitsize="64" type="int"/>
+ <reg name="a0" bitsize="64" type="int"/>
+ <reg name="a1" bitsize="64" type="int"/>
+ <reg name="a2" bitsize="64" type="int"/>
+ <reg name="a3" bitsize="64" type="int"/>
+ <reg name="a4" bitsize="64" type="int"/>
+ <reg name="a5" bitsize="64" type="int"/>
+ <reg name="a6" bitsize="64" type="int"/>
+ <reg name="a7" bitsize="64" type="int"/>
+ <reg name="s2" bitsize="64" type="int"/>
+ <reg name="s3" bitsize="64" type="int"/>
+ <reg name="s4" bitsize="64" type="int"/>
+ <reg name="s5" bitsize="64" type="int"/>
+ <reg name="s6" bitsize="64" type="int"/>
+ <reg name="s7" bitsize="64" type="int"/>
+ <reg name="s8" bitsize="64" type="int"/>
+ <reg name="s9" bitsize="64" type="int"/>
+ <reg name="s10" bitsize="64" type="int"/>
+ <reg name="s11" bitsize="64" type="int"/>
+ <reg name="t3" bitsize="64" type="int"/>
+ <reg name="t4" bitsize="64" type="int"/>
+ <reg name="t5" bitsize="64" type="int"/>
+ <reg name="t6" bitsize="64" type="int"/>
+ <reg name="pc" bitsize="64" type="code_ptr"/>
+ </feature>
+ <feature name="org.gnu.gdb.riscv.fpu">
+ <union id="riscv_double">
+ <field name="float" type="ieee_single"/>
+ <field name="double" type="ieee_double"/>
+ </union>
+ <reg name="ft0" bitsize="64" type="riscv_double"/>
+ <reg name="ft1" bitsize="64" type="riscv_double"/>
+ <reg name="ft2" bitsize="64" type="riscv_double"/>
+ <reg name="ft3" bitsize="64" type="riscv_double"/>
+ <reg name="ft4" bitsize="64" type="riscv_double"/>
+ <reg name="ft5" bitsize="64" type="riscv_double"/>
+ <reg name="ft6" bitsize="64" type="riscv_double"/>
+ <reg name="ft7" bitsize="64" type="riscv_double"/>
+ <reg name="fs0" bitsize="64" type="riscv_double"/>
+ <reg name="fs1" bitsize="64" type="riscv_double"/>
+ <reg name="fa0" bitsize="64" type="riscv_double"/>
+ <reg name="fa1" bitsize="64" type="riscv_double"/>
+ <reg name="fa2" bitsize="64" type="riscv_double"/>
+ <reg name="fa3" bitsize="64" type="riscv_double"/>
+ <reg name="fa4" bitsize="64" type="riscv_double"/>
+ <reg name="fa5" bitsize="64" type="riscv_double"/>
+ <reg name="fa6" bitsize="64" type="riscv_double"/>
+ <reg name="fa7" bitsize="64" type="riscv_double"/>
+ <reg name="fs2" bitsize="64" type="riscv_double"/>
+ <reg name="fs3" bitsize="64" type="riscv_double"/>
+ <reg name="fs4" bitsize="64" type="riscv_double"/>
+ <reg name="fs5" bitsize="64" type="riscv_double"/>
+ <reg name="fs6" bitsize="64" type="riscv_double"/>
+ <reg name="fs7" bitsize="64" type="riscv_double"/>
+ <reg name="fs8" bitsize="64" type="riscv_double"/>
+ <reg name="fs9" bitsize="64" type="riscv_double"/>
+ <reg name="fs10" bitsize="64" type="riscv_double"/>
+ <reg name="fs11" bitsize="64" type="riscv_double"/>
+ <reg name="ft8" bitsize="64" type="riscv_double"/>
+ <reg name="ft9" bitsize="64" type="riscv_double"/>
+ <reg name="ft10" bitsize="64" type="riscv_double"/>
+ <reg name="ft11" bitsize="64" type="riscv_double"/>
+ </feature>
+ <feature name="org.gnu.gdb.riscv.csr">
+ <reg name="fflags" bitsize="32" type="int"/>
+ <reg name="frm" bitsize="32" type="int"/>
+ <reg name="fcsr" bitsize="32" type="int"/>
+ </feature>
+</target>
diff --git a/gdb/testsuite/gdb.arch/riscv-tdesc-loading-02.xml b/gdb/testsuite/gdb.arch/riscv-tdesc-loading-02.xml
new file mode 100644
index 00000000000..db0771b863a
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/riscv-tdesc-loading-02.xml
@@ -0,0 +1,81 @@
+<?xml version="1.0"?>
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+ <architecture>riscv</architecture>
+ <feature name="org.gnu.gdb.riscv.cpu">
+ <reg name="zero" bitsize="64" type="int"/>
+ <reg name="ra" bitsize="64" type="code_ptr"/>
+ <reg name="sp" bitsize="64" type="data_ptr"/>
+ <reg name="gp" bitsize="64" type="data_ptr"/>
+ <reg name="tp" bitsize="64" type="data_ptr"/>
+ <reg name="t0" bitsize="64" type="int"/>
+ <reg name="t1" bitsize="64" type="int"/>
+ <reg name="t2" bitsize="64" type="int"/>
+ <reg name="fp" bitsize="64" type="data_ptr"/>
+ <reg name="s1" bitsize="64" type="int"/>
+ <reg name="a0" bitsize="64" type="int"/>
+ <reg name="a1" bitsize="64" type="int"/>
+ <reg name="a2" bitsize="64" type="int"/>
+ <reg name="a3" bitsize="64" type="int"/>
+ <reg name="a4" bitsize="64" type="int"/>
+ <reg name="a5" bitsize="64" type="int"/>
+ <reg name="a6" bitsize="64" type="int"/>
+ <reg name="a7" bitsize="64" type="int"/>
+ <reg name="s2" bitsize="64" type="int"/>
+ <reg name="s3" bitsize="64" type="int"/>
+ <reg name="s4" bitsize="64" type="int"/>
+ <reg name="s5" bitsize="64" type="int"/>
+ <reg name="s6" bitsize="64" type="int"/>
+ <reg name="s7" bitsize="64" type="int"/>
+ <reg name="s8" bitsize="64" type="int"/>
+ <reg name="s9" bitsize="64" type="int"/>
+ <reg name="s10" bitsize="64" type="int"/>
+ <reg name="s11" bitsize="64" type="int"/>
+ <reg name="t3" bitsize="64" type="int"/>
+ <reg name="t4" bitsize="64" type="int"/>
+ <reg name="t5" bitsize="64" type="int"/>
+ <reg name="t6" bitsize="64" type="int"/>
+ <reg name="pc" bitsize="64" type="code_ptr"/>
+ </feature>
+ <feature name="org.gnu.gdb.riscv.fpu">
+ <union id="riscv_double">
+ <field name="float" type="ieee_single"/>
+ <field name="double" type="ieee_double"/>
+ </union>
+ <reg name="ft0" bitsize="64" type="riscv_double"/>
+ <reg name="ft1" bitsize="64" type="riscv_double"/>
+ <reg name="ft2" bitsize="64" type="riscv_double"/>
+ <reg name="ft3" bitsize="64" type="riscv_double"/>
+ <reg name="ft4" bitsize="64" type="riscv_double"/>
+ <reg name="ft5" bitsize="64" type="riscv_double"/>
+ <reg name="ft6" bitsize="64" type="riscv_double"/>
+ <reg name="ft7" bitsize="64" type="riscv_double"/>
+ <reg name="fs0" bitsize="64" type="riscv_double"/>
+ <reg name="fs1" bitsize="64" type="riscv_double"/>
+ <reg name="fa0" bitsize="64" type="riscv_double"/>
+ <reg name="fa1" bitsize="64" type="riscv_double"/>
+ <reg name="fa2" bitsize="64" type="riscv_double"/>
+ <reg name="fa3" bitsize="64" type="riscv_double"/>
+ <reg name="fa4" bitsize="64" type="riscv_double"/>
+ <reg name="fa5" bitsize="64" type="riscv_double"/>
+ <reg name="fa6" bitsize="64" type="riscv_double"/>
+ <reg name="fa7" bitsize="64" type="riscv_double"/>
+ <reg name="fs2" bitsize="64" type="riscv_double"/>
+ <reg name="fs3" bitsize="64" type="riscv_double"/>
+ <reg name="fs4" bitsize="64" type="riscv_double"/>
+ <reg name="fs5" bitsize="64" type="riscv_double"/>
+ <reg name="fs6" bitsize="64" type="riscv_double"/>
+ <reg name="fs7" bitsize="64" type="riscv_double"/>
+ <reg name="fs8" bitsize="64" type="riscv_double"/>
+ <reg name="fs9" bitsize="64" type="riscv_double"/>
+ <reg name="fs10" bitsize="64" type="riscv_double"/>
+ <reg name="fs11" bitsize="64" type="riscv_double"/>
+ <reg name="ft8" bitsize="64" type="riscv_double"/>
+ <reg name="ft9" bitsize="64" type="riscv_double"/>
+ <reg name="ft10" bitsize="64" type="riscv_double"/>
+ <reg name="ft11" bitsize="64" type="riscv_double"/>
+ <reg name="fflags" bitsize="32" type="int"/>
+ <reg name="frm" bitsize="32" type="int"/>
+ <reg name="fcsr" bitsize="32" type="int"/>
+ </feature>
+</target>
diff --git a/gdb/testsuite/gdb.arch/riscv-tdesc-loading-03.xml b/gdb/testsuite/gdb.arch/riscv-tdesc-loading-03.xml
new file mode 100644
index 00000000000..b4af362c196
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/riscv-tdesc-loading-03.xml
@@ -0,0 +1,79 @@
+<?xml version="1.0"?>
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+ <architecture>riscv</architecture>
+ <feature name="org.gnu.gdb.riscv.cpu">
+ <reg name="zero" bitsize="32" type="int"/>
+ <reg name="ra" bitsize="32" type="code_ptr"/>
+ <reg name="sp" bitsize="32" type="data_ptr"/>
+ <reg name="gp" bitsize="32" type="data_ptr"/>
+ <reg name="tp" bitsize="32" type="data_ptr"/>
+ <reg name="t0" bitsize="32" type="int"/>
+ <reg name="t1" bitsize="32" type="int"/>
+ <reg name="t2" bitsize="32" type="int"/>
+ <reg name="fp" bitsize="32" type="data_ptr"/>
+ <reg name="s1" bitsize="32" type="int"/>
+ <reg name="a0" bitsize="32" type="int"/>
+ <reg name="a1" bitsize="32" type="int"/>
+ <reg name="a2" bitsize="32" type="int"/>
+ <reg name="a3" bitsize="32" type="int"/>
+ <reg name="a4" bitsize="32" type="int"/>
+ <reg name="a5" bitsize="32" type="int"/>
+ <reg name="a6" bitsize="32" type="int"/>
+ <reg name="a7" bitsize="32" type="int"/>
+ <reg name="s2" bitsize="32" type="int"/>
+ <reg name="s3" bitsize="32" type="int"/>
+ <reg name="s4" bitsize="32" type="int"/>
+ <reg name="s5" bitsize="32" type="int"/>
+ <reg name="s6" bitsize="32" type="int"/>
+ <reg name="s7" bitsize="32" type="int"/>
+ <reg name="s8" bitsize="32" type="int"/>
+ <reg name="s9" bitsize="32" type="int"/>
+ <reg name="s10" bitsize="32" type="int"/>
+ <reg name="s11" bitsize="32" type="int"/>
+ <reg name="t3" bitsize="32" type="int"/>
+ <reg name="t4" bitsize="32" type="int"/>
+ <reg name="t5" bitsize="32" type="int"/>
+ <reg name="t6" bitsize="32" type="int"/>
+ <reg name="pc" bitsize="32" type="code_ptr"/>
+ </feature>
+ <feature name="org.gnu.gdb.riscv.fpu">
+ <reg name="ft0" bitsize="32" type="float"/>
+ <reg name="ft1" bitsize="32" type="float"/>
+ <reg name="ft2" bitsize="32" type="float"/>
+ <reg name="ft3" bitsize="32" type="float"/>
+ <reg name="ft4" bitsize="32" type="float"/>
+ <reg name="ft5" bitsize="32" type="float"/>
+ <reg name="ft6" bitsize="32" type="float"/>
+ <reg name="ft7" bitsize="32" type="float"/>
+ <reg name="fs0" bitsize="32" type="float"/>
+ <reg name="fs1" bitsize="32" type="float"/>
+ <reg name="fa0" bitsize="32" type="float"/>
+ <reg name="fa1" bitsize="32" type="float"/>
+ <reg name="fa2" bitsize="32" type="float"/>
+ <reg name="fa3" bitsize="32" type="float"/>
+ <reg name="fa4" bitsize="32" type="float"/>
+ <reg name="fa5" bitsize="32" type="float"/>
+ <reg name="fa6" bitsize="32" type="float"/>
+ <reg name="fa7" bitsize="32" type="float"/>
+ <reg name="fs2" bitsize="32" type="float"/>
+ <reg name="fs3" bitsize="32" type="float"/>
+ <reg name="fs4" bitsize="32" type="float"/>
+ <reg name="fs5" bitsize="32" type="float"/>
+ <reg name="fs6" bitsize="32" type="float"/>
+ <reg name="fs7" bitsize="32" type="float"/>
+ <reg name="fs8" bitsize="32" type="float"/>
+ <reg name="fs9" bitsize="32" type="float"/>
+ <reg name="fs10" bitsize="32" type="float"/>
+ <reg name="fs11" bitsize="32" type="float"/>
+ <reg name="ft8" bitsize="32" type="float"/>
+ <reg name="ft9" bitsize="32" type="float"/>
+ <reg name="ft10" bitsize="32" type="float"/>
+ <reg name="ft11" bitsize="32" type="float"/>
+ </feature>
+ <feature name="org.gnu.gdb.riscv.csr">
+ <reg name="fflags" bitsize="32" type="int"/>
+ <reg name="frm" bitsize="32" type="int"/>
+ <reg name="fcsr" bitsize="32" type="int"/>
+ </feature>
+</target>
diff --git a/gdb/testsuite/gdb.arch/riscv-tdesc-loading-04.xml b/gdb/testsuite/gdb.arch/riscv-tdesc-loading-04.xml
new file mode 100644
index 00000000000..d44d7e27d87
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/riscv-tdesc-loading-04.xml
@@ -0,0 +1,77 @@
+<?xml version="1.0"?>
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+ <architecture>riscv</architecture>
+ <feature name="org.gnu.gdb.riscv.cpu">
+ <reg name="zero" bitsize="32" type="int"/>
+ <reg name="ra" bitsize="32" type="code_ptr"/>
+ <reg name="sp" bitsize="32" type="data_ptr"/>
+ <reg name="gp" bitsize="32" type="data_ptr"/>
+ <reg name="tp" bitsize="32" type="data_ptr"/>
+ <reg name="t0" bitsize="32" type="int"/>
+ <reg name="t1" bitsize="32" type="int"/>
+ <reg name="t2" bitsize="32" type="int"/>
+ <reg name="fp" bitsize="32" type="data_ptr"/>
+ <reg name="s1" bitsize="32" type="int"/>
+ <reg name="a0" bitsize="32" type="int"/>
+ <reg name="a1" bitsize="32" type="int"/>
+ <reg name="a2" bitsize="32" type="int"/>
+ <reg name="a3" bitsize="32" type="int"/>
+ <reg name="a4" bitsize="32" type="int"/>
+ <reg name="a5" bitsize="32" type="int"/>
+ <reg name="a6" bitsize="32" type="int"/>
+ <reg name="a7" bitsize="32" type="int"/>
+ <reg name="s2" bitsize="32" type="int"/>
+ <reg name="s3" bitsize="32" type="int"/>
+ <reg name="s4" bitsize="32" type="int"/>
+ <reg name="s5" bitsize="32" type="int"/>
+ <reg name="s6" bitsize="32" type="int"/>
+ <reg name="s7" bitsize="32" type="int"/>
+ <reg name="s8" bitsize="32" type="int"/>
+ <reg name="s9" bitsize="32" type="int"/>
+ <reg name="s10" bitsize="32" type="int"/>
+ <reg name="s11" bitsize="32" type="int"/>
+ <reg name="t3" bitsize="32" type="int"/>
+ <reg name="t4" bitsize="32" type="int"/>
+ <reg name="t5" bitsize="32" type="int"/>
+ <reg name="t6" bitsize="32" type="int"/>
+ <reg name="pc" bitsize="32" type="code_ptr"/>
+ </feature>
+ <feature name="org.gnu.gdb.riscv.fpu">
+ <reg name="ft0" bitsize="32" type="float"/>
+ <reg name="ft1" bitsize="32" type="float"/>
+ <reg name="ft2" bitsize="32" type="float"/>
+ <reg name="ft3" bitsize="32" type="float"/>
+ <reg name="ft4" bitsize="32" type="float"/>
+ <reg name="ft5" bitsize="32" type="float"/>
+ <reg name="ft6" bitsize="32" type="float"/>
+ <reg name="ft7" bitsize="32" type="float"/>
+ <reg name="fs0" bitsize="32" type="float"/>
+ <reg name="fs1" bitsize="32" type="float"/>
+ <reg name="fa0" bitsize="32" type="float"/>
+ <reg name="fa1" bitsize="32" type="float"/>
+ <reg name="fa2" bitsize="32" type="float"/>
+ <reg name="fa3" bitsize="32" type="float"/>
+ <reg name="fa4" bitsize="32" type="float"/>
+ <reg name="fa5" bitsize="32" type="float"/>
+ <reg name="fa6" bitsize="32" type="float"/>
+ <reg name="fa7" bitsize="32" type="float"/>
+ <reg name="fs2" bitsize="32" type="float"/>
+ <reg name="fs3" bitsize="32" type="float"/>
+ <reg name="fs4" bitsize="32" type="float"/>
+ <reg name="fs5" bitsize="32" type="float"/>
+ <reg name="fs6" bitsize="32" type="float"/>
+ <reg name="fs7" bitsize="32" type="float"/>
+ <reg name="fs8" bitsize="32" type="float"/>
+ <reg name="fs9" bitsize="32" type="float"/>
+ <reg name="fs10" bitsize="32" type="float"/>
+ <reg name="fs11" bitsize="32" type="float"/>
+ <reg name="ft8" bitsize="32" type="float"/>
+ <reg name="ft9" bitsize="32" type="float"/>
+ <reg name="ft10" bitsize="32" type="float"/>
+ <reg name="ft11" bitsize="32" type="float"/>
+ <reg name="fflags" bitsize="32" type="int"/>
+ <reg name="frm" bitsize="32" type="int"/>
+ <reg name="fcsr" bitsize="32" type="int"/>
+ </feature>
+</target>
diff --git a/gdb/testsuite/gdb.arch/riscv-tdesc-loading.exp b/gdb/testsuite/gdb.arch/riscv-tdesc-loading.exp
new file mode 100644
index 00000000000..e11117280c3
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/riscv-tdesc-loading.exp
@@ -0,0 +1,39 @@
+# Copyright 2020 Free Software Foundation, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+# Check that we can load different RISC-V target descriptions.
+
+if {![istarget "riscv*-*-*"]} {
+ verbose "Skipping ${gdb_test_file_name}."
+ return
+}
+
+clean_restart
+
+# Run over every test XML file and check the target description can be
+# loaded.
+foreach filename [lsort [glob $srcdir/$subdir/riscv-tdesc-loading-*.xml]] {
+ if {[is_remote host]} {
+ set test_path [remote_download host $filename]
+ } else {
+ set test_path $filename
+ }
+
+ # Currently it is expected that all of the target descriptions in
+ # this test will load successfully, so we expect no additonal
+ # output from GDB.
+ gdb_test_no_output "set tdesc filename $test_path" \
+ "check [file tail $filename]"
+}
--
2.25.4
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