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([2001:8a0:f924:2600:209d:85e2:409e:8726]) by smtp.gmail.com with ESMTPSA id 7-20020a05600c024700b003a03e63e428sm457891wmj.36.2022.06.24.09.58.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Jun 2022 09:58:04 -0700 (PDT) Message-ID: Date: Fri, 24 Jun 2022 17:58:03 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [PATCHv3 3/6] gdb: select suitable thread for gdbarch_adjust_breakpoint_address Content-Language: en-US To: Andrew Burgess , gdb-patches@sourceware.org References: <9645de63bf2655cb1d03b5fde9ea0eb9379941f6.1655136816.git.aburgess@redhat.com> From: Pedro Alves In-Reply-To: <9645de63bf2655cb1d03b5fde9ea0eb9379941f6.1655136816.git.aburgess@redhat.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-10.1 required=5.0 tests=BAYES_00, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, NICE_REPLY_A, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 24 Jun 2022 16:58:08 -0000 On 2022-06-13 17:15, Andrew Burgess via Gdb-patches wrote: > --- > gdb/arm-tdep.c | 12 ++++++++---- > gdb/breakpoint.c | 24 ++++++++++++++++++------ > 2 files changed, 26 insertions(+), 10 deletions(-) > > diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c > index 7f27d4bd6e8..e0e5c7efd63 100644 > --- a/gdb/arm-tdep.c > +++ b/gdb/arm-tdep.c > @@ -541,20 +541,24 @@ arm_is_thumb (struct regcache *regcache) > return (cpsr & t_bit) != 0; > } > > -/* Determine if FRAME is executing in Thumb mode. */ > +/* Determine if FRAME is executing in Thumb mode. FRAME must be an ARM > + frame. */ > > int > arm_frame_is_thumb (struct frame_info *frame) > { > - CORE_ADDR cpsr; > - ULONGEST t_bit = arm_psr_thumb_bit (get_frame_arch (frame)); > + /* Check the architecture of FRAME. */ > + struct gdbarch *gdbarch = get_frame_arch (frame); > + gdb_assert (gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm); I think you wanted instead: gdb_assert (gdbarch_bfd_arch_info (gdbarch)->arch == bfd_arch_arm); ? > > /* Every ARM frame unwinder can unwind the T bit of the CPSR, either > directly (from a signal frame or dummy frame) or by interpreting > the saved LR (from a prologue or DWARF frame). So consult it and > trust the unwinders. */ > - cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM); > + CORE_ADDR cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM); > > + /* Find and extract the thumb bit. */ > + ULONGEST t_bit = arm_psr_thumb_bit (gdbarch); > return (cpsr & t_bit) != 0; > } > static CORE_ADDR > adjust_breakpoint_address (struct gdbarch *gdbarch, > - CORE_ADDR bpaddr, enum bptype bptype) > + CORE_ADDR bpaddr, enum bptype bptype, > + struct program_space *pspace) > { > + gdb_assert (pspace != nullptr); > + > if (bptype == bp_watchpoint > || bptype == bp_hardware_watchpoint > || bptype == bp_read_watchpoint > @@ -7140,10 +7144,16 @@ adjust_breakpoint_address (struct gdbarch *gdbarch, > { > CORE_ADDR adjusted_bpaddr = bpaddr; > > + /* Some targets have architectural constraints on the placement > + of breakpoint instructions. Obtain the adjusted address. */ > if (gdbarch_adjust_breakpoint_address_p (gdbarch)) > { > - /* Some targets have architectural constraints on the placement > - of breakpoint instructions. Obtain the adjusted address. */ > + /* Targets that implement this adjustment function will > + likely inspect either the symbol table, or target memory > + add BPADDR, so ensure a suitable thread (and its s/add BPADDR/at BPADDR/, I think. Note the comment as is doesn't justify why switch to a thread, as opposed to just switching the inferior (e.g., with switch_to_inferior_no_thread), as you can read memory without a thread selected (well, modulo a bug in linux-nat.c). We want a thread here for the arm fallback. I'd suggest extending the comment in that direction, like: "... or target memory at BPADDR, or even state registers." > + associated program space) are currently selected. */ > + scoped_restore_current_pspace_and_thread restore_pspace_thread; > + switch_to_program_space_and_thread (pspace); > adjusted_bpaddr = gdbarch_adjust_breakpoint_address (gdbarch, bpaddr); > } Otherwise LGTM.